阅读说明：本技术 电子装置、数据处理装置及电子设备 (Electronic device, data processing device and electronic equipment ) 是由 刘升鑫 于 2021-01-05 设计创作，主要内容包括：本公开涉及电子装置、数据处理装置及电子设备,所述装置包括第一NMOS晶体管、第二NMOS晶体管、第一PMOS晶体管、第二PMOS晶体管及电压保持单元,所述电子装置用于将属于第一电压范围的输入信号转换为属于第二电压范围的输出信号。本公开实施例提出的电子装置,当产生所述输入信号的第三电源电压在维持一段时间消失时,可以维持第一端的所述输出信号的反相信号的电位,并维持第二端的输出信号的电位,使得在其中一个电源停止工作时,保持输出信号的稳定,且,利用减少一个电源进行工作,可以降低功耗。(The present disclosure relates to an electronic device, a data processing device, and an electronic apparatus, the device including a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, and a voltage holding unit, the electronic device being configured to convert an input signal belonging to a first voltage range into an output signal belonging to a second voltage range. In the electronic device provided by the embodiment of the disclosure, when the third power voltage generating the input signal is maintained for a period of time and disappears, the potential of the inverted signal of the output signal at the first end can be maintained, and the potential of the output signal at the second end can be maintained, so that when one of the power supplies stops working, the stability of the output signal is maintained, and by reducing one power supply to work, the power consumption can be reduced.)

1. An electronic device comprising a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor and a voltage holding unit, for converting an input signal belonging to a first voltage range into an output signal belonging to a second voltage range, wherein,

the grid electrode of the first NMOS transistor is used for receiving input signals, the drain electrode of the first NMOS transistor is electrically connected with the drain electrode of the first PMOS transistor, the source electrode of the first NMOS transistor is grounded,

the gate of the second NMOS transistor is used for receiving the inverted signal of the input signal, the drain of the second NMOS transistor is electrically connected to the drain of the second PMOS transistor, the source of the second NMOS transistor is grounded,

the source electrode of the first PMOS transistor is electrically connected to the first end of the voltage holding unit, and the voltage signal of the first end of the voltage holding unit is the inverted signal of the output signal;

a source of the second PMOS transistor is electrically connected to the second terminal of the voltage holding unit for outputting the output signal,

the first power supply terminal of the voltage holding unit is used for inputting a first power supply voltage, the gate of the first PMOS transistor, the gate of the second PMOS transistor and the second power supply terminal of the voltage holding unit are used for inputting a second power supply voltage, wherein when a third power supply voltage generating the input signal disappears after being maintained for a period of time, the voltage holding unit is used for maintaining the potential of the output signal and the potential of the inverted signal of the output signal.

2. The apparatus according to claim 1, further comprising a first inverter, wherein an input terminal of the first inverter is electrically connected to a gate of the first NMOS transistor, an output terminal of the first inverter is electrically connected to a gate of the second NMOS transistor, a power supply terminal of the first inverter is used for inputting the third power supply voltage, a ground terminal of the first inverter is grounded,

the first inverter is used for carrying out inversion processing on the input signal and outputting an inverted signal of the input signal.

3. The apparatus of claim 1, wherein the voltage holding unit comprises a second inverter and a third inverter, wherein the second inverter and the third inverter are cross-coupled.

4. The apparatus of claim 3, wherein the second inverter comprises a third NMOS transistor and a third PMOS transistor, and wherein the third inverter comprises a fourth NMOS transistor and a fourth PMOS transistor, and wherein:

a drain of the third NMOS transistor is electrically connected to a drain of the third PMOS transistor, a gate of the fourth NMOS transistor, a gate of the fourth PMOS transistor, and a source of the first PMOS transistor for generating an inverted signal of the output signal,

a gate of the third NMOS transistor is electrically connected to a gate of the third PMOS transistor, a drain of the fourth NMOS transistor, a drain of the fourth PMOS transistor, and a source of the second PMOS transistor for generating the output signal,

a source of the third NMOS transistor is electrically connected to a source of the fourth NMOS transistor, a gate of the first PMOS transistor, and a gate of the second PMOS transistor, for receiving the second power voltage,

the source electrode of the third PMOS transistor is electrically connected to the source electrode of the fourth PMOS transistor and used for receiving the first power supply voltage.

5. The apparatus of claim 1, wherein the voltage of the first power supply voltage is higher than the voltage of the second power supply voltage, and wherein the voltage of the second power supply voltage is higher than the voltage of the third power supply voltage.

6. The apparatus of claim 1, wherein source-drain channels of the first NMOS transistor, the second NMOS transistor, the first PMOS transistor, and the second PMOS transistor are capable of withstanding the first supply voltage.

7. The apparatus of claim 4, wherein source-drain channels of the third and fourth PMOS transistors are capable of withstanding a voltage between the first and second supply voltages.

8. A data processing apparatus, characterized in that the data processing apparatus comprises an electronic apparatus according to any of claims 1-7.

9. An electronic device, characterized in that the electronic device comprises the data processing apparatus as claimed in claim 8.

10. The electronic device of claim 9, wherein the electronic device comprises a portable computer, a smart handheld electronic device.

Technical Field

The present disclosure relates to the field of power management technologies, and in particular, to an electronic device, a data processing device, and an electronic apparatus.

Background

Electronic devices are commonly used in semiconductor circuits to convert signal levels in one voltage domain to different voltage levels in another domain. At present, the electronic device in the related art generally performs level conversion by using dual power sources, and when one of the power sources stops operating due to some reason, the electronic device in the related art cannot stably operate, an output signal is unstable, so that a problem that a through current flows through a subsequent circuit which operates according to the output signal occurs, and the electronic device in the related art has a problem of high power consumption when realizing its function.

Disclosure of Invention

In view of the above, the present disclosure provides an electronic device, a data processing device and an electronic apparatus, so as to solve the problems that when one of the power supplies stops operating for some reason, the electronic device cannot operate stably, and the output signal is unstable.

According to an aspect of the present disclosure, an electronic device is provided, the device comprising a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, and a voltage holding unit, the electronic device for converting an input signal belonging to a first voltage range into an output signal belonging to a second voltage range, wherein,

the grid electrode of the first NMOS transistor is used for receiving input signals, the drain electrode of the first NMOS transistor is electrically connected with the drain electrode of the first PMOS transistor, the source electrode of the first NMOS transistor is grounded,

the gate of the second NMOS transistor is used for receiving the inverted signal of the input signal, the drain of the second NMOS transistor is electrically connected to the drain of the second PMOS transistor, the source of the second NMOS transistor is grounded,

the source electrode of the first PMOS transistor is electrically connected to the first end of the voltage holding unit, and the voltage signal of the first end of the voltage holding unit is the inverted signal of the output signal;

a source of the second PMOS transistor is electrically connected to the second terminal of the voltage holding unit for outputting the output signal,

the first power supply terminal of the voltage holding unit is used for inputting a first power supply voltage, the gate of the first PMOS transistor, the gate of the second PMOS transistor and the second power supply terminal of the voltage holding unit are used for inputting a second power supply voltage, wherein when a third power supply voltage generating the input signal disappears after being maintained for a period of time, the voltage holding unit is used for maintaining the potential of the output signal and the potential of the inverted signal of the output signal.

In a possible implementation manner, the apparatus further includes a first inverter, an input terminal of the first inverter is electrically connected to the gate of the first NMOS transistor, an output terminal of the first inverter is electrically connected to the gate of the second NMOS transistor, a power supply terminal of the first inverter is used for inputting the third power supply voltage, a ground terminal of the first inverter is grounded,

the first inverter is used for carrying out inversion processing on the input signal and outputting an inverted signal of the input signal.

In one possible embodiment, the voltage holding unit includes a second inverter and a third inverter, wherein the second inverter and the third inverter are cross-coupled.

In one possible implementation, the second inverter includes a third NMOS transistor and a third PMOS transistor, and the third inverter includes a fourth NMOS transistor and a fourth PMOS transistor, wherein:

a drain of the third NMOS transistor is electrically connected to a drain of the third PMOS transistor, a gate of the fourth NMOS transistor, a gate of the fourth PMOS transistor, and a source of the first PMOS transistor for generating an inverted signal of the output signal,

a gate of the third NMOS transistor is electrically connected to a gate of the third PMOS transistor, a drain of the fourth NMOS transistor, a drain of the fourth PMOS transistor, and a source of the second PMOS transistor for generating the output signal,

a source of the third NMOS transistor is electrically connected to a source of the fourth NMOS transistor, a gate of the first PMOS transistor, and a gate of the second PMOS transistor, for receiving the second power voltage,

the source electrode of the third PMOS transistor is electrically connected to the source electrode of the fourth PMOS transistor and used for receiving the first power supply voltage.

In one possible embodiment, the voltage of the first supply voltage is higher than the voltage of the second supply voltage, which is higher than the voltage of the third supply voltage.

In a possible implementation manner, source-drain channels of the first NMOS transistor, the second NMOS transistor, the first PMOS transistor, and the second PMOS transistor can bear the first power supply voltage.

In a possible implementation manner, the source-drain channels of the third PMOS transistor and the fourth PMOS transistor can bear a voltage between the first power supply voltage and the second power supply voltage.

According to another aspect of the present disclosure, a data processing apparatus is provided, which includes the electronic apparatus.

According to another aspect of the present disclosure, an electronic device is provided, which includes the data processing apparatus.

In one possible implementation, the electronic device includes a portable computer, an intelligent handheld electronic device.

In the electronic device provided by the embodiment of the disclosure, when the third power voltage generating the input signal is maintained for a period of time and disappears, the potential of the inverted signal of the output signal at the first end can be maintained, and the potential of the output signal at the second end can be maintained, so that when one of the power supplies stops working, the stability of the output signal is maintained, and by reducing one power supply to work, the power consumption can be reduced.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

Fig. 1 shows a schematic view of an electronic device according to an embodiment of the present disclosure.

Fig. 2 is a schematic diagram illustrating an effect of an operation of an electronic device according to an embodiment of the present disclosure.

Fig. 3 shows a schematic diagram of an electronic device according to an embodiment of the present disclosure.

Detailed Description

Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure.

Referring to fig. 1, fig. 1 is a schematic diagram illustrating an electronic device according to an embodiment of the disclosure.

As shown in fig. 1, the apparatus includes a first NMOS (N-Metal-Oxide-Semiconductor) transistor 110, a second NMOS transistor 112, a first PMOS (P-Metal-Oxide-Semiconductor) transistor 110a, a second PMOS transistor 112a, and a voltage holding unit 120, the electronic apparatus is used for converting an input signal a belonging to a first voltage range into an output signal Y belonging to a second voltage range, wherein,

the gate of the first NMOS transistor 110 is configured to receive the input signal a, the drain of the first NMOS transistor 110 is electrically connected to the drain of the first PMOS transistor 110a, the source of the first NMOS transistor 110 is grounded,

the gate of the second NMOS transistor 112 is used for receiving the inverse signal Y of the input signal_bThe drain of the second NMOS transistor 112 is electrically connected to the drain of the second PMOS transistor 112a, the source of the second NMOS transistor 112 is grounded,

a source of the first PMOS transistor 110a is electrically connected to a first end of the voltage holding unit 120, and a voltage signal of the first end of the voltage holding unit 120 is an inverted signal Y of the output signal_b；

The source of the second PMOS transistor 112a is electrically connected to the second end of the voltage holding unit, for outputting the output signal Y,

the first power terminal of the voltage holding unit 120 is used for inputting a first power voltage V_DDHThe gate of the first PMOS transistor 110a, the gate of the second PMOS transistor 112a and the second power terminal of the voltage holding unit 120 are used for inputting a second power voltage V_SSHWherein, when the third power voltage generating the input signal a disappears after being maintained for a period of time, the voltage holding unit 120 is used for maintaining the potential of the output signal Y and the inverted signal Y of the output signal_bThe potential of (2).

In the electronic device provided by the embodiment of the disclosure, when the third power voltage generating the input signal is maintained for a period of time and disappears, the potential of the inverted signal of the output signal at the first end can be maintained, and the potential of the output signal at the second end can be maintained, so that when one of the power supplies stops working, the stability of the output signal is maintained, and by reducing one power supply to work, the power consumption can be reduced.

The electronic device of the embodiment of the present disclosure may be applied to a data processing device, and the data processing device may be applied to an electronic apparatus. The data processing device may process input data, for example, perform data temporary storage, shift, operation, and the like, where the electronic device may include a mobile phone, a sound box, an intelligent wearable device, a digital camera, mp3, mp4, a router, an electronic book, a switch, a broadband cat, a PSP, PS3, an NDS, an XBOX, a usb disk, a digital satellite receiver, and other digital products, and may also include a computer motherboard, a BIOS of a printer, a BIOS of a display card, a mouse, a display, an optical drive, a hard disk, a keyboard, a GPS terminal, a precision electronic instrument (such as a nuclear magnetic resonance instrument), and the like. In one example, the first voltage range may be a voltage range formed by the second power supply voltage and the ground voltage, and the second voltage range may be a range formed by the first power supply voltage and the ground voltage.

In one example, the electronic device may be a Level Shifter (Level Shifter).

In one possible embodiment, the voltage of the first power supply voltage may be higher than the voltage of the second power supply voltage, and the voltage of the first power supply voltage is higher than the logic 1 potential of the input signal a.

Referring to fig. 2, fig. 2 is a schematic diagram illustrating an effect of an operation of an electronic device according to an embodiment of the disclosure.

According to the electronic device of the embodiment of the present disclosure, as shown in FIG. 2, when the third power voltage V is applied_DDLWhen the power failure is maintained for a period of time, although the level of the input signal A is also reduced from the high level to the low level, the output signal Y is still maintained at the high level due to the action of the voltage holding unit, and the normal and stable output of the circuit is maintained.

In one example, assume that the input signal A is at a third supply voltage V_DDLIs logic 1 potential (high level), at this time, the inverse signal A of the input signal A_bAt a logic 0 level (low level), the first NMOS transistor 110 outputs an output signal through the first PMOS transistor 110a which is turned on during a period in which the input signal A maintains a logic 1 levelInverse signal Y of the signal_bPulled low and the second NMOS transistor 112 is turned off during this time, presenting a high impedance state, therefore, the output signal Y is high.

In one example, a third voltage supply V is used to generate the input signal A_DDLAfter the input signal a is at the logic 1 level for a period of time, the level of the input signal a gradually decreases to the reference ground level, the first NMOS transistor 110 assumes a high-impedance state during the period of time, and the inverted signal of the input signal a also fails, so that the source-drain channel of the second NMOS transistor 112 also assumes a high-impedance state, and therefore the output signal Y and the inverted output signal Yb of the voltage holding unit 120 are still maintained at high levels (close to the first power voltage V, respectively) (i.e., close to the first power voltage V)_DDH) And a low potential (close to the second supply voltage V)_SSH). That is, the electronic device allows the third voltage source V for generating the input signal A_DDLThe effective transmission and retention of the logic state can be ensured only by maintaining for a short time, thereby reducing the power consumption of the whole circuit.

In one example, it is assumed that the input signal a is at a logic 0 potential (low level) under the maintenance of the third power supply voltage, and at this time, the inverted signal a of the input signal a_bAt a logic 1 level (high level), the first NMOS transistor 110 is in a high-impedance state during a period of time when the input signal A maintains a logic 0 level, so that the inverse signal Y of the output signal is generated_bAnd is high, and the second NMOS transistor 112 is turned on during this time to pull the output signal Y low, which is low.

In one example, a third voltage supply V is used to generate the input signal A_DDLWhen the input signal a is at the logic 0 level for a period of time and disappears, the first NMOS transistor 110 and the second NMOS transistor 112 will be in the high-impedance state for the period of time, so that the output signal Y and the inverted output signal Y of the voltage holding unit 120 are obtained_bAre still respectively maintained at low potential (close to the second power voltage V)_SSH) And a high potential (close to the first supply voltage V_DDH). That is, the electronic device allows the third voltage source for generating the input signal A to be maintained for a short period of time to ensure effective transfer of the logic stateAnd hold, thereby reducing the power consumption of the overall circuit.

In a possible implementation manner, the source-drain channels of the first NMOS transistor 110, the second NMOS transistor 112, the first PMOS transistor 110a, and the second PMOS transistor 112a can bear the first power voltage V_DDH。

In one example, when selecting the devices of the first NMOS transistor 110, the second NMOS transistor 112, the first PMOS transistor 110a, and the second PMOS transistor 112a, the selection may be performed according to the above criteria, and the electronic device may operate more efficiently and stably by selecting the first NMOS transistor 110, the second NMOS transistor 112, the first PMOS transistor 110a, and the second PMOS transistor 112a capable of withstanding the first power voltage VDDH according to the embodiment of the disclosure.

In a possible embodiment, the first supply voltage V_DDHMay be higher than the second supply voltage V_SSHOf the second supply voltage V_SSHIs higher than the third supply voltage V_DDLThe voltage of (c).

In one example, the voltage holding unit 120 may be biased to the first power voltage V_DDHAnd the second power supply voltage V_SSHIn the meantime.

Referring to fig. 3, fig. 3 is a schematic diagram illustrating an electronic device according to an embodiment of the disclosure.

In a possible implementation manner, as shown in fig. 3, the apparatus may further include a first inverter 111, an input terminal of the first inverter 111 is electrically connected to the gate of the first NMOS transistor 110, an output terminal of the first inverter 111 is electrically connected to the gate of the second NMOS transistor 112, and a power source terminal of the first inverter 111 is used for inputting the third power source voltage V_DDLThe ground terminal of the first inverter 111 is grounded,

the first inverter 111 is configured to perform inverse processing on the input signal a and output an inverse signal a of the input signal_b。

In the present example, an inverted signal A of the input signal A_bMay be generated by the first inverter 111, and the potential of the input signal a may be generated by the third power supply voltage V_DDLAnd (4) maintaining.

Of course, in other embodiments, the embodiment of the present disclosure may further include a signal generating unit for generating a third power voltage V_DDLUnder the action of (1), an input signal A and an inverse signal A thereof are generated_bI.e. the inverse A of the input signal_bCan also be generated directly by the signal generation unit without relying on the first inverter 111, i.e. the input signal a and its inverse signal a_bAre independently generated signals.

Of course, the above is applied to the input signal A and its inverse signal A_bThe description of the generation manner is exemplary, and in other embodiments, a person skilled in the art may also implement the generation manner in other manners, and the embodiments of the present disclosure are not limited thereto.

A possible implementation of the voltage holding unit 120 is exemplarily described below.

In one possible embodiment, the voltage holding unit 120 may be implemented by a hardware circuit.

In one possible embodiment, the voltage holding unit 120 may include a second inverter and a third inverter, wherein the second inverter and the third inverter are cross-coupled.

The embodiment of the present disclosure can realize a potential holding function of the voltage holding unit by cross-coupling the first inverter and the second inverter.

In one possible implementation, as shown in fig. 3, the second inverter may include a third NMOS transistor 121a and a third PMOS transistor 122a, and the third inverter may include a fourth NMOS transistor 121b and a fourth PMOS transistor 122 b. :

a drain of the third NMOS transistor 121a is electrically connected to a drain of the third PMOS transistor 122a, a gate 121b of the fourth NMOS transistor, a gate of the fourth PMOS transistor 122b, and a source of the first PMOS transistor 110a, for generating an inverse of the output signalPhase signal Y_b，

The gate of the third NMOS transistor 121a is electrically connected to the gate of the third PMOS transistor 122a, the drain of the fourth NMOS transistor 121b, the drain of the fourth PMOS transistor 122b, and the source of the second PMOS transistor 112a, for generating the output signal Y,

a source of the third NMOS transistor 121a is electrically connected to a source of the fourth NMOS transistor 121b, a gate of the first PMOS transistor 110a, and a gate of the second PMOS transistor 112a, and is configured to receive the second power voltage V_SSH，

A source of the third PMOS transistor 122a is electrically connected to a source of the fourth PMOS transistor 121b for receiving the first power voltage V_DDH。

In a possible implementation manner, the source-drain channels of the third PMOS transistor 122a and the fourth PMOS transistor 122b can bear the first power voltage V_DDHAnd the second power supply voltage V_SSHThe voltage in between.

With the above electronic device, the embodiment of the disclosure can effectively maintain the logic state of the output signal only by using the bias voltage of the high-voltage first power voltage after the low-voltage third power voltage disappears, so as to maintain the circuit stability, and allow the low-voltage power supply to output the voltage without a normal state, thereby further saving power consumption.

Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.