阅读说明：本技术 一种dc-dc过零点检测电路及控制方法 (DC-DC zero-crossing detection circuit and control method ) 是由 边疆 黄鑫 张适 谢瑞 于 2021-01-12 设计创作，主要内容包括：本发明提供了一种DC-DC过零点检测电路及控制方法,当模式控制信号Mode＝0时,NM1管开启,带着电感电流信息的来自功率管的开关结点信号LX通过有源电阻NM3与参考电压相比较,通过比较器的预放大作用和锁存电路以及缓冲器产生过零检测信号；当模式控制信号Mode＝1时,PM1管开启,通过电流源IDC1充电,带着电感电流信息的来自功率管的开关结点信号LX通过有源电阻NM3与参考电压相比较,通过比较器的预放大作用和锁存电路以及缓冲器产生过零检测信号。本发明适应两种工作模式,频率调制模式和强制脉宽调制模式下的过零电流检测,比较器电路增加预放大级,响应速度更快。(The invention provides a DC-DC zero-crossing detection circuit and a control method, when a Mode control signal Mode is 0, an NM1 tube is started, a switch node signal LX from a power tube with inductive current information is compared with a reference voltage through an active resistor NM3, and a zero-crossing detection signal is generated through the pre-amplification action of a comparator, a latch circuit and a buffer; when the Mode control signal Mode is equal to 1, the PM1 transistor is turned on, charged by the current source IDC1, and the switching node signal LX from the power transistor with the inductor current information is compared with the reference voltage through the active resistor NM3, and the zero crossing detection signal is generated through the pre-amplification of the comparator and the latch circuit and the buffer. The invention is suitable for zero-crossing current detection in two working modes, namely a frequency modulation mode and a forced pulse width modulation mode, and the comparator circuit increases a pre-amplification stage and has higher response speed.)

1. A DC-DC zero-crossing detection circuit comprises current sources IDC1 and IDC2, resistors R1 and R2, an inverter INV1, a P-channel enhanced MOS transistor PM1, N-channel enhanced MOS transistors NM1, NM2 and NM3, a comparator Pre-amplification stage Pre _ amp, a Latch and Buffer module Latch _ Buffer, a power supply port VDD, a MODE control port MODE, a ground port GND, a switch node LX and an output port OZD, and is characterized in that:

the VDD port is connected with an external power supply, the MODE port is connected with an external MODE control signal, and the GND port is connected with a ground potential;

one end of the current source IDC1 is connected with VDD, and the other end of the current source IDC1 is connected with the source electrode of the PM 1; one end of the current source IDC2 is connected with VDD, the other end of the current source IDC2 is connected with the drain of NM3 and the input comparison signal end of the pre-amplification stage of the comparator, and IDC1 and IDC2 are bias circuits and provide comparison voltage for the comparator;

one end of the resistor R1 is connected with VDD, and the other end is connected with the grid of NM 2; one end of the resistor R2 is connected with VDD, and the other end is connected with the grid of NM 3;

the input end of the inverter INV1 is connected with MODE, and the output end is respectively connected with the grid electrodes of PM1 and NM 1;

the gate of the PM1 is connected with the output end of the NM1 gate and the INV1, the source is connected with one end of the IDC1, the drain is connected with the drain of the NM1, the drain of the NM2 and the input end of the Pre _ amp; the grid electrode of the NM1 is connected with the grid electrode of the PM1 and the output end of the INV1, the source electrode of the NM1 is connected with GND, and the drain electrode of the NM1 is connected with the drain electrode of the PM1 and the input end of the Pre _ amp;

the grid electrode of NM2 is connected with one end of resistor R1, the source electrode is connected with GND, the drain electrode is connected with the drain electrode of NM1, the drain electrode of NM2 and the input end of Pre _ amp; the gate of NM3 is connected with one end of resistor R2, the source is connected with LX port, and the drain is connected with one end of current source IDC2 and the input end of Pre _ amp; the Pre _ amp comparison input terminal is connected with one terminal of the current source IDC2, the drains of NM2 and NM3, and the drains of PM1 and NM1, the output terminal is connected with the Latch _ Buffer circuit Latch _ Buffer, the Latch _ Buffer input terminal is connected with the Pre-amplification output terminal, and the output terminal is the OZD zero-crossing signal port.

2. A control method using the DC-DC zero-crossing detection circuit of claim 1, characterized by comprising the steps of:

when the Mode control signal Mode is equal to 0, the NM1 transistor is turned on, the reference voltage at the reference terminal of the comparator Pre-amplifying module Pre _ amp is 0, the switching node signal LX from the power transistor with the inductor current information is compared with the reference voltage through the active resistor NM3, and the zero-crossing detection signal is generated through the Pre-amplification function of the comparator, the latch circuit and the buffer;

when the Mode control signal Mode is equal to 1, the PM1 transistor is turned on, a reference voltage is established on the active resistor NM2 by charging through the current source IDC1, the switching node signal LX from the power transistor with the inductor current information is compared with the reference voltage through the active resistor NM3, and the zero crossing detection signal is generated through the pre-amplification of the comparator and the latch circuit and the buffer.

Technical Field

The invention relates to the technical field of circuits, in particular to a zero-crossing detection circuit.

Background

Along with diversification of power supply modes of electronic equipment, in order to cope with different working conditions, a required DC-DC power supply control chip is more and more complex, the most typical situation is that the working frequency changes along with adjustment of power supply voltage, at the moment, the chip works in a pulse frequency modulation mode, along with adjustment of a load, the chip needs to be transited to the pulse width modulation mode, a module for detecting inductive current needs to be switched along with the change of the working frequency, and current detection circuits of various control chips in the existing market generally have the problems that the working state is single, and different working modes cannot be well coped with.

Disclosure of Invention

In order to overcome the defects of the prior art, the invention provides a DC-DC zero-crossing detection circuit and a control method, and provides the zero-crossing detection circuit which can be applied to two DC-DC control modes (a pulse frequency modulation mode and a forced pulse width modulation mode) after the current common zero-crossing detection circuit design idea and structure are adopted.

The technical scheme adopted by the invention for solving the technical problems is as follows:

a DC-DC zero-crossing detection circuit is shown in FIG. 1 and comprises current sources IDC1 and IDC2, resistors R1 and R2, an inverter INV1, a P-channel enhanced MOS tube PM1, N-channel enhanced MOS tubes NM1, NM2 and NM3, a comparator Pre-amplification stage Pre-amp, a Latch and Buffer module Latch-Buffer, a power supply port VDD, a MODE control port MODE, a ground port GND, a switch node LX and an output port OZD.

The VDD port is connected with an external power supply, the MODE port is connected with an external MODE control signal, and the GND port is connected with the ground potential.

One end of the current source IDC1 is connected with VDD, and the other end of the current source IDC1 is connected with the source electrode of the PM 1; one end of the current source IDC2 is connected with VDD, the other end of the current source IDC2 is connected with the drain of NM3 and the input comparison signal end of the comparator pre-amplification stage, and IDC1 and IDC2 mainly serve as bias circuits for providing comparison voltage for the comparator.

One end of the resistor R1 is connected with VDD, and the other end is connected with the grid of NM 2; one end of the resistor R2 is connected with VDD, the other end is connected with the gate of NM3, and the main function of R1 and R2 is to provide the power voltage to the active resistor after the power voltage is reduced to a proper value.

The input end of the inverter INV1 is connected with MODE, and the output end is respectively connected with the grids of PM1 and NM1, and the inverter INV1 is mainly used for shaping signals.

The gate of the PM1 is connected with the output end of the NM1 gate and the INV1, the source is connected with one end of the IDC1, the drain is connected with the drain of the NM1, the drain of the NM2 and the input end of the Pre _ amp; the gate of the NM1 is connected with the output end of the PM1 gate and the INV1, the source is connected with GND, and the drain is connected with the drain of the PM1 and the input end of the Pre _ amp. The main role of PM1 and NM1 is to gate the reference voltage of the comparator.

The grid electrode of NM2 is connected with one end of resistor R1, the source electrode is connected with GND, the drain electrode is connected with the drain electrode of NM1, the drain electrode of NM2 and the input end of Pre _ amp; NM3 has a gate connected to one end of resistor R2, a source connected to the LX port, and a drain connected to one end of current source IDC2 and to the Pre _ amp input. The main role of NM2 and NM3 is to reduce mismatch as active resistance. The Pre _ amp comparison input terminal is connected to one terminal of the current source IDC2, the drains of NM2 and NM3, and the drains of PM1 and NM1, and the output terminal is connected to the Latch and Buffer circuit Latch _ Buffer, which mainly functions as a Pre-amplification stage of the comparator. The Latch _ Buffer input end of the Latch and Buffer circuit is connected with the pre-amplification output end, and the output end is an OZD zero-crossing signal port.

The invention also provides a control method of the DC-DC zero-crossing detection circuit, which comprises the following specific steps:

when the Mode control signal Mode is equal to 0, the NM1 transistor is turned on, the reference voltage at the reference terminal of the comparator Pre-amplifying module Pre _ amp is 0, the switching node signal LX from the power transistor with the inductor current information is compared with the reference voltage through the active resistor NM3, and the zero-crossing detection signal is generated through the Pre-amplification function of the comparator, the latch circuit and the buffer; when the Mode control signal Mode is equal to 1, the PM1 transistor is turned on, a reference voltage is established on the active resistor NM2 by charging through the current source IDC1, the switching node signal LX from the power transistor with the inductor current information is compared with the reference voltage through the active resistor NM3, and the zero crossing detection signal is generated through the pre-amplification of the comparator and the latch circuit and the buffer.

The invention has the beneficial effects that:

1. the zero-crossing current detection method can adapt to zero-crossing current detection in two working modes, namely a frequency modulation mode and a forced pulse width modulation mode.

2. The comparator circuit increases the pre-amplification stage, and the response speed is higher.

Drawings

Fig. 1 is a schematic diagram of a zero-crossing point detection circuit applicable to multiple modes according to the present invention.

Detailed Description

The invention is further illustrated with reference to the following figures and examples.

As shown in fig. 1, a DC-DC zero-crossing detection circuit includes current sources IDC1 and IDC2, resistors R1 and R2, an inverter INV1, a P-channel enhancement type MOS transistor PM1, N-channel enhancement type MOS transistors NM1, NM2, NM3, a comparator Pre-amplification stage Pre _ amp, a Latch and Buffer module Latch _ Buffer, a power supply port VDD, a MODE control port MODE, a ground port GND, a switch node LX, and an output port OZD. The VDD port is connected with an external power supply, the MODE port is connected with an external MODE control signal, and the GND port is connected with the ground potential.

One end of the current source IDC1 is connected with VDD, and the other end of the current source IDC1 is connected with a PM1 source electrode; one end of the current source IDC2 is connected with VDD, the other end of the current source IDC2 is connected with the drain of NM3 and the input comparison signal end of the pre-amplification stage of the comparator, and IDC1 and IDC2 mainly serve as bias circuits and provide comparison voltage for the comparator.

One end of the resistor R1 is connected with VDD, and the other end is connected with the grid of NM 2; one end of the resistor R2 is connected with VDD, the other end is connected with the gate of NM3, and the main function of R1 and R2 is to provide the power voltage to the active resistor after the power voltage is reduced to a proper value.

The input end of the inverter INV1 is connected with MODE, and the output end is connected with the grids of PM1 and NM1, and the inverter INV1 mainly acts as a shaping signal.

The gate of the PM1 is connected with the output end of the NM1 gate and the INV1, the source is connected with one end of the IDC1, the drain is connected with the drain of the NM1, the drain of the NM2 and the input end of the Pre _ amp; the gate of the NM1 is connected with the output end of the PM1 gate and the INV1, the source is connected with GND, and the drain is connected with the drain of the PM1 and the input end of the Pre _ amp. The main role of PM1 and NM1 is to gate the reference voltage of the comparator.

The grid electrode of NM2 is connected with one end of resistor R1, the source electrode is connected with GND, the drain electrode is connected with the drain electrode of NM1, the drain electrode of NM2 and the input end of Pre _ amp; NM3 has a gate connected to one end of resistor R2, a source connected to the LX port, and a drain connected to one end of current source IDC2 and to the Pre _ amp input. The main role of NM2 and NM3 is to reduce mismatch as active resistance. The Pre _ amp comparison input terminal is connected to one terminal of the current source IDC2, the drains of NM2 and NM3, and the drains of PM1 and NM1, and the output terminal is connected to the Latch and Buffer circuit Latch _ Buffer, which mainly functions as a Pre-amplification stage of the comparator. The Latch _ Buffer input end of the Latch and Buffer circuit is connected with the pre-amplification output end, and the output end is an OZD zero-crossing signal port.

Referring to fig. 1, the control method of the DC-DC zero-crossing detection circuit includes: when the Mode control signal Mode is equal to 0, the NM1 transistor is turned on, and the reference voltage at the reference terminal of the comparator Pre-amplifying module Pre _ amp is 0, the switching node signal LX from the power transistor with the inductor current information is compared with the reference voltage through the active resistor NM3, and the zero-crossing detection signal is generated through the Pre-amplification function of the comparator, the latch circuit and the buffer; when the Mode control signal Mode is equal to 1, the PM1 transistor is turned on, and then a reference voltage is established on the active resistor NM2 by charging through the current source IDC1, and the switching node signal LX from the power transistor with the inductor current information is compared with the reference voltage through the active resistor NM3, and a zero crossing detection signal is generated through the pre-amplification function of the comparator, the latch circuit and the buffer.

In summary, the present invention provides a zero crossing point detection circuit applicable to multiple modes, which can be effectively applied to switching between different operating modes of a DC-DC chip. The structure is flexible and has good adaptability to load adjustment.

The above explanation is only a preferred embodiment of the present invention and a basic explanation of the technical principle therein. It should be understood by those skilled in the art that the technical scope of the present invention is not limited to the technical explanation of the above-mentioned technology, and also includes other technical solutions formed by any combination of the above-mentioned technical solutions or equivalent solutions within the technical scope of the present invention, for example, the technical solutions formed by replacing and modifying the technical solutions with (but not limited to) the similar functions disclosed in the present invention.