阅读说明：本技术 一种同步信号相位调整方法及装置 (Synchronization signal phase adjustment method and device ) 是由 于洋 于 2020-12-16 设计创作，主要内容包括：本发明提供一种同步信号相位调整方法及装置,所述方法包括：对获取的同步信号进行延时处理,得到延时同步信号；利用预设时钟信号对所述延时同步信号进行相位检测；本发明通过对同步信号进行延时调整,再对延时调整后的同步信号进行相位检测,通过检测系统时钟与同步信号上升沿的相位关系,并根据相位关系动态控制延时调整,进而对输入同步信号进行延时调整,确保同步信号与系统时钟间具有良好的建立保持时间,使得同步输出信号稳定,本发明避免了现有技术中时钟信号与同步信号“撞沿”的技术问题,实现了快速且精准的对同步信号进行调整,且实现了维持系统的工作稳定的技术效果。(The invention provides a method and a device for adjusting the phase of a synchronous signal, wherein the method comprises the following steps: carrying out time delay processing on the obtained synchronous signal to obtain a time delay synchronous signal; carrying out phase detection on the delay synchronization signal by using a preset clock signal; according to the invention, the synchronization signal is subjected to delay adjustment, then the phase detection is carried out on the synchronization signal after the delay adjustment, the phase relation between the system clock and the rising edge of the synchronization signal is detected, the delay adjustment is dynamically controlled according to the phase relation, and further the delay adjustment is carried out on the input synchronization signal, so that the good establishment holding time between the synchronization signal and the system clock is ensured, and the synchronization output signal is stable.)

1. A method for adjusting a phase of a synchronization signal, the method comprising:

carrying out time delay processing on the obtained synchronous signal to obtain a time delay synchronous signal;

and carrying out phase detection on the delayed synchronous signal by using a preset clock signal, if the rising edge of the delayed synchronous signal is in the first quarter cycle interval and the last quarter cycle interval in one cycle of the preset clock signal, carrying out delay processing on the delayed synchronous signal again until the rising edge of the delayed synchronous signal is in the other two quarter cycle intervals of the preset clock signal, and outputting the final delayed synchronous signal.

2. The method of claim 1, further comprising:

and determining the number of the delayers and the phase detectors in the synchronous signal delay link according to the frequency of the preset clock signal.

3. The method of claim 1, wherein delaying the delayed synchronization signal comprises:

performing phase adjustment on an input synchronous signal by adopting a preset phase adjustment value; alternatively, the first and second electrodes may be,

receiving a phase adjustment correction value to carry out phase adjustment on the input delayed synchronous signal after at least one time delay; and the phase adjustment correction value is obtained by carrying out phase detection on the delay synchronous signal.

4. The method of claim 3, wherein the predetermined phase adjustment value is set to a median value of the total delay of the synchronization signal delay chain.

5. The method of claim 2, wherein the phase detection delay amount in the synchronization signal delay chain is set to one quarter of a predetermined clock period.

6. An apparatus for adjusting a phase of a synchronization signal, the apparatus comprising:

the synchronous signal processing module is used for carrying out time delay processing on the obtained synchronous signal to obtain a time delay synchronous signal;

and the synchronous signal detection module is used for carrying out phase detection on the delayed synchronous signal by utilizing a preset clock signal, and if the rising edge of the delayed synchronous signal is in the first quarter cycle interval and the last quarter cycle interval in one cycle of the preset clock signal, carrying out time delay processing on the delayed synchronous signal again until the rising edge of the delayed synchronous signal is in the other two quarter cycle intervals of the preset clock signal, and outputting the final delayed synchronous signal.

7. The apparatus of claim 6, further comprising:

and the delay link module is used for determining the number of delayers and phase detections in the synchronous signal delay link according to the frequency of a preset clock signal.

8. The apparatus of claim 6, wherein the delaying the delayed synchronization signal comprises:

performing phase adjustment on an input synchronous signal by adopting a preset phase adjustment value; alternatively, the first and second electrodes may be,

receiving a phase adjustment correction value to carry out phase adjustment on the input delayed synchronous signal after at least one time delay; and the phase adjustment correction value is obtained by carrying out phase detection on the delay synchronous signal.

9. The apparatus of claim 7, wherein the delay chain comprises a plurality of serially connected delays.

10. The apparatus of claim 7, wherein the delay chain comprises a plurality of phase detectors connected in series.

Technical Field

The present invention relates to the field of synchronization signal adjustment technologies, and in particular, to a synchronization signal phase adjustment method and apparatus.

Background

The phase relation between the synchronous signal and the clock signal is one of important factors for determining whether the radar digital receiver system is stable; the radar digital receiver system comprises a plurality of digital receiving components, and the synchronization among the components needs to ensure consistency so as to ensure the system index. Each component uses the clock signal provided by the frequency synthesizer system to sample the synchronization signal, thereby determining the effective moment of the synchronization signal. When the rising edge of the clock collides with the rising edge of the synchronous signal, which causes that the establishment time and the holding time of the synchronous signal cannot be satisfied, the system working period of the whole receiving assembly will have a shaking of one clock period, which causes the jumping of the synchronous signal, and causes the reduction of the system synthesis efficiency.

During the operation of the radar digital receiver system, due to the influence of factors such as temperature, voltage, interference and the like, the phase of a clock or a synchronous signal can drift slowly, so that the phenomenon that the clock and the synchronous signal collide with each other during the operation of a normal system can occur, and the system is unstable.

Disclosure of Invention

In order to solve at least one of the above problems, a first aspect of the present invention provides a synchronization signal phase adjustment method, including:

s101: carrying out time delay processing on the obtained synchronous signal to obtain a time delay synchronous signal;

s102: and carrying out phase detection on the delayed synchronous signal by using a preset clock signal, if the rising edge of the delayed synchronous signal is in the first quarter cycle interval and the last quarter cycle interval in one cycle of the preset clock signal, carrying out delay processing on the delayed synchronous signal again until the rising edge of the delayed synchronous signal is in the other two quarter cycle intervals of the preset clock signal, and outputting the final delayed synchronous signal.

Preferably, the method further comprises:

and determining the number of the delayers and the phase detectors in the synchronous signal delay link according to the frequency of the preset clock signal.

Preferably, the delaying the delayed synchronization signal includes:

performing phase adjustment on an input synchronous signal by adopting a preset phase adjustment value; alternatively, the first and second electrodes may be,

receiving a phase adjustment correction value to carry out phase adjustment on the input delayed synchronous signal after at least one time delay; and the phase adjustment correction value is obtained by carrying out phase detection on the delay synchronous signal.

Preferably, the preset phase adjustment value is set as a middle value of the total delay of the synchronization signal delay link.

Preferably, the phase detection delay amount in the synchronization signal delay link is set to be one fourth of the preset clock period.

A second aspect of the present invention provides a synchronization signal phase adjustment apparatus, including:

the synchronous signal processing module is used for carrying out time delay processing on the obtained synchronous signal to obtain a time delay synchronous signal;

and the synchronous signal detection module is used for carrying out phase detection on the delayed synchronous signal by utilizing a preset clock signal, and if the rising edge of the delayed synchronous signal is in the first quarter cycle interval and the last quarter cycle interval in one cycle of the preset clock signal, carrying out time delay processing on the delayed synchronous signal again until the rising edge of the delayed synchronous signal is in the other two quarter cycle intervals of the preset clock signal, and outputting the final delayed synchronous signal.

Preferably, the apparatus further comprises:

and the delay link module is used for determining the number of delayers and phase detections in the synchronous signal delay link according to the frequency of a preset clock signal.

Preferably, the delaying the delayed synchronization signal includes:

performing phase adjustment on an input synchronous signal by adopting a preset phase adjustment value; alternatively, the first and second electrodes may be,

receiving a phase adjustment correction value to carry out phase adjustment on the input delayed synchronous signal after at least one time delay; and the phase adjustment correction value is obtained by carrying out phase detection on the delay synchronous signal.

Preferably, the delay chain comprises a plurality of series-connected delayers.

Preferably, the delay chain comprises a plurality of phase detectors connected in series.

The invention has the advantages of

The invention provides a method and a device for adjusting the phase of a synchronous signal, wherein the method comprises the following steps: carrying out time delay processing on the obtained synchronous signal to obtain a time delay synchronous signal; performing phase detection on the delayed synchronous signal by using a preset clock signal, and if the rising edge of the delayed synchronous signal is in the first quarter cycle interval and the last quarter cycle interval of one cycle of the preset clock signal, performing delay processing on the delayed synchronous signal again until the rising edge of the delayed synchronous signal is in the other two quarter cycle intervals of the preset clock signal, and outputting a final delayed synchronous signal; according to the invention, the synchronization signal is subjected to delay adjustment, then the phase detection is carried out on the synchronization signal after the delay adjustment, the phase relation between the system clock and the rising edge of the synchronization signal is detected, the delay adjustment is dynamically controlled according to the phase relation, and further the delay adjustment is carried out on the input synchronization signal, so that the good establishment holding time between the synchronization signal and the system clock is ensured, and the synchronization output signal is stable.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a schematic flow chart illustrating a synchronization signal adjustment method according to an embodiment of the present invention;

fig. 2 is a block diagram of a synchronization signal adjustment according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a synchronization signal delay link according to an embodiment of the present invention;

fig. 4 is a schematic diagram illustrating acquisition of a delayed synchronization signal replica according to an embodiment of the present invention;

fig. 5 is a schematic diagram of a delay locked signal before and after adjustment according to an embodiment of the present invention;

fig. 6 is a schematic diagram illustrating an adjustable range of delay of a synchronization signal according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.

With the continuous development of scientific technology, the radar digital transceiving technology has also made a leap progress. It is well known that the phase relationship between the clock signal and the synchronization signal is one of the key factors for the stability of the radar digital transceiving technology. In the prior art, each component in the radar digital transceiver system samples an input synchronization signal through a clock signal provided by a frequency synthesizer, so as to determine the synchronization time of the two components. Then, when the rising edge of the clock signal and the rising edge of the synchronization signal collide with each other in time, so that the establishment of the holding time cannot be met, the working period of the radar digital transceiving system has a clock signal period which is involved in a kurtosis, so that phase jump is caused, and the system synthesis efficiency is low.

Due to the influence of factors such as temperature, voltage, interference and the like, the phases of the clock signal and the synchronous signal can drift slowly, so that the phenomenon of 'edge collision' of the clock signal and the synchronous signal can occur during the working period of the system, and the system is unstable; therefore, the technical disadvantage that the system has 'edge collision' during working is solved, and the problem of maintaining the stable working of the radar digital transceiving system is urgently solved.

In view of the above, a first aspect of the present invention provides a method for adjusting a phase of a synchronization signal, referring to fig. 1, the method includes:

s101: carrying out time delay processing on the obtained synchronous signal to obtain a time delay synchronous signal;

specifically, the acquired synchronization signal refers to a synchronization signal initially received by the system, and performing the delay processing on the acquired synchronization signal refers to changing a phase of the synchronization signal.

S102: and carrying out phase detection on the delayed synchronous signal by using a preset clock signal, if the rising edge of the delayed synchronous signal is in the first quarter cycle interval and the last quarter cycle interval in one cycle of the preset clock signal, carrying out delay processing on the delayed synchronous signal again until the rising edge of the delayed synchronous signal is in the other two quarter cycle intervals of the preset clock signal, and outputting the final delayed synchronous signal.

Referring to fig. 2, in a specific example, the synchronization signal is sent to the relative phase detection module after passing through the delay adjustment module, and the detection module can detect the phase relationship between the system clock and the rising edge of the synchronization signal, and dynamically control the delay adjustment module according to the phase relationship to perform delay adjustment on the input synchronization signal, so that the rising edge of the input synchronization signal after delay adjustment falls within the period from 2/4 to 3/4 of the preset clock signal.

For example, as shown in fig. 5, there is a good clock sampling relationship when the synchronization signal is in the region b or the region c; when the synchronous signal is monitored to be in the area a, delaying and lagging the synchronous signal to enable the synchronous signal to be in the area b or c; when the synchronous signal is monitored to be in the area d, the synchronous signal is advanced to be in the area b or the area c; the adjustment is guaranteed not to cause cycle jumps of the synchronization signal.

The method provided by the invention carries out delay adjustment on the synchronous signal, then carries out phase detection on the synchronous signal after delay adjustment, and carries out delay adjustment on the input synchronous signal by detecting the phase relationship between the system clock and the rising edge of the synchronous signal and dynamically controlling the delay adjustment according to the phase relationship, thereby ensuring that the synchronous signal and the system clock have good establishment holding time, so that the synchronous output signal is stable.

In a specific embodiment, the synchronization signal phase adjustment method further includes: and determining the number of the delayers and the phase detectors in the synchronous signal delay link according to the frequency of the preset clock signal.

For example, for example: after the synchronous signal A passes through n delay modules in the delayer, a delay synchronous signal a is obtained; the delay amount of the delayed synchronization signal a corresponding to the synchronization signal a is x.

At this time, when the frequency of the clock signal is y, the delay amount x is 2y ± Ins. And, the number of phase detection modules in the phase detector is such that the 5 delayed synchronization signal copies differ by 1/4 clock signal periods each.

More specifically, when the frequency of the clock signal is 80MHZ, the number of delay blocks is 10, and the number of phase detection blocks is 4.

In an embodiment, referring to fig. 2, the delaying the delayed synchronization signal includes:

performing phase adjustment on an input synchronous signal by adopting a preset phase adjustment value; alternatively, the first and second electrodes may be,

receiving a phase adjustment correction value to carry out phase adjustment on the input delayed synchronous signal after at least one time delay; and the phase adjustment correction value is obtained by carrying out phase detection on the delay synchronous signal.

Specifically, the input synchronization signal may be a synchronization signal received by a delay device, or may be a phase-modulated delayed synchronization signal; the phase detector detects the received delayed synchronous signals, and feeds back phase adjustment correction values to the delayer according to detection results, and the delayer adjusts the input synchronous signals according to the phase adjustment correction values.

In a specific embodiment, the preset phase adjustment value is set to be an intermediate value of the total delay of the synchronization signal delay link.

For example, the total delay of the synchronization signal delay chain is 24.18ns, and the preset phase adjustment value is set to 12.09 ns.

In a specific embodiment, the phase detection delay amount in the synchronization signal delay link is set to be one fourth of the preset clock period.

For example, the predetermined clock frequency is 80MHz, and the phase detection delay amount in the synchronization signal delay chain is set to 3.125ns, which is 1/4 of the clock period of 80 MHz.

To more clearly understand the technical solution of the present invention, the following description is made with reference to specific embodiments, and different delay values can be set by the delay adjusting and phase detecting module for different system clock frequencies, which is described by taking clock frequency 80MHz as an example.

As shown in fig. 3, a DELAY line of a synchronization signal link is built through a plurality of IO DELAY modules to obtain a plurality of synchronization signal copies with a determined DELAY relationship, and DELAY amounts of the four modules XD1, XD2, XD3 and XD4 are respectively set to about 3.125ns, namely 1/4 of an 80MHz clock period, so that differences between synchronization signal copies Trig 1-Trig 5 are 1/4 of the 80MHz clock period, namely 90-degree phases.

The phase relation between the Trig1 signal (namely the synchronous output signal) and the 80MHz clock signal can be judged through sampling values of 80MHz pair synchronous signal copies Trig 1-Trig 5.

It can be determined which of the four regions a, b, c, d of 80MHz one cycle the rising edge of the Trig1 signal (i.e., the sync out signal) falls in, respectively corresponding to 0, 1, 2, 3 of the loopback word.

As shown in FIG. 4, the sampling value of the 80MHz clock pair Trig 1-Trig 5 is 11110, which represents that the rising edge of the Trig1 falls in the a-interval.

Through the delay adjustment of D1-D10, the delay of the synchronization signals of the Trig 1-Trig 5 can be adjusted, and the phase relation of the synchronization signals relative to 80MHz is changed, so that the purpose of adjustment is achieved.

It can be understood that 10 adjustment modules are provided for D1-D10, each adjustment module can adjust 31 beats × 78ps, and 310 beats can be adjusted by 24.18ns (about 2 80MHz periods), since D1-D10 can only increase the delay. When power-on initialization (or closing adjustment) is carried out, D1-D10 are set to be a total delay intermediate value, namely 155 beats, then the monitoring circuit carries out synchronous signal monitoring again, and if adjustment is started, the delay values of D1-D10 can be increased or decreased according to the monitoring result.

As shown in fig. 5, when the auto-tuning is turned on, there is a good clock sampling relationship when the sync signal is in the region b or the region c; when the synchronous signal is monitored to be in the area a, delaying and lagging the synchronous signal to enable the synchronous signal to be in the area b or c; when the synchronous signal is monitored to be in the area d, the synchronous signal is advanced to be in the area b or the area c; the adjustment is guaranteed not to cause cycle jumps of the synchronization signal.

It can be understood that when the automatic adjustment is turned on, the adjustment value is continuously corrected according to the monitoring result, so that the synchronization signal is located in the b or c region. If the clock or the synchronous signal continuously and slowly drifts towards one direction, the adjusting circuit needs to continuously adjust towards the same direction (continuously increasing or continuously decreasing the time delay), an adjusting limit exists, when the adjusting limit is reached, the adjusting circuit cannot continuously adjust, at the moment, if the signal continuously and slowly drifts, the adjusting circuit can drift out of the area b or the area c, and the automatic adjusting circuit cannot adjust the signal back.

Since 10 adjustment modules are provided from D1 to D10, the total 310 beats can be adjusted by 24.18ns (about 2 cycles of 80 MHz), and the initial time is set to the middle value, the adjustment capability of the automatic adjustment circuit in both directions is 12.09ns (about 1 cycle of 80 MHz), and the specific adjustment range corresponding to different phase positions of the input synchronization signal in 80MHz is shown in fig. 6.

A second aspect of the present invention provides a synchronization signal phase adjustment apparatus, including:

the synchronous signal processing module is used for carrying out time delay processing on the obtained synchronous signal to obtain a time delay synchronous signal;

and the synchronous signal detection module is used for carrying out phase detection on the delayed synchronous signal by utilizing a preset clock signal, and if the rising edge of the delayed synchronous signal is in the first quarter cycle interval and the last quarter cycle interval in one cycle of the preset clock signal, carrying out time delay processing on the delayed synchronous signal again until the rising edge of the delayed synchronous signal is in the other two quarter cycle intervals of the preset clock signal, and outputting the final delayed synchronous signal.

The device provided by the invention carries out delay adjustment on the synchronous signal, then carries out phase detection on the synchronous signal after delay adjustment, and carries out delay adjustment on the input synchronous signal by detecting the phase relation between the system clock and the rising edge of the synchronous signal and dynamically controlling the delay adjustment according to the phase relation, thereby ensuring that the synchronous signal and the system clock have good establishment holding time, so that the synchronous output signal is stable.

Further, the apparatus further comprises:

and the delay link module is used for determining the number of delayers and phase detections in the synchronous signal delay link according to the frequency of a preset clock signal.

For example, for example: after the synchronous signal A passes through n delay modules in the delayer, a delay synchronous signal a is obtained; the delay amount of the delayed synchronization signal a corresponding to the synchronization signal a is x.

At this time, when the frequency of the clock signal is y, the delay amount x is 2y ± Ins. And, the number of phase detection modules in the phase detector is such that the 5 delayed synchronization signal copies differ by 1/4 clock signal periods each.

More specifically, referring to fig. 3, when the frequency of the clock signal is 80MHZ, the number of delay modules is 10, and the number of phase detection modules is 4.

Further, the delay chain comprises a plurality of series-connected delayers.

Further, the delay chain comprises a plurality of phase detectors connected in series.

Specifically, the delayer is used for: performing phase adjustment on an input synchronous signal by adopting a preset phase adjustment value or receiving a phase adjustment correction value fed back by a phase detector to perform phase adjustment on the input synchronous signal; the phase detector is for: and carrying out phase detection on the delay synchronization signal by using a preset clock signal.

In a specific embodiment, the delaying the delayed synchronization signal includes: performing phase adjustment on an input synchronous signal by adopting a preset phase adjustment value; or, receiving a phase adjustment correction value to perform phase adjustment on the input delayed synchronous signal after at least one time delay; and the phase adjustment correction value is obtained by carrying out phase detection on the delay synchronous signal.

Specifically, the input synchronization signal may be a synchronization signal received by a delay device, or may be a phase-modulated delayed synchronization signal; the phase detector detects the received delayed synchronous signals, and feeds back phase adjustment correction values to the delayer according to detection results, and the delayer adjusts the input synchronous signals according to the phase adjustment correction values.

In the description of the present specification, reference to the description of the terms "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present specification. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example.

Furthermore, the various embodiments or examples and features of the various embodiments or examples described in this specification can be combined and combined by those skilled in the art without contradiction. The above description is only an embodiment of the present disclosure, and is not intended to limit the present disclosure. Various modifications and changes may occur to those skilled in the art to which the embodiments of the present disclosure pertain. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiments of the present specification should be included in the scope of the claims of the embodiments of the present specification.