阅读说明：本技术 驱动电路、具有驱动电路的系统和校准程序 (Driver circuit, system having the same, and calibration program ) 是由 R·伊林 C·德耶拉希-切克 C·格兰策 于 2020-10-26 设计创作，主要内容包括：在此公开了驱动电路、具有驱动电路的系统和校准程序。在此提供了一种驱动器电路(10)。驱动器电路(10)具有功率晶体管(14)和栅极驱动器电路装置(11)。驱动器电路(10)被集成在封装中。另外,驱动器电路(10)具有用于外部晶体管(13)的接头(12)。外部晶体管(13)和功率晶体管(14)由栅极驱动器电路装置(11)彼此对应地驱控。(A driver circuit, a system having the driver circuit, and a calibration procedure are disclosed herein. A driver circuit (10) is provided. The driver circuit (10) has a power transistor (14) and a gate driver circuit arrangement (11). The driver circuit (10) is integrated in a package. In addition, the driver circuit (10) has a connection (12) for an external transistor (13). The external transistor (13) and the power transistor (14) are controlled by the gate driver circuit arrangement (11) in correspondence with each other.)

1. A driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000) comprises:

a gate driver circuit arrangement (11),

a power transistor (14; 25) coupled with the gate driver circuit arrangement (11), and

at least one connection terminal (12; GATE1, GATE2, GATE3) coupled to the GATE driver circuit arrangement (11),

wherein the GATE driver circuit arrangement (11) is arranged to drive the power transistor (14; 25) and at least one external transistor (13; 25) in correspondence with each other, the at least one external transistor being coupled to the driver circuit (10; 20; 30; 40; 50; 60; 60; 70; 80; 90; 231; 531; 1000) at the at least one connection terminal (12; GATE1, GATE2, GATE3),

wherein the driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000) is integrated in one package.

2. The driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000) as defined in claim 1, further comprising a current monitoring circuit arranged to monitor a current through the power transistor (14; 25).

3. The driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000) as defined in claim 2, wherein the current monitoring circuit comprises a detection transistor (31; 44, 45) scaled with respect to the power transistor (14; 25) and is configured to monitor a current through the power transistor (14; 25) based on the current through the detection transistor (31; 44, 45).

4. The driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000) as claimed in claim 2 or 3, further comprising a calibration memory (52) in which information about the performance of the at least one external transistor (13; 25) compared to the power transistor (14; 25) is stored, wherein the current monitoring circuit is arranged to monitor the current flow through the at least one external transistor (13; 25) based on the information and the current through the power transistor (14; 25).

5. The driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000) as claimed in any of claims 2 to 4, wherein the driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000) is arranged to switch off the power transistor (14; 25) and the at least one external transistor (13; 25) when a current through the power transistor (14; 25) indicates an overcurrent event.

6. Driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000) as claimed in any of claims 1 to 5, wherein the at least one connection terminal (12; GATE1, GATE2, GATE3) can optionally be deactivated.

7. The driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000) as claimed in claim 6, wherein the at least one connection terminal (12; GATE1, GATE2, GATE3) comprises a plurality of connection terminals, wherein each connection terminal of the plurality of connection terminals can be selectively deactivated.

8. Driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000) as claimed in claim 6 or 7, further comprising an availability checker arranged to detect whether an external transistor (13; 25) is available at the at least one connection terminal (12; GATE1, GATE2, GATE3) and to selectively deactivate the at least one connection terminal (12; GATE1, GATE2, GATE3) in dependence on the detection.

9. Driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000; 1000) as claimed in any of claims 1 to 8, wherein the gate driver circuit arrangement (11) has a single gate driver (42; 61) for driving the power transistor (14; 25) and the at least external transistor (13; 25).

10. Driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000) as claimed in any of claims 1 to 8, wherein the gate driver circuit arrangement (11) has a first gate driver (61) for driving the power transistor (14; 25) and at least one second gate driver (71, 72, 73) for driving the at least one external transistor (13; 25).

11. The driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000; 1000) as claimed in claim 10 and as claimed in any one of claims 6 to 8, wherein said optionally deactivating comprises optionally deactivating said at least one second GATE driver (71, 72, 73) associated with said at least one connection terminal (12; GATE1, GATE2, GATE 3).

12. The driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000; 1000) of any one of claims 1 to 11, wherein the driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000; 1000) is monolithically integrated on a chip, or wherein the driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000) is integrated on two or more chips arranged in the package.

13. A system, comprising:

at least one external transistor (13; 25), and

a driver circuit, comprising:

a gate driver circuit arrangement (11),

a power transistor (14; 25) coupled with the gate driver circuit arrangement (11), and

at least one connection terminal (12; GATE1, GATE2, GATE3) coupled to the GATE driver circuit arrangement (11),

wherein the driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000) is integrated in one package,

wherein the at least one external transistor (13; 25) is coupled to the at least one connection (12; GATE1, GATE2, GATE3) and

wherein the gate driver circuit arrangement (11) is arranged to drive the power transistor (14; 25) and the at least one external transistor (13; 25) in correspondence with each other.

14. The system according to claim 13, wherein the driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000) is designed according to any one of claims 1 to 13.

15. The system according to claim 13 or 14, wherein the at least one external transistor (13; 25) and the power transistor (14; 25) have similar parameters.

16. The system of claim 15, wherein the parameters include one or more of the following parameters:

a resistance of the at least one external transistor (13; 25) in the on-state,

a start-up voltage of the at least one external transistor (13; 25),

a breakdown voltage of the at least one external transistor (13; 25),

the steepness of the characteristic curve of the at least one external transistor (13; 25),

type of said at least one external transistor (13; 25), or

-an over-current stability of the at least one external transistor (13; 25).

17. The system according to any of claims 13-16, wherein the at least one external transistor (13; 25) comprises a plurality of external transistors (13; 25), and wherein the at least one connection terminal (12; GATE1, GATE2, GATE3) comprises a single connection terminal (12; GATE1, GATE2, GATE3) coupled to the plurality of transistors (13; 25), or

Wherein the at least one transistor (13; 25) comprises a plurality of external transistors (13; 25), and wherein the at least one connection terminal (12; GATE1, GATE2, GATE3) comprises a plurality of connection terminals, wherein each connection terminal (12; GATE1, GATE2, GATE3) of the plurality of connection terminals is coupled to one transistor (13; 25) of the plurality of transistors (13; 25).

18. A method for calibrating a driver circuit, wherein the driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000) comprises:

a gate driver circuit arrangement (11),

a power transistor (14; 25) coupled with the gate driver circuit arrangement (11), and

at least one connection terminal (12; GATE1, GATE2, GATE3) coupled to the GATE driver circuit arrangement (11), and

a calibration memory (52) for storing a calibration data,

wherein the driver circuit (10; 20; 30; 40; 50; 60; 70; 80; 90; 231; 531; 1000) is integrated in one package, and

wherein the GATE driver circuit arrangement (11) is arranged to drive the power transistor (14; 25) and at least one external transistor (13; 25) in correspondence with each other, the at least one external transistor being coupled to the driver circuit (10; 20; 30; 40; 50; 60; 60; 70; 80; 90; 231; 531; 1000) at the at least one connection terminal (12; GATE1, GATE2, GATE3),

wherein the method comprises:

providing calibration data for the at least one external transistor (13; 25), and

storing the calibration data in the calibration memory (52).

19. The method of claim 18, wherein the method is performed under one or more of the following conditions:

the drive circuit is manufactured such that the drive circuit,

manufacturing a system including the driving circuit, or

The driver circuit repeats over the life of the driver circuit.

20. The method of claim 18 or 19, wherein the calibration data is based on one or more of the following parameters:

a resistance of the at least one external transistor (13; 25) in the on-state,

a start-up voltage of the at least one external transistor (13; 25),

a breakdown voltage of the at least one external transistor (13; 25),

steepness of the characteristic curve of the at least one external transistor (13; 25), or

-an over-current stability of the at least one external transistor (13; 25).

Technical Field

The present application relates to a driver circuit, a system having such a driver circuit and a method for calibrating a driver circuit.

Background

The driver circuit is used to drive a transistor, such as a power transistor. Such power transistors are used in various applications for converting high currents and/or high voltages. Such driver circuits usually contain a gate driver for driving the gate connections of the transistors and various diagnostic and protective functions. When the driver circuit is used to drive an external transistor, i.e. a transistor external to the driver circuit, the external transistor is controlled by a corresponding pin of the driver circuit. A plurality of simultaneously controlled transistors may also be connected to the pin.

In order to measure the current flowing through this external transistor or through these external transistors, an external measuring resistor is usually used, which is connected in series with the external transistor. The current is then measured by the voltage drop across the resistor. In case of an overcurrent, the external transistor or transistors are switched off. Such an external resistor results in additional costs and requires a corresponding pin on the driver circuit in order to provide the tapped-off voltage to the driver circuit.

Disclosure of Invention

A driver circuit, system and method for calibrating a driver circuit according to the present invention are provided herein.

According to one embodiment, there is provided a driver circuit including: the power transistor comprises a gate driver circuit arrangement, a power transistor coupled with the gate driver circuit arrangement, and at least one connection terminal coupled with the gate driver circuit arrangement. The driver circuit is integrated in one package. The gate driver circuit arrangement is arranged to drive the power transistors and at least one external transistor coupled to the driver circuit at least one connection terminal in correspondence with each other.

According to another embodiment, a system is provided having such a driver circuit and at least one external transistor coupled to at least one output.

Finally, a method for calibrating such a driver circuit is provided, the method comprising: providing calibration data for the external transistor, and storing the calibration data in the driver circuit.

The calibration data may account for parameters of the external transistor.

The above summary serves only as a brief summary of some embodiments and should not be construed as limiting, as other embodiments may have features other than those described above.

Drawings

FIG. 1 shows a block diagram of a system according to one embodiment.

FIG. 2A illustrates a block diagram of a system according to one embodiment.

FIG. 2B illustrates a detailed block diagram of a system according to one embodiment.

Fig. 3 shows a circuit diagram of a system according to an embodiment.

Fig. 4 shows a circuit diagram of a system according to an embodiment.

FIG. 5A illustrates a block diagram of a system according to one embodiment.

FIG. 5B illustrates a detailed block diagram of a system according to one embodiment.

Fig. 6 shows a circuit diagram of a system according to an embodiment.

Fig. 7 shows a circuit diagram of a system according to an embodiment.

FIG. 8 shows a circuit diagram of a system according to one embodiment.

FIG. 9 shows a circuit diagram of a system according to one embodiment.

Fig. 10 shows a circuit diagram illustrating probing of connected transistors, according to some embodiments.

FIG. 11 shows a flow diagram for illustrating a method according to various embodiments.

Detailed Description

Various embodiments are explained in detail below with reference to the drawings. These examples are used only as examples and should not be construed as limiting. In other embodiments, some features or components shown or described may be omitted or replaced by alternative features and components. In addition to the features and components explicitly described, further features or components may be provided, for example also for use in conventional driver circuits and corresponding systems.

The features of the different embodiments may be combined with each other. For example, a change or modification described with respect to one of the embodiments may also be applied to the other embodiments, and thus, the description will not be repeated.

For simplicity and better understanding, parts or elements corresponding to each other in different figures have the same reference numerals and are not explained repeatedly.

FIG. 1 shows a block diagram of a system 15 according to one embodiment. The system 15 has a driver circuit 10. The driver circuit 10 comprises a gate driver circuit arrangement 11, a power transistor 14 and a connection 12. A connection is in this sense an element of the driver circuit 10 with which an element external to the driver circuit 10 can communicate with the driver circuit 10. In the case of the system 15, an external transistor 13 is connected to the connection 12 in order to communicate with the driver circuit 10.

The driver circuit 10 is integrated in a single package. The connections 12 are then pins, pads or similar connections of the package, depending on the implementation and type of the package. The components of the driver circuit 10, in particular the gate driver circuit arrangement 11 and the power transistor 14, may be monolithically integrated on a single chip. In other embodiments, the components of the driver circuit 10 may also be implemented on separate chips, which are then arranged together in one package.

The gate driver circuit arrangement 11 drives the power transistor 14 and the external transistor 13 in order to control the power transistor 14 and the external transistor 13, for example on and off. The actuation corresponds here to one another, i.e. the external transistor 13 and the power transistor 14 are switched together so that they have the same switching behavior, for example switched on and off simultaneously. This applies within the following limits: for example due to different signal propagation times from the gate driver circuit arrangement 11 to the external transistor 13 and the power transistor 14, due to implementation differences between the external transistor 13 and the power transistor 14 and/or limits determined by other tolerances or fluctuations.

The external transistor 13 may also be a power transistor. A power transistor is understood to be a transistor designed for converting high voltages and/or high currents. The size of the power transistor on the chip may be greater than 0.5mm²To be able to conduct such large currents, and may have a size greater than10mm²The size of (2). The resistance Ron at switch-on may be 20m omega/mm²Wherein the total resistance Ron may be less than 100m omega. The power transistor may, for example, conduct a current of more than 10A, for example in the range up to 40A, and/or switch a voltage of more than 10V, for example several hundred volts.

It should be noted that fig. 1 shows only some of the possible components of the system 15. A plurality of external transistors may be used instead of a single external transistor. In addition, the driver circuit 10 may have diagnostic and/or measurement functionality. In some embodiments, measurements may be performed on the power transistor 14, for example, measurements of the current through the power transistor 14, and the current through the external transistor 13 may be derived based thereon. Examples of this will now be explained in detail with reference to further figures.

FIG. 2A illustrates a block diagram of a system according to one embodiment. The system of fig. 2A includes a driver circuit 231. The driver circuit 231 has an internal power transistor 25. The power transistor 25 may be a DMOS transistor, for example. The driver circuit 231 also has a control function 232, a protection function 234, and a diagnostic function 235. The control function 232 is used, inter alia, to drive the power transistor 25 and to drive external transistors that are controlled by the driver circuit 231. As an example, three external transistors 215A, 215B, 215C are shown in fig. 2A, which are controlled via GATE resistors via a single connection GATE1 of the driver circuit 231. The external transistors 215A, 215B, and 215C are collectively referred to as an external transistor 215 hereinafter. The number of three external transistors 215 is only to be understood as an illustrative example and fewer external transistors 215 may also be provided, for example one or two external transistors 215, or more than three external transistors 215.

The external transistor 215 is connected in parallel with the power transistor 25 between a positive supply voltage 217 and a load 218 to selectively couple the load 218 with the positive supply voltage 217.

The driver circuit 231 is controlled by a microcontroller (micro controller) 230. The microcontroller may exchange various control and diagnostic signals with the driver circuit 231. An example of this is explained in more detail later with reference to fig. 2B. The driver circuit 231 drives the power transistor 25 and the external transistor 215 in correspondence with each other so that they have substantially the same switching characteristics. Additionally, in the embodiment of fig. 2A, the external transistor 215 and the power transistor 25 have similar parameters, such as resistance in the on state, breakdown voltage, starting voltage, steepness, overcurrent stability, and the like. Thus, protection function 234 and diagnostic function 235 may draw conclusions about the current, voltage, etc. at external transistor 215 by measuring the current, voltage, etc. at power transistor 25, without requiring, for example, an external measurement resistor for measuring the current through external transistor 215. As will be described in more detail later. The current measurement of the current through the power transistor 25 may be output by the driver circuit 231 on an output IS and fed to an analog/digital converter input of the microcontroller 230, as will also be explained in more detail later.

The external wiring of the driver circuit 231 may also be as shown in fig. 2A.

Possible details of such a driver circuit 231 will now be explained in more detail with reference to fig. 2B. FIG. 2B illustrates a detailed block diagram of a system according to one embodiment. The driver circuit 20 of fig. 2B may be considered as an implementation example of the driver circuit 231 of fig. 2A.

The system of fig. 2B includes a driver circuit 20 and one or more external transistors 215, three external transistors 215A, 215BGB, 215C being shown in the illustrated example. The number of three external transistors is again only used as an example and a different number of external transistors may also be provided depending on the embodiment.

In the illustrated embodiment, the external transistor 215 is a power transistor implemented as a MOSFET.

Similar to the driver circuit 10 of fig. 1, the driver circuit 20 is integrated in one package, and may also be monolithically integrated into a single chip, or provided on multiple chips within a package. The driver circuit 20 has a connection GATE1 coupled to the GATE connection of the transistor 215.

The driver circuit 20 in turn has a power transistor 25, which is also implemented as a MOSFET. In the embodiment of fig. 2B, power transistor 25 and external transistor 215 have similar parameters. For example, these transistors can be realized in nominally the same way with respect to their dimensions and configuration, so that differences in parameters can only occur due to process fluctuations, manufacturing tolerances, etc. Similar parameters mean that parameters such as starting voltage, breakdown voltage, steepness and resistance Ron in the exact state are approximately the same, i.e. differ by a maximum of 10%, for example a maximum of 5% or a maximum of 1%. In other embodiments, the size of the transistor 215 may be different from the power transistor 25 of the driver circuit 20. This will be described in detail later.

In the illustrated embodiment, the power transistor 25 and the external transistor 215 are connected in parallel with their drain-source paths between a positive supply voltage 217 and a load 218 to optionally provide power to the load 218. To this end, the power transistor 25 and the external transistor 215 are controlled in correspondence with one another, in particular switched on and off together, such that the power transistor 25 and the external transistor 215 are jointly opened to separate the load 218 from the positive supply voltage 217 or are jointly closed to connect the load 218 with the positive supply voltage 217 in order to supply energy to the load 218.

For this purpose, the supply voltage 217 of the driver circuit 20 is transmitted to the connection VS. As shown, the connection VS is connected to the drain connection of the power transistor 25. The source connection of the power transistor 25 is connected to the connection AUS0 of the driver circuit 20. The load 218 is connected to the source connection of the transistor 215 and to the connection OUT0, as shown in fig. 2B.

The connection VS is also connected to the circuit block 21. Circuit block 21 has a supply voltage monitor that monitors whether supply voltage 217 is within an acceptable range. Further, the circuit block 21 has an overvoltage protector, which is a protection mechanism when the voltage is excessively high. Automatic restart control may also be provided in the event of a brief failure of voltage 217. In addition, in block 21, an internal supply voltage is generated from the supply voltage 217, which supplies power to the various components of the driver circuit 20. Finally, the sense output IS operated by the circuit block 21, at which a detected current can be output as described later. The circuit block 21 may be designed as in a conventional driver circuit and also have components other than those shown.

The circuit block 22 is connected to the connections UV _ SD, IN0, IN1, DEN, DSEL, IOC through which the driver circuit 20 can communicate with external components such as a microcontroller. In the case of undervoltage, circuit block 22 can be switched off by means of connection UV _ SD. The connections IN0, IN1, DEN, DSEL are used for operation and diagnostics and are first connected to a protection circuit for electrostatic discharge protection (ESD protection) and to an input logic which makes it possible to convert the levels at these connections to internal levels and/or to have signals at these connections. Further, the circuit block 22 is grounded via the connection terminal GND, and the corresponding circuit portion (GND circuit) processes and connects to the ground within the driver circuit 20.

In addition, the circuit block 22 has polarity inversion protection which protects the driver circuit 20 if the positive supply voltage 217 and ground are connected in reverse, i.e. the positive supply voltage is connected to the connection GND and ground to the connection VS. This protection is also referred to as reverse polarity protection. Circuit block 22 may also be designed as in a conventional driver circuit.

The signals on the connections IN0, IN1, DEN, DSEL may be provided, for example, by an external microcontroller IN order to control and monitor the switching of the power transistor 25 and the external transistor 215. The signal on connection IN0 is used to control power transistor 25 and external transistors 215A through 215C. A first channel is formed, represented in fig. 2B by channel 0. IN some embodiments, a further channel may be provided and controlled via the signal at connection IN1, the channel having a further power transistor internal to the driver circuit 20 and a further external transistor, which are coupled via a further connection GATE 1. This is not explicitly shown in fig. 1 and may be designed like the first channel (channel 0) described below. In other embodiments, there is only a single channel or there are more than two channels. The diagnostic function can be triggered by signals on the connections DEN and DSEL, with the diagnostic being activated by a signal on the connection DEN and the channel for the diagnostic being selected by a signal on the connection DSEL.

The diagnosis and monitoring and the driving of the first channel are performed in the circuit block 23 including the power transistor 25. This circuit block 23 is described in more detail below. The control is discussed first, followed by a discussion of various diagnostic possibilities.

To control power transistor 25 and transistor 215, the signal from connection IN0 is supplied to driver logic 28, which drives the gate controller together with charge pump 210 IN response to the signal, which generates a corresponding voltage to drive transistors 25 and 215. In the exemplary embodiment shown, the output signals of the gate controller and of the charge pump 210 are supplied to the gate connection of the power transistor 25. In addition, the signal is supplied to the GATE connection of the external transistor 215 via the GATE controller 24 and the connection GATE 1. In this way, the power transistor 25 and the external transistor 215 are driven in correspondence with each other. In some embodiments, GATE control 24 may optionally decouple the signal from GATE controller and charge pump 210 from connection GATE1 so that it can operate without external transistor 215 and/or if the voltage requirements of the transistor are different from the voltage requirements of power transistor 25, the signal may be amplified, buffered, or potential shifted to match transistor 215. The details of such circuitry will be described in more detail later. In addition, the GATE controller 24 may provide an anti-electrostatic discharge protection (ESD protection) for the connection GATE 1.

Next, the diagnostic and protection functions of the circuit block 23 will be described.

For the diagnosis, a load current detector 212 is provided which detects a current flowing through the power transistor (i.e., a drain-source current), or in other words, a current flowing from the positive power supply voltage 217 to the load 218 via the power transistor 25. The detected current can be forwarded by the driver logic and output, for example, at the output IS, in particular if a corresponding diagnostic request IS present at the connection DEN. The load current can furthermore be monitored by an overcurrent limiter 213 which switches off the transistor 25 in case of an overcurrent, i.e. in case the current is above a predetermined threshold, and switches off the external transistor 215 via the gate controller 24. In this manner, in some embodiments, damage to power transistor 25 and external transistor 215 due to excessive current may be avoided.

In the embodiment of fig. 2B, the following fact is utilized: external transistor 215 has similar parameters as power transistor 25, as described above. Thus, in the on state, approximately the same current will flow through each of the external transistors 215 and the power transistor 25. In this case, an overcurrent at the power transistor 25 therefore means that an overcurrent is also present at the external transistor 215, since the transistors have exactly approximately the same parameters, including their overcurrent characteristics. Thus, in the embodiment of FIG. 2B, no external measuring resistor or other external measuring device is required to monitor the current through external transistor 215, but this can be done by measuring the current through power transistor 25.

Any conventional circuit for current sensing may be used for load current detector 212, such as an internal measurement resistor or measurement transistor within driver circuit 20. The use of the measurement transistor will be explained in more detail later.

If the diagnostic function requires a total current, the total current through the load is equal to the detected current through the power transistors multiplied by the total number of transistors, i.e., in the example of FIG. 2B, by 4 (power transistor 25+ three external transistors 215). This may also be used to provide overcurrent monitoring for the load 218, since in this way the current through the load is also known.

Furthermore, in the embodiment of fig. 2B, a temperature sensor 26 is assigned to the power transistor 25. The over-temperature detector 29 checks whether the temperature detected by this temperature sensor 26 is higher than a threshold value. If this is the case, a warning may be output and/or the power transistor 25 may be turned off along with the external transistor 215. Finally, a voltage sensor 27 is provided for measuring the voltage across the power transistor 25. Additionally, a clamping device 214 is provided that limits the drain-source voltage to a maximum value to avoid avalanche breakdown. In the case of fig. 2A, the clamping means is used for both the power transistor 25 and the external transistor 215. The clamping means may be designed as passive clamping means alone, for example by means of a zener diode, or as active clamping means together with a transistor driven by a zener diode (in the latter case also referred to as "active zener").

Finally, driver circuit 20 includes a circuit 211 that turns on power transistor 25 and external transistor 215 when in an inverted state. This opposite state occurs when the voltage on connection OUT0 is higher than the voltage on connection VS. In this case, in a conventional power transistor implementation, the body diode of power transistor 25 and external transistor 215 will become conductive, which may result in relatively high power losses. This power loss can be limited by switching on the transistors.

It should be noted that various diagnostic functions may be implemented in a manner known per se. However, only certain diagnostic functions or other routine diagnostic functions may be provided. Unlike conventional approaches, power transistor 25 is also first provided with monitoring of external transistor 215 by providing a diagnostic function.

An example of load current measurement and overcurrent detection is now described with reference to fig. 3. Fig. 3 illustrates a portion of a driver circuit 30, particularly current sensing and overcurrent detection, such as may be used in the driver circuits of fig. 1, 2A, and 2B discussed above or one of the driver circuits discussed below.

The driver circuit 30 has the power transistor 25 already discussed. As an example, two external transistors 215 are also shown, labeled 215A and 215B. The power transistor 25 and the external transistor 215 are connected in parallel with each other between the supply voltage 217 already discussed and the load 218 also already discussed. In fig. 3, it is again assumed that the external transistor 215 has similar parameters as the power transistor 25.

Furthermore, the driver circuit 30 has a detection transistor 31 which is connected in parallel with the power transistor 25 and is scaled relative to the power transistor. The detection transistor 31 may be connected to the power transistor 25, in particular in a current mirror configuration. Between the detection transistor 31 and the power transistor 25The scale factor is denoted by k, and is also referred to as k_ILISA factor.

The current through the load 218 consists of the current IDMOS through the power transistor 25, the current Iext _1 through the external transistor 215A, and the current Iext _2 through the external transistor 215B. The current Isense through the sense transistor 31 is scaled by a scaling factor k relative to the current through the power transistor 25. The total current Iload through the load 218 is scaled with respect to the current Isense by a factor K, which is n x K, where n is the number of transistors (power transistor 25+ external transistors), thus 3 x K in the example of fig. 3. The current Isense flows through the resistor 32 to the connection OUT. Resistor 32 is used as a measurement resistor for the Isense current. For this purpose, a corresponding voltage is tapped off at the resistor 32 and supplied to a first input of the comparator 33.

Furthermore, a reference current source 35 generates a reference current Iref, which is measured by means of a measuring resistor 34. The voltage at the measuring resistor 34 is supplied to a second input of the comparator.

If the current Isense exceeds the current Iref, the power transistor 25 and the external transistor 215 are turned off based on the output of the comparator 33, and additionally the sense transistor 31 is turned off in the example of fig. 3. Overcurrent protection can be achieved in this way.

It should be noted that two separate sensing transistors may also be provided for sensing current only and for overcurrent monitoring. A corresponding embodiment is shown in fig. 4, in which more details of current detection and overcurrent monitoring are shown.

Fig. 4 shows a system according to another embodiment. A possible implementation of overcurrent detection and current measurement will be explained in more detail below, in accordance with the system of fig. 4.

The system of fig. 4 shows a driver circuit 40 with a gate driver 42 and a power transistor 25. As explained for the above-mentioned driver circuit, the driver circuit 40 may also be arranged in a package, in particular monolithically integrated on a single chip or integrated in a distributed manner on a plurality of chips arranged inside the package. The GATE driver 42 drives the power transistor 25 and, via a connection GATE1, drives one or more external transistors 215, again three of which, here, 215A to 215C are shown. As in the previous embodiment, the power transistor 25 and the external transistor 215 are connected in parallel between the positive supply voltage 217 and the load 218 to optionally power the load. The gate driver 42 has a strength sufficient to drive the power transistor 25 and a plurality of external transistors designed for the driver circuit 40 and ensures sufficiently fast switching, in particular by a corresponding rate of rise or fall of the respective gate-source voltage.

In the embodiment of fig. 4, driver circuit 40 has ESD protection circuit 43 coupled to connection GATE 1.

The gate driver 42 contains logic and can be controlled via an interface 41, for example an SPI (serial peripheral interface) interface, by a microcontroller, for example as shown in fig. 2A. The driver circuit 40 also has a first detection transistor means 44 for overcurrent detection and a second detection transistor means 45 for current measurement. As shown, the detection transistor arrangements 44 and 45 each have two transistors, which are scaled, in particular have smaller dimensions, with respect to the power transistor 25, as already explained with reference to fig. 3 for the detection transistor 31.

In the embodiment of fig. 4, one first detection transistor of each detection transistor arrangement 44, 45 is always active, and for the detection transistor arrangement 44 the second transistor can be switched on via a switch 46, and for the detection transistor arrangement 45 the second transistor can be switched on via a switch 47. In an embodiment, the switches 46, 47 may be closed when the external transistor 215 is connected to the connection terminal GATE0 of the driver circuit 40.

The switch may be opened if no external transistor is connected. This changes the effective scaling between the sense transistor means 44, 45 and the power transistor 25 and can be used to provide a current measurement corresponding to the total current through the transistor 25, 215. Referring to fig. 3, this means effectively changing by turning on one or more transistors K so that the current provided for K generation in fig. 3 is set by the sense transistor arrangement 44 or 45. Whether the external transistor 215 is provided may be detected by circuitry in the driver circuit, as will be described in detail later, or may be communicated via the interface 41.

The sense transistor device 44 is used for overcurrent sensing detection. For this purpose, a measuring resistor 48 is connected in series with the detection transistor arrangement 44. The voltage across the measuring resistor 48, which is a measure for the current through the sense transistor arrangement 44 and thus for the total current through the power transistors 25, 215, is measured by the differential amplifier 49 and fed to the logic of the gate driver 42. The logic of the gate driver 42 may compare the value thus provided with a threshold value and in case of an overcurrent, i.e. when the measured current exceeds the threshold value.

The sense transistor means 45 is also used to provide a current measurement. The source connection of the power transistor and the source connection of the detection transistor arrangement 45 are connected to a differential amplifier 410, the output of which is connected to the gate connection of a transistor 411. The source voltage of the sense transistor means 45 is regulated to the source voltage of the power transistor 25 by means of the components 410, 411. Since the drain connections are each connected to the supply voltage 217, this means that the voltage drop across the detection transistor means 45 is exactly the same (within the accuracy of the regulation) as the voltage drop across the power transistor 25, which in some embodiments may improve the accuracy of the current measurement. As shown, transistor 411 IS connected to output IS of driver circuit 40 so that in this case the current flowing through sense transistor device 45 can be shunted at output IS. It should be noted that in the case of the detection transistor arrangement 44, no such components 410, 411 are required, since here also the drain connection of the detection transistor arrangement 44 and the drain connection of the power transistor 25 are connected to one another.

It should also be noted that in other embodiments, the detection transistor arrangement 45 may also be omitted, and the output of the differential amplifier 49 may also be output at an output such as the output IS as a measure for the flowing current.

In the embodiments discussed above, the respective driver circuits have a single connection terminal (GATE1) to which one or more external transistors are coupled. Other embodiments, explained in more detail below, a first embodiment with some individual connections for a plurality of external transistors is shown in fig. 5A. The embodiment in fig. 5A corresponds to the embodiment in fig. 2A, except for the variations explained below, and elements corresponding to each other have the same reference numerals. Therefore, only the variations will be described below.

Instead of the driver circuit 231 of fig. 2A, the system of fig. 5A has a driver circuit 531 with three connections GATE1, GATE2, GATE 3. The respective external transistors 215A, 215B, and 215C are connected to each of the connection terminals GATE1, GATE2, GATE3, respectively. The transistor 215 is controlled via a driver circuit 531 in accordance with the control of the power transistor 25, as was already explained in fig. 2 for the power transistor 25 and the external transistor 215. Three connections are again provided as an example only, and two connections or more than three connections may also be provided to drive a corresponding number of external transistors 215.

In some embodiments, the connections GATE1, GATE2, GATE3 may optionally be disabled. For example, it is also possible that only the external transistor 215A is provided and the connection terminals GATE1 and GATE2 of the driver circuit 531 are disabled. The controller 232, and in particular its driver, then outputs only control signals to the power transistor 25 and the connection GATE0 to drive the external transistor 215A. For this reason, the driver circuit 531 may also be arranged to automatically recognize whether the external transistors are connected to the connection terminals GATE1, GATE2, and GATE3 and to which connection terminal. This will be described in detail later.

Fig. 5B shows a more detailed block diagram. The system of fig. 5B is a variation of the system of fig. 2B, and like elements have again been given like reference numerals and are not described again.

The system of fig. 5B has a driver circuit 50. Differences from the driver circuit 20 of fig. 2B are explained below.

Similar to the driver circuit 531 of fig. 5A, the driver circuit 50 of fig. 5B has three separate GATE connections GATE1, GATE2, and GATE3, with one of the transistors 215A, 215B, 215C connected to each of these connections. Each of the connections GATE1, GATE2, and GATE3 is coupled to a respective GATE controller 53A, 53B, 53C that provides the functionality of the GATE controller 24 of fig. 2B for each of the connections GATE1, GATE2, GATE3, respectively. To optionally deactivate the connections GATE1, GATE2, GATE3, the GATE controllers 53A, 53B, 53C may be optionally deactivated, e.g. turned off, and controlled by the GATE controllers and the charge pump 210, respectively-similar to the GATE controller 24 of fig. 2B.

The differences between the circuit block 51 of the driver circuit 50 and the corresponding circuit block 23 of the driver circuit 20 of fig. 2B are discussed next. The circuit block 51 includes, in addition to the circuit block 23, an availability check circuit 54 that checks which of the connection terminals GATE1, GATE2, and GATE3 the external transistor 215 is connected to. This implementation example will be explained later. Those of the connections GATE1 through GATE3 to which no external transistor is connected may then be deactivated. In addition, the load current detection can be adjusted accordingly, for example, by means of the switches 46, 47 as explained with reference to fig. 4.

The result of the availability checker 54 can also be transmitted via the connection to another unit, for example a microcontroller 230 (see fig. 5A), which can be used to influence various functions. For example, the absence of the external transistor 215 that should actually be present may also indicate a defective transistor. In this case, for example, certain functions in the system may be turned off. As an example, the loads 218 may include various loads in an automobile, some of which may be more important than others. If one of the external transistors 215 is not available, a secondary function, particularly a safety-independent function (e.g., seat heating), may be turned off to limit the maximum current draw through the load 218.

It should be noted that the availability checker 54 may operate at system start-up, but may also operate during system operation, for example to avoid failures. The strength of the gate controller and charge pump 210 may also be adjusted if some or all of the external transistors 215 are unavailable.

Providing the plurality of external transistors 215 may also include redundancy. For example, only one of the external transistors 215 may always be activated, and if one of the transistors is found to be unavailable, the other of the external transistors 215 is activated.

In addition, the circuit block 51 has a calibration memory 52. In contrast to the above described embodiment, this calibration memory may be used if the external transistor 215 does not have any parameters similar to the power transistor 25. In this case, for example, the current flow through each external transistor 215 may be different from the current flow through power transistor 25, and/or the breakdown and/or breakdown condition or overcurrent condition may be different. This different characteristic may be stored in the calibration memory 52 and then considered by the driver logic. For example, the current through the external transistor 215 can be deduced from the current detected by the load current detector 212 from the relation of the resistance in the on-state of the external transistor 215 (commonly referred to as Ron) and the power transistor 215, and the turn-off behavior can be initiated in case of a corresponding overcurrent.

Some details of this calibration are explained in more detail later with reference to fig. 11.

Fig. 6 shows a circuit diagram of a system according to an embodiment, showing possible implementation details of the system of fig. 5A and 5B. The system of fig. 6 has a driver circuit 60, the three external transistors 215A, 215B and 215C already discussed being in driver circuit connection at three connection terminals GATE1, GATE2 and GATE3, wherein the number of three external transistors is again used as an example. The driver circuit of fig. 6 shows the sense transistor arrangements 44, 45 and the corresponding wiring already discussed with reference to fig. 4. In addition, the driver circuit has a driver 61 with a logic which drives the detection transistor arrangements 44, 45 and the power transistor 25. The drive 61 can be actuated via the interface 41 already described.

In addition, the driver 61 may drive the external transistor 215 through the gate controllers 62, 63, and 64. For clarity, the connections from driver 61 to gate controllers 62, 63, and 64 are not shown. The connections GATE1, GATE2 and GATE3 may optionally be deactivated by the GATE controllers 62, 63, 64, or the external transistors 215A, 215B, 215C may optionally be controlled, in particular.

Furthermore, the driver circuit 16 comprises an availability check circuit 65 which is arranged to check which external transistor 215 is available, i.e. which external transistor is connected to the respective connection terminal GATE1, GATE2, GATE3 and is operable, e.g. fault-free.

For this purpose, as shown, the availability checker 65 is connected on the one hand to each of the connections GATE1, GATE2, GATE3 and on the other hand to the connection OUT via a resistor 66. By connecting to the connections GATE1, GATE2, GATE3, the availability check circuit 65 "knows" which external transistor 215 should be switched on. For example, to test the availability, the driver 61 may sequentially drive the gate controllers 62, 63, 64 that turn on the respective transistors 215A, 215B, 215C. It can then be detected by means of the resistor 66 whether this connection causes a corresponding voltage change at the connection OUT. If this is the case, the corresponding transistor is available.

Such testing may be performed at start-up and during operation of the driver circuit 60, for example during periods when the load 218 does not need to be powered.

Fig. 7 shows another embodiment of the system, which is a variation of the system of fig. 6.

The system of fig. 7 includes a driver circuit 70. In contrast to the driver circuit 60 in fig. 6, the driver circuit 70 has a separate GATE driver 71, 72, 73 for each connection GATE1, GATE2, GATE 3. These individual gate drivers may be controlled by the logic of gate driver 61 or directly by the microcontroller through interface 41. During operation, the gate driver 61 and the gate drivers 71 to 73 are controlled in such a way that the power transistor 25 and the external transistor 215 are driven in correspondence with each other, as already explained. If the availability check circuit 65 indicates that one or more of the external transistors 215 are not available, the corresponding GATE driver 71, 72, 73 is disabled, and the corresponding output GATE1, GATE2, or GATE3 is disabled.

An implementation example of such a gate driver is shown in fig. 8. Fig. 8 shows a system with a part of a driver circuit 80, which is in turn connected, by way of example, with three external transistors 215 at respective connection terminals GATE1, GATE2 and GATE 3. Other portions of the driver circuit 80 may be implemented as in the embodiments described above.

In block 82, the driver circuit 80 has the power transistor 25 already discussed together with the sense transistor means 44 and 45. The power transistor 25 and the sense transistor means 44, 45 are driven by a first driver 86. As shown, the first driver 86 primarily has a high-side switch and a low-side switch with which the output node of the driver can be selectively connected to either a high-side current source or a low-side current source. The first driver is connected between a supply voltage VCP 85 provided by the charge pump and-the output OUT via a resistor 83.

For driving the external transistors 215A, 215B, 215C, respective second drivers 81A, 81B and 81C are provided, which are constructed analogously to the first driver 86. To turn ON the power transistor 25 and the external transistor 215, the first driver 86 and the second drivers 81A to 81C are driven with a signal ON to close the high-side switch when the low-side switch is open. To turn OFF the transistors, the drivers 86, 81A, 81B and 81C are correspondingly controlled with signal OFF to close the low-side switch when the high-side switch is OFF. In the embodiment, this driving is performed in common for all the drivers 86, 81A, 81B, 81C, so that the transistors can be driven in correspondence with each other. If a usability checker is provided as described above, some of the drivers 81A to 81C may be disabled (no external transistor 215 is available at their associated connections GATE1 to GATE 2), for example where both the high-side switch and the low-side switch are open.

Another system is shown in fig. 9. The system of fig. 9 has a driver circuit 90 with the already discussed power transistor 25, which connects the two external transistors 215A, 215B at the two connection terminals GATE1, GATE2 as an example. Also, the number of two external transistors is merely an example.

Other parts of the driver circuit 90, in particular for current detection, may be implemented as described in the previous embodiments. The main purpose of fig. 9 is to give another example for implementing a gate driver.

The driver circuit 90 has a charge pump 91 that supplies voltages to all gate drivers described below. In the example shown, the charge pump 91 is a Dickson (Dickson) charge pump. Other types of charge pumps may also be used.

A driver circuit 94 is provided for driving the power transistor 25, and driver circuits 96A, 96B are provided for driving the external transistors 215A, 215B. Similar to the driver circuits 86, 81A-81C discussed with reference to fig. 8, the driver circuits 94, 96A, 96B have a high-side switch, a low-side switch, a high-side current source, and a low-side switch. In the embodiment as already discussed with reference to fig. 8, the high-side and low-side switches of the driver circuit are driven by common control signals (ON and OFF in fig. 8) such that the power transistor 25 and the external transistor 215 are driven in correspondence with each other. At least the high-side current sources of the driver circuits 94, 96A and 96B are driven to provide the same current or currents having a predetermined relationship to each other. This is achieved in fig. 9 in that all driver circuits 94, 96A, 96B are supplied with the same reference current iRef, on the basis of which the current sources are regulated. The reference current iRef may be generated by a reference current source. In other embodiments, the current of the high-side current source of one of the driver circuits (e.g., driver circuit 94) may be delivered to the other driver circuits (e.g., 96A, 96B) by means of a current mirror as a reference current.

In addition, a clamping device 95 is assigned to the driver 94 and respective clamping devices 97A, 97B are assigned to the drivers 96A, 96B. These clamping devices are used to limit the drain-source voltage of the respective transistor to a maximum value to prevent avalanche breakdown, as is the clamping arrangement 214 already described with reference to fig. 2B. As described for the clamping means 214, this may be realized by means of a zener diode. In contrast to fig. 2B, in fig. 9 a single clamping means is provided for each transistor (power transistor 25 and external transistor 215).

Fig. 10 shows a more detailed embodiment of the availability check circuit as used in various embodiments. This circuit is illustrated in the example of the external transistor 215 being driven by the driver 1003A. Other drivers (as designated by 1003B) may be provided for other external transistors.

The circuit of fig. 10 is based on the fact that: in monitoring the charging of the transistor, the gate-source voltage (or gate voltage) should rise to the Miller plateau of the external transistor 215 (MOSFET in the example of fig. 10). In the case where no external transistor 215 is available, a current source may be utilized to pull the gate-source voltage or gate voltage to 0V.

To check for availability, a high-side switch 1001 or a low-side switch 1002 connected to the respective current source is provided, which can be switched in an attempt to pull down the gate-source voltage, for example at a frequency in the range of 1 kHz. This may be done, for example, in a state where the external transistor 215 is turned on by the driver 1003A. If the external transistor 2015 is available and the gate is fully charged, it is almost impossible to pull the gate voltage to 0V at this frequency, i.e., the gate voltage varies only slightly, e.g., in the range of 100 mV. Conversely, if the external transistor 215 is not available, e.g., is not connected or has a fault, the voltage may be pulled down to about 0V. This can be detected using a comparator.

Drivers 1003A, 1003B are supplied via charge pump 96. As a comparator, for example, a set-reset flip-flop 1005 can be used together with a preceding (bergahelten) schmitt flip-flop, which is connected to the output OUT via a switch 1007, optionally via a resistor 1008.

As already explained, the current threshold value can be set depending on the availability, or the drive strength can be set accordingly.

As already explained with reference to fig. 5B, in embodiments where the parameters of the external transistor are different from the parameters of the power transistor of the driver circuit, calibration data may be stored in the calibration memory. A corresponding method for this purpose will now be described with reference to fig. 11.

At 1100, the method of FIG. 11 includes providing calibration data. If the manufacturer of the driver also provides a specific transistor as an external transistor for the driver circuit, this provision can be implemented on the part of the manufacturer of the respective driver circuit (see driver circuit described above). However, this can also be achieved by the system manufacturer (system with driver circuits and external transistors), for example, combining an external transistor of one manufacturer with a driver circuit of another manufacturer to produce a system. The calibration data may comprise parameters of the external transistor, such as resistance Ron in the on-state, breakdown voltage, overcurrent source, usage, etc., or a ratio of these parameters to parameters of a power transistor (e.g. 25) of the driver circuit. These parameters may be provided by the manufacturer of the external transistor. They can also be determined repeatedly during operation by corresponding measurements, for example at predetermined time intervals, in order to adapt the calibration to the aging of the external transistor.

At 1101, the method includes storing calibration data in a driver circuit.

At 1102, the calibration data is then used in the operation of the driver circuit in order to be able to draw conclusions about the current through the external transistor from the calibration data from the current measurement, which is carried out on the basis of the current through the power transistor of the driver circuit, and/or to provide overcurrent monitoring for the external transistor by means of the calibration data, as has been briefly described in fig. 5B.

The following examples define some embodiments:

example 1. a driver circuit includes:

a gate driver circuit device for a semiconductor device,

a power transistor coupled to the gate driver circuit arrangement, and

at least one connection terminal coupled to the gate driver circuit arrangement,

wherein the gate driver circuit arrangement is arranged to drive the power transistor and the at least one external transistor in correspondence with each other, the at least one external transistor being coupled to the driver circuit at the at least one connection,

wherein the driver circuit is integrated in one package.

Example 2. the driver circuit according to example 1, further comprising a current monitoring circuit arranged to monitor a current through the power transistor.

Example 3. the driver circuit according to example 1 or 2, wherein the current monitoring circuit comprises a detection transistor scaled relative to the power transistor and configured to monitor the current through the power transistor based on the current through the detection transistor.

Example 4. the driver circuit according to example 2 or 3, further comprising a calibration memory in which information about the performance of the at least one external transistor compared to the power transistor is stored, wherein the current monitoring circuit is arranged to monitor the current flow through the at least one external transistor based on the current through the power transistor and the information.

Example 5. the driver circuit of any of examples 2 to 4, wherein the driver circuit is configured to turn off the power transistor and the at least one external transistor when a current through the power transistor indicates an overcurrent event.

Example 6. the driver circuit according to any one of examples 1 to 5, wherein at least one connection terminal can be optionally disabled.

Example 7. the driver circuit according to example 6, wherein the at least one connection terminal comprises a plurality of connection terminals, wherein each of the plurality of connection terminals can be selectively disabled.

Example 8. the driver circuit according to example 6 or 7, further comprising an availability checker configured to detect whether an external transistor is available at the at least one connection terminal, and to optionally deactivate the at least one connection terminal in dependence on the detection.

Example 9. the driver circuit of any of examples 1 to 8, the gate driver circuit arrangement having a single gate driver for driving the power transistor and at least the external transistor.

Example 10. the driver circuit of any of examples 1 to 8, wherein the gate driver circuit arrangement has a first gate driver to drive the power transistor and at least one second gate driver to drive the at least one external transistor.

Example 11 the driver circuit of any of examples 10 and 6 to 8, wherein the optionally disabling includes optionally disabling at least one second gate driver associated with the at least one connection terminal.

Example 12. the driver circuit according to any one of examples 1 to 11, the driver circuit monolithically integrated on a chip.

Example 13 the driver circuit of any of examples 1 to 11, wherein the driver circuit is integrated on two or more chips disposed in a package.

Example 14. a system, comprising:

at least one external transistor, and

a driver circuit, comprising:

a gate driver circuit device for a semiconductor device,

a power transistor coupled to the gate driver circuit arrangement, and

at least one connection terminal coupled to the gate driver circuit arrangement,

wherein the driver circuit is integrated in one package,

wherein at least one external transistor is coupled to at least one connection terminal, an

Wherein the gate driver circuit is configured to drive the power transistor and the at least one external transistor in correspondence with each other.

Example 15. according to the system of example 14, the driver circuit is designed according to any one of examples 1 to 13.

Example 16 the system of examples 14 or 15, wherein the driver circuit comprises a current monitoring circuit arranged to monitor a current through the power transistor.

Example 17. the system of example 16, wherein the current monitoring circuit includes a detection transistor scaled relative to the power transistor, and the current monitoring circuit is configured to monitor the current through the power transistor based on the current through the detection transistor.

Example 18. the system according to example 16 or 17, wherein the driver circuit further comprises a calibration memory in which information about the performance of the at least one external transistor compared to the power transistor is stored, wherein the current monitoring circuit is arranged to monitor the current flow through the at least one external transistor based on the current through the power transistor and the information.

Example 19 the system of any of examples 16 to 18, wherein the driver circuit is configured to turn off the power transistor and the at least one external transistor when a current through the power transistor indicates an over-current event.

Example 20. the system of any of examples 14 to 19, wherein at least one connection end can be optionally disabled.

Example 21. the system of example 20, wherein the at least one connection end comprises a plurality of connection ends, wherein each of the plurality of connection ends can be selectively deactivated.

Example 22 the system of examples 20 or 21, wherein the driver circuit further comprises an availability checker configured to detect whether an external transistor is available at the at least one connection terminal, and to selectively deactivate the at least one connection terminal in dependence on the detection.

Example 23. the system of any of examples 14 to 22, wherein the gate driver circuitry has a single gate driver to drive the power transistor and at least the external transistor.

Example 24. the system of any of examples 14 to 23, wherein the gate driver circuitry has a first gate driver to drive the power transistor and at least one second gate driver to drive the at least one external transistor.

Example 25 the system of any of examples 24 and 20 to 22, wherein the optionally disabling includes disabling at least one second gate driver associated with the at least one connection terminal.

Example 26. the system of any of examples 14 to 25, wherein the driver circuit is monolithically integrated on a chip.

Example 27. the system of any of examples 14 to 25, wherein the driver circuit is integrated on two or more chips arranged in a package.

Example 28. the system of any of examples 14 to 27, wherein the at least one external transistor and the power transistor have similar parameters.

Example 29. the system of example 28, wherein the parameters include one or more of the following:

the resistance of the at least one external transistor in the on-state,

the start-up voltage of at least one external transistor,

the breakdown voltage of at least one of the external transistors,

the steepness of the characteristic curve of the at least one external transistor,

type of at least one external transistor, or

Overcurrent stability of at least one external transistor.

Example 30. the system of any of examples 14 to 29, wherein the at least one external transistor comprises a plurality of external transistors, and wherein the at least one connection comprises a single connection coupled to the plurality of transistors.

Example 31 the system of any of examples 14 to 29, wherein the at least one transistor comprises a plurality of external transistors, and wherein the at least one connection comprises a plurality of connections, each connection of the plurality of connections being coupled to a transistor of the plurality of transistors.

Example 32 a method of calibrating a driver circuit, the driver circuit comprising:

a gate driver circuit device for a semiconductor device,

a power transistor coupled to the gate driver circuit arrangement, and

at least one connection terminal coupled to the gate driver circuit arrangement, and

the memory is calibrated in such a way that,

wherein the driver circuit is integrated in one package, an

Wherein the gate driver circuit arrangement is arranged to drive the power transistor and the at least one external transistor in correspondence with each other, the at least one external transistor being connected to the driver circuit at the at least one connection terminal,

wherein the method comprises the following steps:

providing calibration data for at least one external transistor, an

The calibration data is stored in a calibration memory.

Example 33. the method of example 32, wherein the method is performed in one or more of:

the manufacture of the drive circuit is carried out,

manufacturing a system including a driving circuit, or

The operation is repeated over the life of the driver circuit.

Example 34. the method of example 32 or 33, wherein the calibration data is based on one or more of the following parameters:

the resistance of the at least one external transistor in the on-state,

the start-up voltage of at least one external transistor,

the breakdown voltage of at least one of the external transistors,

steepness of characteristic curve of at least one external transistor, or

Overcurrent stability of at least one external transistor.

Example 35. the method of any of examples 32 to 34, wherein the driver circuit is designed according to any of examples 1 to 13, and/or the driver circuit of the system is designed according to any of examples 1 to 31.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention as defined by the claims. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. It is therefore intended that this invention be limited only by the claims and the equivalents thereof.