阅读说明：本技术 适用于低功耗cmos ldo的折返式限流保护电路 (Foldback current-limiting protection circuit suitable for low-power-consumption CMOS LDO ) 是由 徐飞 靳瑞英 朱丽丽 于 2021-02-20 设计创作，主要内容包括：本发明公开了适用于低功耗CMOS LDO的折返式限流保护电路,应用于模拟电路技术和半导体集成电路技术领域,包括电流采样单元、第一基准电流单元、导通控制单元、第二基准电流单元和功率管单元；电流采样单元与第一基准电流单元、导通控制单元、功率管单元连接；电流采样单元用于检测功率管单元电流；导通控制单元与所述第二基准电流单元连接；本发明可以更好得保护芯片在过流尤其时短路时候不至于因发热而损坏；该电路亦可应用于其他需要根据输出调节电路限流电流的应用场景。(The invention discloses a foldback current-limiting protection circuit applicable to a low-power-consumption CMOS LDO (complementary metal oxide semiconductor) and applied to the technical fields of analog circuit technology and semiconductor integrated circuits, wherein the foldback current-limiting protection circuit comprises a current sampling unit, a first reference current unit, a conduction control unit, a second reference current unit and a power tube unit; the current sampling unit is connected with the first reference current unit, the conduction control unit and the power tube unit; the current sampling unit is used for detecting the current of the power tube unit; the conduction control unit is connected with the second reference current unit; the invention can better protect the chip from being damaged by heating when the chip is subjected to overcurrent and particularly short circuit; the circuit can also be applied to other application scenes which need to regulate the current limiting current of the circuit according to the output.)

1. The foldback current-limiting protection circuit applicable to the low-power-consumption CMOS LDO is characterized by comprising a current sampling unit (1), a first reference current unit (3), a conduction control unit (4), a second reference current unit (5) and a power tube unit (6);

the current sampling unit (1) is connected with the first reference current unit (3), the conduction control unit (4) and the power tube unit (6); the current sampling unit (1) is used for detecting the current of the power tube unit (6); the power tube unit (6) is used for comparing with the sampling current of the current sampling unit (1) and setting the first reference current unit (3) of a current limiting point; the power tube unit (6) is used for controlling the conduction control unit (4) and setting the second reference current unit (5);

the conduction control unit (4) is connected with the second reference current unit (5).

2. The foldback current limit protection circuit suitable for a low-power CMOS LDO according to claim 1,

the current sampling unit (1) comprises a first PMOS (P-channel metal oxide semiconductor) tube (11), a second PMOS tube (12), a third PMOS tube (15), a third reference current source (13) and a sampling resistor (14);

the source electrode of the first PMOS tube (11) is connected with an LDO power supply VCC, and the drain electrode and the grid electrode of the first PMOS tube are connected with the third reference current source (13);

the source electrode of the second PMOS tube (12) is connected with one end of the sampling resistor (14), the grid electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube (11), and the drain electrode of the second PMOS tube is the output end of sampling current;

the source electrode of the third PMOS tube (15) is connected with one end of the sampling resistor (14), the grid electrode of the third PMOS tube (15) is connected with the grid electrode of the power tube unit (6), and the drain electrode of the third PMOS tube is connected with the LDO voltage output end;

one end of the sampling resistor (14) is connected with an LDO power supply VCC, and the other end of the sampling resistor is connected with the source electrode of the second PMOS tube (12) and the source electrode of the third PMOS tube (15).

3. The foldback current limit protection circuit suitable for a low-power CMOS LDO of claim 2,

the conduction control unit (4) comprises a first NMOS (N-channel metal oxide semiconductor) tube (41) and a second NMOS tube (42), the grid electrode of the first NMOS tube (41) is connected with the internal reference of the LDO, the drain electrode of the first NMOS tube (41) is connected with the drain electrode of the first PMOS tube (11) of the current sampling unit (1), and the source electrode of the first NMOS tube (41) is in short circuit with the source electrode of the second PMOS tube (42);

the source electrode of the second NMOS tube (42) is connected with the drain electrode of the third PMOS tube (15) of the sampling current unit (1), and the grid electrode of the second NMOS tube is connected with the second reference current unit (5).

4. The foldback current limit protection circuit suitable for a low-power CMOS LDO according to claim 3,

the LDO internal reference is a direct current level inside the LDO.

5. The foldback current limit protection circuit suitable for a low-power CMOS LDO according to claim 1,

the power tube unit (6) comprises a fourth PMOS tube (61), the source electrode of the fourth PMOS tube (61) is connected with the LDO power VCC, the grid electrode of the fourth PMOS tube is connected with the input end of the power tube unit (6), and the drain electrode of the fourth PMOS tube is connected with the LDO voltage output end.

6. The foldback current limit protection circuit suitable for a low-power CMOS LDO according to claim 1,

the current limiting point is a connection point of a sampling current output end of the current sampling unit (1) and the first reference current unit (3).

7. The foldback current limiting protection circuit suitable for a low-power CMOS LDO according to any one of claims 1 to 6,

the current limiting device is characterized by further comprising an inverting driving unit (3), wherein the input end of the inverting driving unit (3) is connected with the current limiting point, and the output end of the inverting driving unit is connected with the input end of the power tube unit (6).

Technical Field

The invention relates to the technical field of analog circuits and semiconductor integrated circuits, in particular to a foldback current-limiting protection circuit suitable for a low-power-consumption CMOS LDO (complementary metal oxide semiconductor) device.

Background

The LDO has the advantages of low cost, small requirement on peripheral devices, low output noise, small static current and the like, and is widely applied to various power supply occasions. With the development of communication technology, especially the wide application of 5G, the devices tend to be miniaturized and have low power consumption. The miniaturization is realized by packaging the PCB in a smaller size, and peripheral devices need to be simplified so as to save precious PCB space; the power consumption is as low as possible on the basis of meeting the load requirement so as to prolong the working time of the terminal equipment powered by the battery. Based on this, LDOs become a very suitable power supply option. The reliable operation of the LDO can not be realized without the cooperative work of various protection modules, such as over-temperature, over-voltage, over-current and the like. The overcurrent protection is an important function, and can protect the chip from being damaged due to overheating when the chip is in output overload or output short circuit or other abnormalities.

The conventional LDO output current limiting technique is shown in fig. 1. The sampling tube 02 is used for sampling the current of the power tube and injecting the current into the resistor 05 to generate sampling voltage, and the sampling voltage is compared with the internal reference VREF and then passes through the error amplifier 04 to control the output current of the power tube 03. The sampling tube 02 with the structure and the power tube 03 with the overlarge proportion can cause inaccurate sampling, and the chip area waste can be caused by the overlarge proportion. The structure can maintain the chip at a fixed current limiting point IL when the chip is in overcurrent, so that when the chip is in short circuit, the chip bearing power is close to the level of VCC IL, great heat generation is realized, and the risk of heat generation and damage is caused.

Therefore, it is an urgent need to solve the problem of the art to provide a foldback current limiting protection circuit suitable for a low power consumption CMOS LDO to protect a chip from being damaged due to excessive heat generation to the maximum extent.

Disclosure of Invention

In view of the above, the present invention provides a foldback current limiting protection circuit suitable for a low power consumption CMOS LDO.

In order to achieve the purpose, the invention adopts the following technical scheme:

a foldback current limiting protection circuit suitable for low-power consumption CMOS LDO includes:

the device comprises a current sampling unit, a first reference current unit, a conduction control unit, a second reference current unit and a power tube unit;

the current sampling unit is connected with the first reference current unit, the conduction control unit and the power tube unit; the current sampling unit is used for detecting the current of the power tube unit; the power tube unit is used for comparing with the sampling current of the current sampling unit and setting the first reference current unit of a current limiting point; the power tube unit is used for controlling the conduction control unit and setting the second reference current unit;

the conduction control unit is connected with the second reference current unit.

Preferably, the current sampling unit comprises a first PMOS transistor, a second PMOS transistor, a third reference current source and a sampling resistor;

the source electrode of the first PMOS tube is connected with an LDO power supply VCC, and the drain electrode and the grid electrode of the first PMOS tube are connected with the third reference current source;

the source electrode of the second PMOS tube is connected with one end of the sampling resistor, the grid electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube, and the drain electrode of the second PMOS tube is the output end of the sampling current;

the source electrode of the third PMOS tube is connected with one end of the sampling resistor, the grid electrode of the third PMOS tube is connected with the grid electrode of the power tube unit, and the drain electrode of the third PMOS tube is connected with the LDO voltage output end;

one end of the sampling resistor is connected with an LDO power VCC, and the other end of the sampling resistor is connected with the source electrode of the second PMOS tube and the source electrode of the third PMOS tube.

The conduction control unit comprises a first NMOS tube and a second NMOS tube, the grid electrode of the first NMOS tube is connected with the internal reference of the LDO, the drain electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube of the current sampling unit, and the source electrode of the first NMOS tube is in short circuit with the source electrode of the second PMOS tube;

and the source electrode of the second NMOS tube is connected with the drain electrode of the third PMOS tube of the sampling current unit, and the grid electrode of the second NMOS tube is connected with the second reference current unit.

Preferably, the LDO internal reference is a dc level inside the LDO.

Preferably, the power tube unit includes a fourth PMOS tube, a source of the fourth PMOS tube is connected to the LDO power VCC, a gate of the fourth PMOS tube is connected to the input terminal of the power tube unit, and a drain of the fourth PMOS tube is connected to the LDO voltage output terminal.

Preferably, the current limiting point is a connection point of a sampling current output end of the current sampling unit and the first reference current unit.

Preferably, the power tube unit further comprises an inverting drive unit, an input end of the inverting drive unit is connected with the current limiting point, and an output end of the inverting drive unit is connected with an input end of the power tube unit.

Preferably, the working current of a third reference current unit in the current sampling unit is less than 1 microampere, and the size ratio of the first PMOS transistor to the second PMOS transistor is 1: and N, the size of the current limiting point can be changed by adjusting the value of N.

Preferably, the maximum working current of the second PMOS transistor in the current sampling unit is less than 1 microampere.

Preferably, the internal reference in the conduction control unit may be any LDO internal relatively stable dc level.

Preferably, the first NMOS transistor in the turn-on control unit is not limited in kind, and may be enhancement type, depletion type or Native type.

Preferably, the second NMOS transistor in the turn-on control unit is not limited in kind, and may be enhancement type, depletion type or Native type.

Preferably, the first NMOS transistor and the second NMOS transistor are enhancement type, depletion type or Native type, and different current-limiting foldback curves can be obtained.

According to the technical scheme, compared with the prior art, the foldback current-limiting protection circuit applicable to the low-power-consumption CMOS LDO is provided, so that a chip can be better protected from being damaged due to heating when overcurrent, particularly short circuit occurs; the circuit can also be applied to other application scenes which need to regulate the current limiting current of the circuit according to the output.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a schematic diagram of a conventional LDO current-limiting protection circuit;

FIG. 2 is a block diagram of a foldback current limiting protection circuit suitable for a low power consumption CMOS LDO according to the present invention;

FIG. 3 is a schematic diagram of a circuit structure of a current sampling unit according to the present invention;

FIG. 4 is a circuit diagram of a conduction control unit according to the present invention;

FIG. 5 is a schematic diagram of a foldback current limiting protection circuit suitable for a low power consumption CMOS LDO according to the present invention;

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, in order to sample the power tube current injection resistor 05 mainly through the sampling tube 02 to generate a sampling voltage, the sampling voltage is compared with an internal reference VREF and then passes through an error amplifier 04 to control the output current of the power tube 03. The sampling tube 02 with the structure and the power tube 03 with the overlarge proportion can cause inaccurate sampling, and the chip area waste can be caused by the overlarge proportion. The structure can maintain the chip at a fixed current limiting point IL when the chip is in overcurrent, so that when the chip is in short circuit, the chip bearing power is close to the level of VCC IL, great heat generation is realized, and the risk of heat generation and damage is caused.

Example 1

Referring to fig. 2, a block diagram of a foldback current-limiting protection circuit suitable for a low-power CMOS LDO is disclosed, including a current sampling unit 1, a first reference current unit 3, a conduction control unit 4, a second reference current unit 5, and a power tube unit 6;

the current sampling unit 1 is connected with the first reference current unit 3, the conduction control unit 4 and the power tube unit 6; the current sampling unit 1 is used for detecting the current of the power tube unit 6; the power tube unit 6 is used for comparing with the sampling current of the current sampling unit 1 and setting a first reference current unit 3 of a current limiting point; the power tube unit 6 is used for controlling the conduction control unit 4 and setting a second reference current unit 5;

the conduction control unit 4 is connected to the second reference current unit 5.

In a specific embodiment, referring to fig. 3, the current sampling unit 1 includes a first PMOS transistor 11, a second PMOS transistor 12, a third PMOS transistor 15, a third reference current source 13, and a sampling resistor 14;

the source electrode of the first PMOS tube 11 is connected with an LDO power supply VCC, and the drain electrode and the grid electrode are connected with a third reference current source 13;

the source electrode of the second PMOS tube 12 is connected with one end of the sampling resistor 14, the grid electrode is connected with the grid electrode of the first PMOS tube 11, and the drain electrode is the output end of the sampling current;

the source electrode of the third PMOS tube 15 is connected with one end of the sampling resistor 14, the grid electrode of the third PMOS tube 15 is connected with the grid electrode of the power tube unit 6, and the drain electrode is connected with the LDO voltage output end;

one end of the sampling resistor 14 is connected to the LDO power VCC, and the other end is connected to the source of the second PMOS transistor 12 and the source of the third PMOS transistor 15.

The power tube driving circuit further comprises an inverting driving unit 3, wherein the input end of the inverting driving unit 3 is connected with the current limiting point, and the output end of the inverting driving unit 3 is connected with the input end of the power tube unit 6.

In an embodiment, referring to fig. 4, the conduction control unit 4 includes a first NMOS transistor 41 and a second NMOS transistor 42, a gate of the first NMOS transistor 41 is connected to the LDO internal reference, a drain of the first NMOS transistor 41 is connected to the drain of the first PMOS transistor 11 of the current sampling unit 1, and a source of the first NMOS transistor is shorted with a source of the second NMOS transistor 42;

the source of the second NMOS transistor 42 is connected to the drain of the third PMOS transistor 15 of the sampling current unit 1, and the gate thereof is connected to the second reference current unit 5.

In a specific embodiment, the internal reference in the conduction control unit 4 can be any LDO internal relatively stable dc level.

In an embodiment, the power transistor unit 6 includes a fourth PMOS transistor 61, a source of the fourth PMOS transistor 61 is connected to the LDO power VCC, a gate of the fourth PMOS transistor is connected to the input terminal of the power transistor unit 6, and a drain of the fourth PMOS transistor is connected to the LDO voltage output terminal.

In a specific embodiment, the current limiting point is a connection point of the sampled current output terminal of the current sampling unit 1 and the first reference current unit 3.

In a specific embodiment, the operating current of the third reference current unit 13 in the current sampling unit 1 is less than 1 microampere, and the size ratio of the first PMOS transistor 11 to the second PMOS transistor 12 is 1: and N, the size of the current limiting point can be changed by adjusting the value of N.

In a specific embodiment, the maximum operating current of the second PMOS transistor 12 in the current sampling unit 1 is less than 1 microampere.

In a specific embodiment, the internal reference in the conduction control unit 4 can be any LDO internal relatively stable dc level.

In one embodiment, the first NMOS transistor 41 of the turn-on control unit 4 is not limited in kind, and may be an enhancement type, a depletion type or a Native type.

In one embodiment, the second NMOS transistor 42 of the turn-on control unit 4 is not limited in kind, and may be an enhancement type, a depletion type or a Native type.

In another embodiment, the first NMOS transistor 41 and the second NMOS transistor 42, which are enhancement type, depletion type or Native type, may have different current-limiting foldback curves.

Example 2

Referring to fig. 5, the present embodiment discloses a foldback current limiting protection circuit suitable for a low power consumption CMOS LDO, which has the following working principle:

the sampling current Is proportional to the current of the power tube unit 6 Is obtained by the current sampling unit 1 of the power tube unit 6. The sampling current Is compared with the first reference current unit 22 to generate a comparison voltage Verror at 202, and the comparison voltage Verror Is amplified by the inverting driving unit 2 to control the current flowing through the power tube unit 6, wherein the current Is the current-limiting current IL. Meanwhile, the LDO voltage output terminal 206 is connected to the gate of the second NMOS transistor 42 of the conduction control unit 4 to control VGS of the second NMOS transistor 42, and further control the current flowing through the conduction control unit 4, and the smaller the output voltage, the larger the current flowing through the conduction control unit 4. And when the output of the LDO voltage output terminal 206 is short-circuited to ground, the current flowing through the conduction control unit 4 reaches the maximum value, which is the current of the second reference current unit 5, and at this time, after loop control, the current flowing through the power tube unit 6 reaches the minimum value Ishort. At this time, the heat generation power consumption of the chip itself is VCC iphart, which is smaller than the power consumption VCC IL when the control circuit is turned on. The heating problem when the chip is overloaded and short-circuited can be reduced to the maximum extent by reasonably setting the Ishort value.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention in a progressive manner. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.