阅读说明：本技术 用于针对非易失性存储器进行信息保护的方法和设备 (Method and apparatus for information protection for non-volatile memory ) 是由 戴昌宪 于 2020-03-30 设计创作，主要内容包括：本发明提供一种用于针对非易失性存储器进行信息保护的方法和设备,其中该方法应用于控制器。该方法包括：取得第一裸片依赖性种子与第二裸片依赖性种子,其中该第一裸片依赖性种子与该第二裸片依赖性种子对应于用来实施该非易失性存储器的裸片；依据该第一裸片依赖性种子对一地址的多组地址信息进行重新排列,以保护该控制器与该非易失性存储器之间的至少一个地址信号所载的该地址；以及依据该第二裸片依赖性种子对一组数据的多个子集合进行重新排列,以保护该控制器与该非易失性存储器之间的至少一个数据信号所载的该组数据。(The invention provides a method and a device for protecting information for a nonvolatile memory, wherein the method is applied to a controller. The method comprises the following steps: obtaining a first die dependency seed and a second die dependency seed, wherein the first die dependency seed and the second die dependency seed correspond to dies used to implement the non-volatile memory; rearranging sets of address information for an address according to the first die dependency seed to protect the address carried by at least one address signal between the controller and the non-volatile memory; and rearranging a plurality of subsets of a set of data according to the second die-dependent seed to protect the set of data carried by at least one data signal between the controller and the non-volatile memory.)

1. A method for information protection for a non-volatile memory, the method applied to a controller, the method comprising:

obtaining a first die dependency seed and a second die dependency seed, wherein the first die dependency seed and the second die dependency seed correspond to dies used to implement the non-volatile memory;

rearranging sets of address information for an address in accordance with the first die-dependent seed to protect the address carried by at least one address signal between the controller and the non-volatile memory; and

rearranging a plurality of subsets of a set of data to protect the set of data carried by at least one data signal between the controller and the non-volatile memory in accordance with the second die-dependent seed.

2. The method of claim 1, wherein the controller comprises a storage unit; and the step of obtaining the first die dependency seed and the second die dependency seed further comprises:

obtaining at least one die dependency seed of the first die dependency seed and the second die dependency seed from the storage unit, wherein the at least one die dependency seed was previously stored in the storage unit.

3. The method of claim 1, wherein the rearranging of the sets of address information for the address in accordance with the first die dependency seed further comprises:

swapping two or more address lines of a set of address lines in accordance with the first die-dependent seed with a set of switches to rearrange the sets of address information for the addresses.

4. The method of claim 1, wherein the rearranging of the plurality of subsets of the set of data in accordance with the second die dependency seed further comprises:

swapping, with a set of switches, two or more data lines of a set of data lines in accordance with the second die-dependent seed to rearrange the plurality of subsets of the set of data.

5. The method of claim 1, wherein the step of taking the first die dependency seed and the second die dependency seed further comprises:

parsing a header in information from the non-volatile memory to retrieve at least one of the first die dependency seed and the second die dependency seed from the header.

6. The method of claim 1, further comprising:

generating an initial seed using a seed generator in the controller, wherein the initial seed is updated over time;

respectively converting the initial seed into a plurality of conversion seeds for data conversion by using a plurality of seed converters in the controller, wherein the plurality of conversion seeds are updated as the initial seed changes, and the plurality of conversion seeds comprise a first conversion seed and a second conversion seed; and

determining whether an integrity code transfer function is enabled according to the first conversion seed to generate a first determination result, wherein the integrity code transfer function is configured to transfer the set of data and one of respective integrity codes of a plurality of sets of data according to the second conversion seed, the plurality of sets of data include the set of data, and the first determination result indicates whether the integrity code transfer function is enabled.

7. The method of claim 1, wherein the first determination indicates that the integrity code transfer function is enabled; and the method further comprises:

and determining which of the respective integrity codes of the plurality of data sets is selected as the integrity code according to the second conversion seed to generate a second determination result, wherein the second determination result indicates which of the respective integrity codes of the plurality of data sets is selected as the integrity code for the data conversion.

8. A controller applicable for information protection for non-volatile memory, the controller comprising:

a core circuit for controlling the controller according to predetermined information loaded from the non-volatile memory to control an operation of an electronic device, wherein the electronic device includes the controller and the non-volatile memory;

address information rearrangement circuitry, coupled to the core circuitry, for performing address information rearrangement, wherein the address information rearrangement circuitry obtains a first die dependency seed and rearranges a plurality of sets of address information for an address according to the first die dependency seed to protect the address carried by at least one address signal between the controller and the non-volatile memory; and

a data conversion circuit coupled to the core circuit for performing data conversion, wherein the data conversion circuit obtains a second die-dependent seed and rearranges subsets of a set of data according to the second die-dependent seed to protect the set of data carried by at least one data signal between the controller and the non-volatile memory;

wherein the first die dependency seed and the second die dependency seed correspond to dies used to implement the non-volatile memory.

9. An electronic device comprising the controller of claim 8, wherein the electronic device comprises the non-volatile memory.

10. An apparatus to protect information for non-volatile memory, the apparatus comprising:

an address information rearrangement circuit for rearranging address information, wherein the address information rearrangement circuit obtains a first die dependency seed and rearranges a plurality of sets of address information of an address according to the first die dependency seed to protect the address carried by at least one address signal between a controller and the non-volatile memory; and

a data conversion circuit for performing data conversion, wherein the data conversion circuit obtains a second die-dependent seed and rearranges subsets of a set of data according to the second die-dependent seed to protect the set of data carried by at least one data signal between the controller and the non-volatile memory;

wherein the first die dependency seed and the second die dependency seed correspond to dies used to implement the non-volatile memory.

Technical Field

The present invention relates to memory control, and more particularly, to a method for information protection for a non-volatile memory (NVM) and related apparatus (apparatus), such as a controller, an electronic device including the controller, and the like.

Background

For side channel attack (side channel attack), hackers may perform reverse engineering on the read or write behavior of Flash memory (Flash memory) by controller Integrated Circuit (IC) through a logic analyzer (logic analyzer) or a current meter, for example, perform correlation analysis to determine that a program is performing a certain operation, and further analyze patterns (patterns) to attack a certain read or write address. A protection method regarding content encryption has been proposed in the related art in an attempt to solve the above-described problems, but there may be additional problems such as some side effects. For example, the computations for the above-described protection methods (encryption/decryption, etc., among others) are very time consuming, which can reduce system performance. In addition, although a vendor (vendor) may encrypt different versions of firmware, a hacker may directly replace an old flash memory in an old electronic product with a new flash memory in a new electronic product, so that the new version of firmware may be run on the old version of IC platform to analyze a read or write pattern, which may pose a great threat to system security. Therefore, there is a need for a novel method and related architecture to address the problems of the related art without, or with less likelihood of, side effects.

Disclosure of Invention

The present invention is directed to a method for protecting information with respect to a non-volatile memory and related devices, such as a controller, an electronic device including the controller, and the like, to solve the above problems.

At least one embodiment of the invention provides a method for information protection for a non-volatile memory, wherein the method is applied to a controller. The method comprises the following steps: obtaining a first die-dependent seed (die-dependent seed) and a second die-dependent seed, wherein the first die-dependent seed and the second die-dependent seed correspond to a die (die) used to implement the non-volatile memory; rearranging (rearranging) sets of address information of an address according to the first die dependency seed to protect the address carried by at least one address signal (carry) between the controller and the non-volatile memory; and rearranging a plurality of subsets of a set of data according to the second die-dependent seed to protect the set of data carried by at least one data signal between the controller and the non-volatile memory.

In addition to the above method, the present invention also provides a controller that can be applied (applicable to) information protection for a nonvolatile memory. The controller includes a core circuit, and an address information rearranging circuit and a data converting circuit respectively coupled to the core circuit. The core circuit is used for controlling the controller according to predetermined information loaded (loaded) from the nonvolatile memory to control the operation of an electronic device, wherein the electronic device comprises the controller and the nonvolatile memory. In addition, the address information rearrangement circuit can be used for rearranging address information, wherein the address information rearrangement circuit obtains a first die dependency seed and rearranges a plurality of groups of address information of an address according to the first die dependency seed so as to protect the address carried by at least one address signal between the controller and the nonvolatile memory. In addition, the data conversion circuit is configured to perform data conversion, wherein the data conversion circuit obtains a second die-dependent seed and rearranges subsets of a set of data according to the second die-dependent seed to protect the set of data carried by at least one data signal between the controller and the non-volatile memory. For example, the first die dependency seed and the second die dependency seed correspond to dies used to implement the non-volatile memory.

According to some embodiments, the present invention also provides an electronic device comprising the above controller, wherein the electronic device comprises the nonvolatile memory.

In addition to the above method, the present invention also provides an apparatus for information protection with respect to a nonvolatile memory. The apparatus includes an address information rearranging circuit and a data converting circuit. In addition, the address information rearrangement circuit can be used for rearranging address information, wherein the address information rearrangement circuit obtains a first die dependency seed and rearranges a plurality of groups of address information of an address according to the first die dependency seed so as to protect the address carried by at least one address signal between a controller and the nonvolatile memory. In addition, the data conversion circuit is configured to perform data conversion, wherein the data conversion circuit obtains a second die-dependent seed and rearranges subsets of a set of data according to the second die-dependent seed to protect the set of data carried by at least one data signal between the controller and the non-volatile memory. For example, the first die dependency seed and the second die dependency seed correspond to dies used to implement the non-volatile memory.

The method and the related device provided by the invention can ensure that the electronic device can operate properly under various conditions, wherein the related device comprises the following components: the controller, the electronic device, etc. In addition, the implementation according to the related embodiment of the invention does not add much extra cost. Accordingly, the problems of the related art can be properly solved. Compared with the related art, the invention can realize a robust information protection mechanism under the condition of no side effect or less possibility of bringing about the side effect.

Drawings

Fig. 1 is a schematic diagram of an electronic device according to an embodiment of the invention.

Fig. 2 is a flowchart of a method for information protection for a non-volatile memory according to an embodiment of the present invention.

FIG. 3 illustrates a write control scheme of the method of FIG. 2 in one embodiment of the invention.

FIG. 4 illustrates a read control scheme of the method of FIG. 2 in one embodiment of the invention.

FIG. 5 illustrates a hybrid (hybrid) conversion control scheme of the method of FIG. 2 in one embodiment of the invention.

Fig. 6 illustrates an address information rearrangement control scheme of the method shown in fig. 2 in one embodiment of the present invention.

FIG. 7 illustrates a data transition control scheme for the method of FIG. 2 in one embodiment of the invention.

FIG. 8 illustrates another example of a read and restore operation of the data conversion control scheme shown in FIG. 7.

FIG. 9 illustrates another example of a read and restore operation of the data conversion control scheme shown in FIG. 7.

FIG. 10 illustrates another example of a read and restore operation of the data conversion control scheme shown in FIG. 7.

Detailed Description

Fig. 1 is a diagram of an electronic device 100 according to an embodiment of the invention. The electronic device 100 may include a controller 100C and a non-volatile memory 100M coupled to each other, although the invention is not limited thereto. For example, the electronic device 100 may also include other elements such as a touch-sensitive (tactile) display module, one or more sound output modules, one or more wireless transmission modules, and the like, wherein at least a portion (e.g., a portion or all) of these elements may be coupled to each other and to the controller 100C by a bus. For ease of understanding, examples of electronic device 100 may include (but are not limited to): multifunctional mobile phones (multi functional mobile phones), wearable devices (wearable devices), tablet computers (tablets), and personal computers (personal computers), such as notebook computers.

The controller 100C may include a core circuit 101, a storage unit 110, an address information rearrangement circuit 120, a seed generation circuit 130, and a data conversion circuit 140, and particularly, the seed generation circuit 130 may include a seed generator (seed generator)130SG (e.g., a timer) and a plurality of seed translators 131,132,133,134, and 135, and the data conversion circuit 140 may include a data subset rearrangement circuit 142 and an integrity code (integrity code) selective arrangement circuit 144, wherein the address information rearrangement circuit 120 and the data conversion circuit 140 may be coupled between the core circuit 101 and an NVM interface circuit of the controller 100C, and the NVM interface circuit may pass a set of signals such as IO between the controller 100C and the NVM 100M₀、IO₁、IO₂、IO₃CLK, etc. for the controller 100C to read or write to the NVM 100M, but the invention is not limited thereto. In some embodiments, at least a portion (e.g., a portion or all) of the storage unit 110, the address information rearrangement circuit 120, the seed generation circuit 130, and the data conversion circuit 140 may be integrated into the core circuit 101. In addition, the controller 100C (e.g., the NVM interface circuitry thereof) may be Joint Electron Device engineering (Joint Electron Device) compliantng Council, JEDEC) specification or other specifications.

According to the present embodiment, the core circuit 101 can control the controller 100C according to the predetermined information loaded from the NVM 100M to control the operation of the electronic device 100. In addition, the controller 100C may be applied to protect information against the NVM 100M to combat various misbehaviors of hackers. The address information rearrangement circuit 120 and the data conversion circuit 140 may perform address information rearrangement and data conversion, respectively, and particularly perform information protection through related control of some seeds, such as a plurality of die-dependent seeds Seed1 and Seed2 stored in the storage unit 110 in advance and a plurality of conversion seeds (converted seeds) Seed3.1, Seed3.2, Seed3.3, Seed3.4 and Seed3.5 generated by the Seed generation circuit 130. For example, the storage unit 110 may provide the die-dependent Seed1 to the address information rearranging circuit 120, so that the address information rearranging circuit 120 performs the address information rearranging according to the die-dependent Seed1, and the storage unit 110 and the Seed generating circuit 130 may provide the die-dependent Seed2 and the conversion seeds Seed3.1, Seed3.2, Seed3.3, Seed3.4, and Seed3.5 to the data conversion circuit 140, respectively, so that the data conversion circuit 140 (e.g., the data subset rearranging circuit 142) performs the data conversion according to the die-dependent Seed2 and the conversion seeds Seed3.1, Seed3.2, Seed3.3, Seed3.4, and Seed 3.5. The data conversion may include data subset rearrangement, and in particular, may also include integrity code selective arrangement, wherein the data subset rearrangement circuit 142 may perform the data subset rearrangement according to the die-dependent Seed2, and the integrity code selective arrangement circuit 144 may perform the integrity code selective arrangement according to the conversion seeds Seed3.1, Seed3.2, Seed3.3, Seed3.4, and Seed3.5, but the invention is not limited thereto.

As shown in fig. 1, the Seed generator 130SG may generate an initial Seed3, and the Seed converters 131,132,133,134, and 135 may convert the initial Seed3 into conversion seeds Seed3.1, Seed3.2, Seed3.3, Seed3.4, and Seed3.5, respectively, for the data conversion. Note that the initial Seed3 may be updated over time, and the conversion seeds Seed3.1, Seed3.2, Seed3.3, Seed3.4, and Seed3.5 may be updated as the initial Seed3 changes. Thus, this data conversion based on these seeds may result in data signals (e.g., signal IO) between controller 100C and NVM 100M₀、IO₁、IO₂And IO₃And, in particular, the data being transmitted thereby).

Furthermore, die-dependent seeds Seed1 and Seed2 may correspond to the die used to implement NVM 100M. When the die is replaced with another die for implementing NVM 100M, die dependent seeds Seed1 and Seed2 may be updated to correspond to the other die. For example, the electronic devices {100} may be obtained by mass production. For a plurality of dies of the respective NVM {100M } used to implement the electronic devices {100} respectively, the die-dependent seeds Seed1 and Seed2 of each die are different from the die-dependent seeds Seed1 and Seed2 of any other of the dies, respectively. Based on the architecture shown in fig. 1, the present invention enables a robust information protection mechanism without side effects or with less possibility of side effects.

In the above embodiments, NVM 100M may be implemented by flash memories such as NAND type flash Memory and NOR type flash Memory, Electrically Erasable Programmable Read-Only Memory (EPRON), and the like. In addition, the storage unit 110 may be implemented by way of a one-time programming (one-time programming) memory element such as an electronic fuse (e-fuse), a register such as a secure register (secure register), and the like. For example, the storage unit 110 may include at least one electronic fuse and/or at least one security register. In addition, the address information rearranging circuit 120 and the data converting circuit 140 (especially, the data subset rearranging circuit 142 therein) may be implemented by a plurality of sets of switches, respectively. For example, address information rearrangement circuitry 120 may include a set of switches that may be used to swap two or more address lines of a set of address lines in accordance with die-dependent Seed1 for the address information rearrangement. As another example, the data conversion circuit 140 (and in particular, the data subset rearrangement circuit 142 therein) may include a set of switches operable to swap two or more data lines of a set of data lines for the data subset rearrangement in accordance with the die-dependent Seed 2.

FIG. 2 is a flow diagram of a method for information protection for an NVM, such as the NVM 100M shown in FIG. 1, in accordance with one embodiment of the present invention. The method may be applied to related apparatuses such as the controller 100C, the electronic device 100 including the controller 100C, and the like, and may be performed by the controller 100C. For example, the steps S10-S18 and S20-S28 may be performed in the write PHASE (0) (e.g., the production PHASE) and the read PHASE (1) (e.g., the end user PHASE) of the electronic device 100, respectively, but the invention is not limited thereto. To facilitate understanding, the first die dependency Seed and the second die dependency Seed described in the workflow shown in fig. 2 may be described as die dependency seeds Seed1 and Seed2, respectively.

In step S10, the controller 100C obtains die dependent seeds Seed1 and Seed 2. For example, the address information rearranging circuit 120 and the data conversion circuit 140 may obtain the die-dependent seeds Seed1 and Seed2 from the storage unit 110, respectively.

In step S12, the controller 100C (e.g., the address information rearrangement circuit 120) rearranges the sets of address information of the address according to the die-dependent Seed1 to protect the address carried by at least one address signal between the controller 100C and the NVM 100M, wherein the address in the write PHASE (0) may represent a write address. For example, controller 100C may swap two or more address lines of a set of address lines according to die-dependent Seed1 using the set of switches in address information rearrangement circuit 120 to rearrange (rearrange) the sets of address information for the address.

In step S14, the controller 100C (e.g., the data conversion circuit 140) rearranges a plurality of subsets of a set of data (e.g., a set of write data) according to the die-dependent Seed2 to protect the set of data carried by at least one data signal between the controller 100C and the NVM 100M. For example, the controller 100C may swap two or more data lines of a set of data lines according to die-dependent Seed2 using the set of switches in the data conversion circuit 140 (and in particular, the data subset rearrangement circuit 142 therein) to rearrange the subsets of the set of data.

In step S16, the controller 100C performs a write operation to the NVM 100M according to the address (e.g. the write address) described in step S12, and in particular, writes the set of data (e.g. the set of write data) rearranged in step S14 to the NVM 100M.

In step S18, the controller 100C determines whether writing in the write PHASE (0) is completed. If so, the controller 100C may leave the write PHASE (0), e.g., may enter the read PHASE (1) during a subsequent boot (e.g., the next boot), and in particular, enter step S20; if not, the controller 100C may stay in the write PHASE (0) to continue writing, and more particularly, proceed to step S10.

In step S20, the controller 100C obtains die dependent seeds Seed1 and Seed 2. For example, the address information rearranging circuit 120 and the data conversion circuit 140 may obtain the die-dependent seeds Seed1 and Seed2 from the storage unit 110, respectively.

In step S22, the controller 100C (e.g., the address information rearrangement circuit 120) rearranges the sets of address information of an address according to the die-dependent Seed1 to protect the address carried by at least one address signal between the controller 100C and the NVM 100M, wherein the address in the read PHASE (1) may represent a read address. For example, controller 100C may rearrange the sets of address information for this address by swapping two or more of the set of address lines according to die-dependent Seed1 using the set of switches in address information rearrangement circuit 120.

In step S24, the controller 100C performs a read operation on the NVM 100M according to the address (e.g., the read address) described in step S22, and in particular, reads a set of data (e.g., a set of read data) from the NVM 100M. For example, the set of data may be loaded into a Random Access Memory (RAM) in the controller 100C, but the invention is not limited thereto.

In step S26, the controller 100C (e.g., the data conversion circuit 140) rearranges the subsets of the set of data (e.g., the set of read data) in step S24 according to the die-dependent Seed2 to protect the set of data carried by at least one data signal between the controller 100C and the NVM 100M. For example, the controller 100C may swap two or more data lines of the set of data lines in accordance with the die-dependent Seed2 using the set of switches in the data conversion circuit 140 (and in particular, the data subset rearrangement circuit 142 therein) to rearrange the plurality of subsets of the set of data.

In step S28, the controller 100C determines whether reading in the reading PHASE (1) is completed. If so, the controller 100C may leave the read PHASE (1) to end the workflow shown in FIG. 2; if not, the controller 100C may stay in the reading PHASE (1) to continue reading, and more particularly, proceed to step S20. For example, when leaving the reading PHASE (1), the controller 100C has loaded the predetermined information control (e.g. program-related information, such as a plurality of instructions and data thereof) into the RAM to control the operation of the electronic device 100, but the invention is not limited thereto.

For a better understanding, the method may be illustrated with the workflow shown in fig. 2, but the invention is not limited thereto. According to some embodiments, one or more steps may be added, deleted or modified from the workflow illustrated in FIG. 2.

According to some embodiments, the NVM 100M shown in fig. 1 may include a corresponding NVM-side information protection circuit structure, which may be identical to the controller-side information protection circuit structure composed of the storage unit 110, the address information rearranging circuit 120, the seed generating circuit 130 and the data converting circuit 140 in the controller 100C, for operating according to the method, but the invention is not limited thereto. For example, assume that a series of available addresses for 100C to control NVM 100M are all effective addresses and each represent a series of storage locations, such as a series of pages (pages), having the same size. Seed1 may be a Seed that varies according to a predetermined sequence that is the same for the same die, whether in the write PHASE (0) or the read PHASE (1). In this case, regardless of how the set of address lines are swapped, the set of data in write PHASE (0), such as the set of write data, may be written somewhere in NVM 100M and read from the same address line swap. Therefore, the NVM 100M does not need to perform reverse rearrangement of the address information rearrangement, nor does it need to provide a corresponding reverse address information rearrangement circuit. In addition, Seed2 may be a Seed that varies according to another predetermined sequence that is the same for the same die, whether in the write PHASE (0) or the read PHASE (1). In this case, regardless of how the set of data lines is swapped, the set of data in write PHASE (0), such as the set of write data, can be written somewhere in NVM 100M and also read out to be restored (recovery) from the same data line swap. Therefore, the NVM 100M does not need to perform reverse rearrangement of the data subset rearrangement, nor does it need to provide a corresponding reverse data subset rearrangement circuit.

According to some embodiments, controller 110C (e.g., core circuitry 101) may parse (parse) the header (header) in the information from NVM 100M to obtain die-dependent seeds Seed1 and Seed2 from the header and provide die-dependent seeds Seed1 and Seed2 to address information rearranging circuitry 120 and data conversion circuitry 140. For example, the corresponding NVM-side information protection circuit architecture may retrieve the die-dependent seeds Seed1 and Seed2 from corresponding storage units therein (e.g., electrical fuses or security registers), embed or insert the die-dependent seeds Seed1 and Seed2 in the header, and combine the header with encrypted data, such as image (image), for transmission to the controller 110C.

FIG. 3 illustrates a write control scheme of the method of FIG. 2 in one embodiment of the invention. For the address information rearrangement circuit 120, the address information rearrangement may include address information shift (shift), for example, shifting the binary version 0001_0010_0011_0100 of 0x1234 to become the binary version 0010_0011_0100_0001 of 0x 2341. In particular, the address information rearrangement may further comprise a hash (scramblele), such as binary version 0010_0011_0100_0001 of the hash 0x2341 to become binary version 0100_1100_0001_1000 of 0x4C 18. For the data subset rearrangement circuitry 142, the data subset rearrangement may include a data subset shift, e.g., a shift of the binary version of 0xABCD 1010_1011_1100_1101 to become the binary version of 0xBCDA 1011_1100_1101_ 1010. In particular, the data subset rearrangement may further comprise a hash, for example, a binary version 1011_1100_1101_1010 of 0xBCDA to become a binary version 0111_1100_1110_0101 of 0x7CE 5. After transmitting the command, the controller 110C may transmit the address (e.g., the write address such as the address after the rearrangement processing by the address information), and then write data (e.g., the set of write data). For example, the address information rearrangement circuit 120 and the data conversion circuit 140 (particularly, the data subset rearrangement circuit 142 therein) may respectively apply a modulo operator (modulo operator) mod to the die-dependent seeds Seed1 and Seed2 by using their respective modulo calculation circuits, and particularly, perform a modulo operation on the die-dependent seeds Seed1 and Seed2 to generate a modulo operation result, so as to perform the address information rearrangement and the data subset rearrangement according to the modulo operation results. For brevity, similar contents in this embodiment are not repeated herein.

FIG. 4 illustrates a read control scheme of the method of FIG. 2 in one embodiment of the invention. In contrast to the write control scheme shown in FIG. 3, after transmitting a command, the controller 110C may transmit the address (e.g., the read address, such as the address after the rearrangement process by the address information) and then read data (e.g., the set of read data). For brevity, similar contents in this embodiment are not repeated herein.

FIG. 5 illustrates a hybrid switching control scheme of the method of FIG. 2 in one embodiment of the invention. At least a portion (e.g., a portion or all) of the controller-side information protection circuit architecture shown in fig. 1 may be integrated into the hybrid conversion module 500. An address and its integrity code, such as a Cyclic Redundancy Check (CRC) code, may be carried on signals ADDR and CRC. For example, the hybrid conversion module 500 may pre-calculate integrity codes of a series of data, such as its CRC codes { C0, …, C3}, { C4, …, C7}, …, { C120, …, C127}, etc., and store the integrity codes, such as the CRC codes, in a CRC table. In addition, the hybrid conversion module 500 may utilize the rearrangement circuit and the splicing circuit therein to rearrange according to the corresponding seeds, such as Seed (1), Seed (2) and Seed (3), and may utilize a Multiplexer (MUX) to select one of the rearrangement results and one of the splicing results according to the corresponding seeds, such as Seed (4), for output. For brevity, similar contents in this embodiment are not repeated herein.

Fig. 6 illustrates an address information rearrangement control scheme of the method shown in fig. 2 in one embodiment of the present invention. Based on the architecture shown in fig. 1, the electronic device 100 may include multiple physical lines between the controller 100C and the NVM 100M. These entity lines contain corresponding signals IO₀、IO₁、IO₂And IO₃And the set of physical lines may be used at different times (or stages) as the set of address lines or the set of data lines. In particular, controller 100C can perform command transmission, Address transmission, and Data transmission or reception during command Phase CMD _ Phase, Address Phase, and Data Phase Data _ Phase, respectively. For example, when the controller 100C rearranges the Address information in the Address Phase Address _ Phase, the set of physical lines represents the set of Address lines and transmits the corresponding signal IO thereon₀、IO₁、IO₂And IO₃Representing address signals. For another example, when the controller 100C performs the Data subset rearrangement in the Data Phase Data _ Phase, the set of physical lines represents the set of Data lines and the corresponding signal IO transmitted thereon₀、IO₁、IO₂And IO₃Representing a data signal.

According to the present embodiment, the physical positions of the set of physical lines are physical line positions P0, P1, P2 and P3, respectively, and can be switched by using the above-mentioned switches to become any one of various rearrangement results. For example, at a point in time, the solid line positions P0, P1, P2 and P3 may be exchanged for solid line positions P1, P3, P2 and P0; at another point in time, the solid line positions P0, P1, P2 and P3 may be exchanged for solid line positions P2, P3, P1 and P0; also, at other points in time, the solid line positions P0, P1, P2, and P3 may be swapped for other rearrangement results. For brevity, similar contents in this embodiment are not repeated herein.

According to some embodiments, the data conversion circuit 140 (e.g., the integrity code selective arrangement circuit 144) may determine whether the integrity code transmission function is enabled according to the conversion seed Seed3.1 to generate a first determination result, wherein the first determination result indicates whether the integrity code transmission function is enabled. The integrity code transmission function is configured to transmit the set of data (e.g., the set of data in step S24, such as the set of read data) together with an integrity code of respective integrity codes of a plurality of sets of data, wherein the respective integrity codes of the plurality of sets of data are respectively configured to perform error detection on the plurality of sets of data, according to the transformation seed 3.2. Examples of such integrity codes may include (but are not limited to): CRC codes, Hash (Hash) values, parity-check (parity-check) codes, etc. When the first determination result indicates that the integrity code transmission function is enabled, the data conversion circuit 140 (e.g., the integrity code selective arrangement circuit 144) may determine which of the respective integrity codes of the plurality of data sets is selected as the integrity code according to the conversion seed Seed3.2 to generate a second determination result, wherein the second determination result indicates which of the respective integrity codes of the plurality of data sets is selected as the integrity code for performing the data conversion. In addition, for transmitting the set of data together with the integrity code, the data conversion circuit 140 (e.g., the integrity code selective arrangement circuit 144) may determine the relative position of the integrity code with respect to the plurality of subsets of the set of data according to the conversion seed3.3 (e.g., the integrity code such as the CRC code may be located before the set of data, after the set of data, between some two subsets of the plurality of subsets of the set of data) for performing the data conversion. In addition, the data conversion circuit 140 (e.g., the integrity code selective arrangement circuit 144) can determine whether to use the integrity code for error detection of a corresponding one of the plurality of data sets according to the conversion seed Seed 3.4. The data conversion circuit 140 (e.g., the integrity code selective arrangement circuit 144) may generate a self-generated integrity code such as a self-generated CRC code based on the corresponding set of data, and compare the integrity code such as the CRC code with the self-generated integrity code such as the self-generated CRC code, wherein two being the same indicates no error and two being different indicates an error. The data conversion circuit 140 (e.g., the integrity code selective arrangement circuit 144) may further determine respective rearrangement positions of the respective integrity codes of the plurality of sets of data (e.g., positions where the integrity codes such as CRC codes are placed, such as positions relative to other integrity codes in the respective integrity codes of the plurality of sets of data, and/or positions relative to the plurality of sets of data) according to the conversion seed Seed3.5 for performing error detection of the plurality of sets of data.

FIG. 7 illustrates a data transition control scheme for the method of FIG. 2 in one embodiment of the invention. In addition to performing the address information rearrangement and the data subset rearrangement (e.g., exchanging physical lines according to die-dependent Seed1 and Seed2, respectively), the controller 100C may perform integrity code selective arrangement using the data conversion circuit 140 (e.g., integrity code selective arrangement circuit 144). Since the read PHASE (1) is taken as an example in the embodiment, the NVM 100M (e.g. the NVM-side information protection circuit architecture therein) may perform its own integrity code selective arrangement to generate a selective arrangement result for output to the controller 100C, and the controller 100C may perform its own integrity code selective arrangement to restore the multiple sets of data when reading the NVM 100M.

As shown in fig. 7, the sets of data such as data 1,2,3,4,5,6,7 and 8 and their respective integrity codes such as CRC codes c0, c1, c2, c3, c4, c5, c6 and c7, along with the dummy data (dummy data) shown in hatching, a set of addresses { Addr } such as 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9 and 0xA that may be stored in NVM 100M, wherein the dummy data may be stored at address 0x6 and the respective subsets {1.1,1.2,1.3,1.4}, { 2.1.1, 2.2,2.3, 4,5,6,7 and 8 of data 1,2,3,4, 3.4, 3.3,3.4, 3.7 and 3.4, 3.7, 3.4, 3.8, 3.4, 3.7, 3.4, 3.8, 3.7, 3.8, 3.4, 3.7, 3.8, 3.7, 3.8, 3, 3.7, 3.8, 3.7, 4, 3.8, 3.7, 3.8, 4, 3.8, 3,4, 3, 3.8, 3,4, 3.8, 3,4, 3.8, 3, 3.8, 3, 3.8, 4,3, 3.8, 4,3, 3.8, 3, 3.8, 3, 3.8, 3,4, 3, 3.8, 3,4, 3, 3.8, 3,4, 3,4, 3, 3.8, 3,4, 3,4, 3, c1, c2, c3 and { c4, c5, c6, c7} may be rearranged and stored respectively at other addresses in the set of addresses { Addr }.

According to the present embodiment, the controller 100C can read the NVM 100M at a certain time point to receive the signal IO from the NVM 100M₀、IO₁、IO₂And IO₃The loaded rearranged subsets 1.1,1.2,1.3,1.4,2.1,2.2,2.3,2.4,3.1,3.2,3.3,3.4, and 4.1,4.2,4.3,4.4, along with CRC codes c5, c6, and c2, which occur randomly before or after, and from which signals IO may be derived₀、IO₁、IO₂And IO₃The information carried restores data 1,2,3 and 4, for example by selective permutation of its own integrity code with the subset of data. In particular, data conversion circuit 140 (e.g., integrity code selective arrangement circuit 144) may perform error detection on data 6 (previously or subsequently read) in accordance with CRC code c 6. For brevity, similar contents in this embodiment are not repeated herein.

FIG. 8 illustrates another example of a read and restore operation of the data conversion control scheme shown in FIG. 7. The controller 100C can read the NVM 100M at another point in time to receive the signal IO from the NVM 100M₀、IO₁、IO₂And IO₃The loaded rearranged subsets 5.1,5.2,5.3,5.4,6.1,6.2,6.3,6.4,7.1,7.2,7.3,7.4, and 8.1,8.2,8.3,8.4, along with randomly occurring subsequent CRC codes c1, c7, and c6, from which the signals IO₀、IO₁、IO₂And IO₃The information carried restores data 5,6,7 and 8, for example by selective permutation of its own integrity code with the subset of data. In particular, data conversion circuit 140 (e.g., integrity code selective arrangement circuit 144) may perform error detection on data 7 according to CRC code c 7. For brevity, similar contents in this embodiment are not repeated herein.

FIG. 9 shows the data shown in FIG. 7Another example of a read and restore operation of a conversion control scheme. The controller 100C can read the NVM 100M at another point in time to receive the signal IO from the NVM 100M₀、IO₁、IO₂And IO₃The loaded rearranged subset {1.1,1.2,1.3,1.4}, {2.1,2.2,2.3,2.4}, {3.1,3.2,3.3,3.4}, {4.1,4.2,4.3,4.4}, together with CRC codes c7 and c1 randomly occurring before or after, and from which signals IO can be derived₀、IO₁、IO₂And IO₃The information carried restores data 1,2,3 and 4, for example by selective permutation of its own integrity code with the subset of data. In particular, the data conversion circuit 140 (e.g., the integrity code selective arrangement circuit 144) may perform error detection on the data 1 according to the CRC code c 1. For brevity, similar contents in this embodiment are not repeated herein.

FIG. 10 illustrates another example of a read and restore operation of the data conversion control scheme shown in FIG. 7. The controller 100C can read the NVM 100M at another point in time to receive the signal IO from the NVM 100M₀、IO₁、IO₂And IO₃The loaded rearranged subsets {1.1,1.2,1.3,1.4}, {2.1,2.2,2.3,2.4}, {3.1,3.2,3.3,3.4}, {4.1,4.2,4.3,4.4}, together with CRC codes c6 and c2 randomly occurring in (e.g., between certain subsets), and from which IO may be derived₀、IO₁、IO₂And IO₃The information carried restores data 1,2,3 and 4, for example by selective permutation of its own integrity code with the subset of data. For brevity, similar contents in this embodiment are not repeated herein.

Based on the above embodiments, the present invention provides a device for information protection for NVM 100M, and examples of the above devices may include (but are not limited to): the electronic device 100, the controller 100C and the controller-side information protection circuit structure therein, the NVM 100M and the NVM-side information protection circuit structure therein, and the like.

The above-mentioned embodiments are merely preferred embodiments of the present invention, and all equivalent changes and modifications made in the claims of the present invention should be covered by the present invention.

Description of the reference numerals

100 electronic device

100C controller

100M:NVM

101 core circuit

110 storage unit

120 address information rearrangement circuit

130 seed generation circuit

130SG seed generator

131,132,133,134,135 seed converter

140 data conversion circuit

142 data subset rearrangement circuit

144 selective arrangement circuit for integrity code

IO₀,IO₁,IO₂,IO₃CLK, ADDR, CRC.ADDR, DATA, CRC.DATA signals

Seed1, Seed2, Seed3, Seed3.1, Seed3.2, Seed3.3, Seed3.4, Seed3.5, Seed (1), Seed (2), Seed (3), Seed (4): Seed1, Seed2, Seed3, Seed3.1, Seed3.2, Seed3.3, Seed (2), Seed (3), Seed (4)

S10, S12, S14, S16, S18, S20, S22, S24, S26, S28

PHASE (0) write PHASE

PHASE (1) read PHASE

mod modulo operator

500 mixing conversion module

C0-C3, C4-C7, C120-C127, C0, C1, C2, C3, C4, C5, C6, C7 CRC code

P0, P1, P2, P3 solid line positions

CMD _ Phase Command Phase

Address Phase Address Phase

Data Phase

Addr address

1,2,3,4,5,6,7,8: data

1.1,1.2,1.3,1.4,2.1,2.2,2.3,2.4,3.1,3.2,3.3,3.4,4.1,4.2,4.3,4.4,5.1,5.2,5.3,5.4,6.1,6.2,6.3,6.4,7.1,7.2,7.3,7.4,8.1,8.2,8.3,8.4: subset