阅读说明：本技术 内容可定址存储器装置 (Content addressable memory device ) 是由 姜易豪 于 2019-10-28 设计创作，主要内容包括：一种存储器装置包含：一控制器电路,用以输出一第一全域预充电控制信号、一第二全域预充电控制信号与一第一本地预充电控制信号；一第一级电路,用以根据该第一全域预充电控制信号对一第一全域匹配线预充电,并比较一查询数据与多个第一数据以决定是否调整该第一全域匹配线的第一位准；以及一第二级电路,用以根据该第一位准与该第二全域预充电控制信号选择性地对一第二全域匹配线预充电,并根据该第二全域匹配线的第二位准与该第一本地预充电控制信号决定是否比较该查询数据与多个第二数据,以调整该第二位准。(A memory device comprising: a controller circuit for outputting a first global precharge control signal, a second global precharge control signal and a first local precharge control signal; a first stage circuit for precharging a first global match line according to the first global precharge control signal and comparing a query data with a plurality of first data to determine whether to adjust a first level of the first global match line; and a second stage circuit for selectively precharging a second global match line according to the first level and the second global precharge control signal, and determining whether to compare the inquiry data with a plurality of second data according to a second level of the second global match line and the first local precharge control signal to adjust the second level.)

1. A memory device, comprising:

a controller circuit for outputting a first global precharge control signal, a second global precharge control signal and a first local precharge control signal;

a first stage circuit for precharging a first global match line according to the first global precharge control signal and comparing a query data with a plurality of first data to determine whether to adjust a first level of the first global match line; and

a second stage circuit for selectively precharging a second global match line according to the first level and the second global precharge control signal, and determining whether to compare the inquiry data with a plurality of second data according to a second level of the second global match line and the first local precharge control signal to adjust the second level.

2. The memory device of claim 1, wherein the second stage circuit comprises:

a global precharge circuit for determining whether to precharge the second global match line according to the first level and the second global precharge control signal; and

a local memory circuit selectively enabled according to the second level to compare the query data with the plurality of second data according to the first local precharge control signal to adjust the second level.

3. The memory device of claim 2, wherein the global precharge circuit comprises:

a logic gate for outputting a first control signal according to the second global precharge control signal when the first stage circuit determines not to adjust the first level according to the polling data;

an inverter for outputting a second control signal according to the first level;

a first transistor for turning on according to the first control signal to precharge the second global match line; and

a second transistor for turning on according to the second control signal to pull down the second level.

4. The memory device of claim 2, wherein the local memory circuit comprises:

a local precharge circuit for determining whether to precharge a local matchline according to the second level and the first local precharge control signal;

a plurality of CAM cells configured to store the second data and compare the query data with the second data to determine whether to adjust a third level of the local match line; and

a protection circuit for adjusting the second level according to the third level and a second local precharge control signal and providing a leakage protection for the second global match line, wherein the controller circuit is further configured to output the second local precharge control signal.

5. The memory device of claim 4, wherein the local precharge circuit comprises:

a logic gate, wherein the logic gate is configured to generate a control signal in response to the first local precharge control signal when the second stage circuit precharges the second global match line; and

a transistor, for turning on according to the control signal, to precharge the local matchline.

6. The memory device of claim 4, wherein the protection circuit comprises:

a first transistor;

a second transistor, wherein the first transistor and the second transistor operate as an inverter and are configured to generate a control signal according to the third level;

a third transistor coupled between the second transistor and ground and selectively turned on according to the second level;

a fourth transistor selectively turned on according to the control signal; and

a fifth transistor coupled between the fourth transistor and ground for selectively turning on according to the second local precharge control signal, wherein the fourth transistor is coupled between the second global matchline and the fifth transistor.

7. The memory device of claim 4, wherein the local precharge circuit does not precharge the local match line when the query data does not match the first plurality of data.

8. The memory device of claim 1, wherein the first stage circuit comprises:

a global precharge circuit for precharging the first global match line according to the first global precharge control signal; and

a local memory circuit for storing the first data and comparing the query data with the first data to determine whether to adjust the first level.

9. The memory device of claim 1, wherein the second stage circuitry selectively precharges the second global match line when the first stage circuitry compares the query data with the plurality of first data.

Technical Field

The present disclosure relates to memory devices, and more particularly, to content addressable memory devices that utilize global match lines as well as local match lines to perform selective precharging.

Background

The content addressable memory provides data comparison and address encoding functions to provide high speed data search capabilities. However, in the conventional architecture, in order to provide high-speed data searching capability, the content addressable memory needs to directly pre-charge a plurality of memory rows in advance. As a result, the content addressable memory may generate unnecessary power consumption, and may cause adverse effects such as electromigration and voltage drop, which may result in reduced performance of the memory.

Disclosure of Invention

In some embodiments, a memory device comprises: a controller circuit for outputting a first global precharge control signal, a second global precharge control signal and a first local precharge control signal; a first stage circuit for precharging a first global match line according to the first global precharge control signal and comparing a query data with a plurality of first data to determine whether to adjust a first level of the first global match line; and a second stage circuit for selectively precharging a second global match line according to the first level and the second global precharge control signal, and determining whether to compare the inquiry data with a plurality of second data according to a second level of the second global match line and the first local precharge control signal to adjust the second level.

The features, implementations, and technical effects of the present disclosure will be described in detail below with reference to the accompanying drawings.

Drawings

FIG. 1 is a schematic diagram illustrating a memory device according to some embodiments of the present disclosure;

FIG. 2 is a waveform diagram illustrating operation of the memory device of FIG. 1 according to some embodiments of the present disclosure;

FIG. 3 is a circuit schematic diagram illustrating the first stage circuit of FIG. 1, according to some embodiments of the present disclosure;

FIG. 4A is a circuit schematic illustrating the second stage circuit of FIG. 1 according to some embodiments of the present disclosure; and

fig. 4B is a detailed circuit schematic diagram illustrating the second stage circuit of fig. 4A, according to some embodiments of the present disclosure.

Description of the symbols

100 memory device

110. 120 universe precharge circuit

111. 121 signal holding circuit

113 local memory circuit

123 local memory circuit

130 controller circuit

CLK clock signal

D_CQuerying data

G_PR1、G_PR2Global precharge control signal

L_G1、L_G2Global matchline

L_PR、L_PRBLocal precharge control signal

R_OEnabling signal

S_AOAddress signal

T₀、T₁、T_LP1Period of time

P_EV0、P_EV1Operation stage

P_PR0、P_PR1Precharge phase

113-1 local precharge circuit

113-2 Content Addressable Memory (CAM) cell

113-3 switching circuit

D₁Data of

I1 inverter

L_L1Local matchline

N1 transistor

S₁Control signal

SLP1, SLN1 bit line

123-1 local precharge circuit

123-2 CAM cell

123-3 protection circuit

D₂Data of

G1, G2 NAND gate (N-AND gate, NOT AND gate)

I2 inverter

L_L2Local matchline

Transistors from N2 to N6 and from P2 to P4

S₂～S₅Control signal

SLP2, SLN2 bit line

VDD Voltage

Detailed Description

All words used herein have their ordinary meaning. The definitions of the above-mentioned words in commonly used dictionaries, any use of the words discussed herein in this disclosure is intended to be exemplary only and should not be construed as limiting the scope and meaning of the disclosure. Likewise, the present disclosure is not limited to the various embodiments shown in this specification.

As used herein, the term "couple" or "connect" refers to two or more elements being in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, or to two or more elements operating or acting together.

As used herein, the term "circuit system" may be a single system formed by at least one circuit (circuit), and the term "circuit" may be a device connected by at least one transistor and/or at least one active and passive component in a certain manner to process signals. As used herein, the term "and/or" includes any combination of one or more of the associated listed items.

The terms first, second, third and the like may be used herein to describe and distinguish various elements. Thus, a first element can be termed a second element herein without departing from the spirit of the present disclosure.

For ease of understanding, like elements in the various figures will be designated with the same reference numerals.

FIG. 1 is a schematic diagram illustrating a memory device 100 according to some embodiments of the present disclosure. In some embodiments, the memory device 100 may be a content-addressable memory (CAM) device.

The memory device 100 includes a plurality of memory rows and a controller circuit 130, wherein each memory includes two levels of circuitry. The two-stage circuit is configured as a pipeline circuit. The first stage circuit is used for comparing the query data D_CAnd a plurality of data (hereinafter referred to as data D) stored in the first stage circuit₁As shown in fig. 3) to determine whether to adjust a global (global) match (match) line L_G1Is detected (hereinafter referred to simply as "first level"). The second stage is used for generating a global precharge control signal G according to the first level_PR2Selectively aligning global match lines L_G2Is precharged and is based onGlobal matchline L_G2Level of (d) and a local precharge control signal L (hereinafter referred to simply as "second level")_PR-Deciding whether to compare query data D_CAnd a plurality of data (hereinafter referred to as data D) stored in the second stage circuit₂As shown in fig. 4A) later, to adjust the second level. With the above arrangement, the power loss generated during the operation of the memory device 100 can be reduced, and the voltage drop (IR-drop) and electro-migration (EM) of the memory device 100 can be significantly improved.

Taking the memory row of the first row as an example, the first stage circuit includes a global precharge circuit 110, a local memory circuit 113, and a signal hold circuit 111. A global precharge circuit 110 is coupled to the global match line L_G1And is used for being based on the global precharge control signal G_PR1For global match line L_G1And (4) pre-charging. Thus, the first level is raised to a high level (e.g., a level corresponding to a logic value of 1). The local memory circuit 113 is used for storing data D₁And comparing the query data D_CAnd data D₁To determine whether to adjust the first level.

If the data D is queried_CMatched (i.e. identical) to data D₁Local memory circuit 113 will not adjust the first level. Under this condition, the first level is maintained at a high level to reflect the query data D_CIs stored in local memory circuit 113. Or, if the data D is queried_CNot matched (i.e. different) to data D₁The local memory circuit 113 will match the global match line L_G1A discharge is performed to pull down the first level to a low level (e.g., a level corresponding to a logic value of 0). Under this condition, the first level may reflect the query data D_CNot stored within local memory circuit 113.

The signal holding circuit 111 is used for maintaining the first level and generating an enable signal R according to the first level and the clock signal CLK_O. In some embodiments, the signal holding circuit 111 may be implemented by a register, flip-flop (flip-flop), or latch. For example, the signal holding circuit 111 can be, but is not limited to, a D-type flip-flop, whichCan output an enable signal R according to the clock signal CLK_O。

The second stage circuit includes a global precharge circuit 120, a local memory circuit 123 and a signal hold circuit 121.

A global precharge circuit 120 is coupled to the global match line L_G2And is used for generating an enable signal R according to the received signal_OAnd global precharge control signal G_PR2Determine whether to match the global match line L_G2And (4) pre-charging. In some embodiments, if the data D is queried_CIs matched with data D₁Global precharge circuit 120 for global match line L_G2And (4) pre-charging. If the data D is queried_CNot matched to data D₁The global precharge circuit 120 does not match the global match line L_G2And (4) pre-charging.

In detail, if the data D is queried_CIs matched with data D₁The first level is a high level. In response to the first level, the signal hold circuit 111_-Outputting an enable signal R with a logic value 1_O. In response to the global precharge control signal G having a logic value of 1_PR2And an enable signal R_OGlobal precharge circuit 120 for global match line L_G2Pre-charging to raise the second level to a high level.

Or, if the data D is queried_CMismatch to data D₁The first level is a low level. In response to the first level, the signal hold circuit 111_-Outputting an enable signal R having a logic value of 0_O. Regardless of the global precharge control signal G_PR2Is determined, the global precharge circuit 120 responds to the enable signal R with a logic value of 0_OWithout aligning the global match line L_G2Pre-charge and pull the second level low.

The local memory circuit 123 is coupled to a global match line L_G2And is selectively enabled according to a second level to be responsive to the local precharge control signal L_PRAdjusting the second level. In some embodiments, when the local memory circuit 123 is enabled, the local memory circuit 123 is enabled according to the local precharge control signal L_PR-Performing a precharge operation, anAccording to the query data D_CDetermining whether to adjust the second level. In some embodiments, when local memory circuit 123 is not enabled, local memory circuit 123 does not perform the precharge operation and is responsive to local precharge control signal L_PR-BThe second level is maintained. As shown in fig. 2, the local precharge control signal L_PR-BInverted to the local precharge control signal L_PR-. The detailed description will be described later with reference to fig. 2 and 4A to 4B.

The signal hold circuit 121 is coupled to the global match line L_G2-. The signal hold circuit 121 functions and is similar to the signal hold circuit 111 in the embodiments. The signal holding circuit 121 is used for holding the second level and generating the address signal S according to the second level_AO. Address signal S_AOCan be used to indicate whether the data stored in the first row of memory lines matches the query data D_C. In some embodiments, the memory device 100 may further include a sense amplifier (not shown) for amplifying the address signal S outputted from the signal holding circuit 121_AO. In some embodiments, the memory device 100 may further include a codec circuit (not shown) that may be responsive to the address signal S for each column_AOGenerating an address indicating to store the query data D_C-The memory location of (2).

The controller circuit 130 is used for outputting a clock signal CLK and a global precharge control signal G_PR1Global precharge control signal G_PR2Local precharge control signal L_PR-And local precharge control signal L_PR-BTo control the precharge operation of each row of memory. In some embodiments, the controller circuit 130 may be implemented by a logic circuit, a microcontroller, a digital signal processing circuit, and the like, but the disclosure is not limited thereto.

In some embodiments, in terms of layout design, the signal paths of the controller circuit 130 outputting the control signals may be implemented by using vertical traces. In other words, the memory device 100 can perform the precharge operation without using the control signal transmitted in the horizontal direction. As will be described later, various control signals may be passed through a plurality of match lines to complete a precharge operation or an operation. Therefore, the layout of the memory array can be more compact, and the circuit area is smaller.

The number of circuits of fig. 1 is for example only, and the disclosure is not so limited. In some embodiments, the memory device 100 can operate without using the signal maintenance circuit 111, the signal maintenance circuit 121, and/or the sense amplifier. In some embodiments, the memory device 100 may include more memory rows (not shown), where each memory row has the same circuit structure. In some embodiments, each memory row may include more stages of circuitry (not shown), where the remaining stages of circuitry have the same circuit structure except for the first stage of circuitry. In some embodiments, memory device 100 further includes read/write control circuitry (not shown) to read from and write to memory cells in a memory row (e.g., CAM cell 113-2 and/or CAM cell 123-2 as described below).

Fig. 2 is a waveform diagram illustrating operation of the memory device 100 of fig. 1 according to some embodiments of the present disclosure. Referring also to fig. 1, the operation of the memory device 100 of fig. 1 will be described with reference to fig. 2.

For the first stage circuit, the first stage circuit responds to the global control signal G during the period T0_PR1Enter the operation phase P_EV0. In the operation phase P_EV0Local memory circuit 113 according to inquiry data D_CIt is determined whether to adjust the first level. The signal holding circuit 111 outputs an enable signal R according to the clock signal CLK and the first level_O. In this example, the local memory circuit 113 validates the query data D_CMismatch to data D₁So that the enable signal R_OIs a logical value 0. In the operation phase P_EV0Thereafter, the first stage circuit enters a precharge phase P_PR0。

In this example, the local memory circuit 113 validates the query data D in the previous operation stage (not shown)_CIs matched with data D₁So that the enable signal R_OIs a logical value of 1. With respect to the second stage circuit, during the period T0, the global precharge circuit 120 responds to global precharge with logic value 1Charging control signal G_PR2And an enable signal R_oFor global match line L_G2Pre-charging to raise the second level to a high level. Then, in response to the local precharge control signal L having a logic value of 1_PRAnd at this second level, the local memory circuit 123 is enabled for a precharge operation to pull up the local match line L of FIG. 4A_L2Is detected (hereinafter referred to simply as "third level"). In this example, the local memory circuit 123 validates the query data D_CNot matching the data stored in the local memory circuit 123, the third level and the second level are pulled down to a low level. As shown in FIG. 2, during the period T when the second stage circuit is performing the precharge operation_LP1The first stage circuit is in the operation stage P_EV0Middle comparison query data D_CAnd data D₁. Comparing the query data D in the second stage circuit_CAnd data D₂During the operation of (2), the first stage circuit is in the precharge phase P_PR0In which a precharge operation is performed.

In response to the global control signal G during the period T1_PR1The first stage circuit enters the operation stage P_EV1. Local memory circuit 113 based on query data D_CIt is determined whether to adjust the first level. In the operation phase P_EV1Thereafter, the first stage circuit enters a precharge phase P_PR1。

For the second stage circuit, during the period T1, the global precharge circuit 120 responds to the enable signal R with logic value 0_o(i.e., the same as the first level in the previous period T0) not to the global match line L_G2Precharged so that the second level remains low corresponding to a logic 0. Then, responding to the enabling signal R with logic value 0_oThe local memory circuit 123 is not enabled and does not perform the precharge operation, so the third level is not changed.

The period T0 and the period T1 each correspond to a period of the clock signal CLK. As can be understood from fig. 2, the first stage circuit performs a precharge operation (i.e., the global match line L) in each cycle of the clock signal CLK_G1Is precharged) period (i.e. precharge phase P)_PR0) Different from the second stage circuitPerforms a precharge operation (i.e., a global match line L)_G2Is precharged) of the first and second phases_LP1. When the first stage circuit performs a precharge operation (i.e., the global match line L)_G1Precharged), the second stage selectively asserts the query data D_CWhether or not to match data D₂. Therefore, the current generated by the memory device 100 at the same time can be significantly reduced, thereby reducing the voltage drop and the electromigration effect. In addition, since the second stage circuit selectively performs the precharge according to the first level generated by the first stage circuit during the previous period, the dynamic power consumption of the second stage circuit can be further reduced.

Fig. 3 is a circuit schematic diagram illustrating the first stage circuit of fig. 1 according to some embodiments of the present disclosure. In some embodiments, the local memory circuit 113 includes a local precharge circuit 113-1, a plurality of CAM cells 113-2, and a switching circuit 113-3.

The local precharge circuit 113-1 is used for matching the local match line L_L1Precharging is performed to raise the local match line L_L1-To a high level. A plurality of CAM cells 113-2 are coupled to a local match line L_L1. In some embodiments, CAM cell 113-2 includes a storage element (not shown) for storing data D₁(ii) a And a comparison element (not shown) for comparing the data D₁And query data D_C。

Each of the plurality of CAM cells 113-2 receives the inquiry data D via the bit line SLP1 and the bit line SLN1_CAnd confirming the query data D_CWhether or not to match data D₁To selectively adjust the local match line L_L1The level of (c). For example, if each CAM cell 113-2 identifies the lookup data D_CIs matched with data D₁Local matchline L_L1-Is kept at a high level. Alternatively, if one of CAM cells 113-2 identifies query data D_CMismatch to data D₁The CAM cell 113-2 pulls down the local match line L_L1-To a low level. In some embodiments, the operation of CAM cell 113-2 may refer to a conventional NOR type CAM cell, but the disclosure is not limited thereto.

The switching circuit 113-3 is coupled to the local match line L_L1And a global matchline L_G1And is used for matching the local match line L_L1Determines whether to adjust the first level. In some embodiments, the switching circuit 113-3 includes an inverter I1 and a transistor N1. Inverter I1 based on local match line L_L1Level of the output control signal S₁. A transistor N1 is coupled to the global match line L_G1And ground, and is used for controlling signal S₁Selectively conducting to determine whether to adjust the first level.

For example, if the local match line L_L1-Is high, the inverter I1 outputs the control signal S with logic value 0₁. Under this condition, the transistor N1 is not turned on, and the first level is not adjusted. Or, if the local match line L_L1-Is low, the inverter I1 outputs the control signal S with logic value 1₁. Under this condition, the transistor N1 is turned on, and pulls down the first level to a low level (e.g., the low level).

The number of elements of fig. 3 is for illustration and the disclosure is not so limited. In some embodiments, the first level circuitry may include more sets of local memory circuits 113 coupled to the same global match line L_G1。

Fig. 4A is a circuit schematic illustrating the second stage circuit of fig. 1 according to some embodiments of the present disclosure. In some embodiments, the local memory circuit 123 includes a local precharge circuit 123-1, a plurality of CAM cells 123-2, and a protection circuit 123-3.

The local precharge circuit 123-1 is coupled to the local match line L_L2And is used for controlling the local precharge control signal L according to the second level_PR--Determine whether to match the local match line L_L2And (4) pre-charging. For example, when the second level is high and the local precharge control signal L_PRAt logic value 1, the local precharge circuit 123-1 pairs the local match line L_L2Pre-charging to pull the third level high. Under other conditions (e.g. the second level is low or the local precharge control signal L)_PRLogic value 0), local pre-predictionCharging circuit 123-1 does not match local matchline L_L2And (4) pre-charging.

A plurality of CAM cells 123-2 are coupled to a local match line L_L2And for storing data D₂. Each of the plurality of CAM cells 123-2 receives data D via bit line SLP2 and bit line SLN2_CAnd comparing the query data D_CAnd data D₂To selectively adjust the third level. For example, if each CAM cell 123-2 identifies the lookup data D_CIs matched with data D₂The third level is maintained high; conversely, if one of CAM cells 123-2 identifies query data D_CMismatch to data D₂The CAM cell 123-2 pulls the third level low. In some embodiments, the operation of CAM cell 123-2 may refer to a conventional NOR type CAM cell, but the disclosure is not limited thereto.

The protection circuit 123-3 is coupled to the local match line L_L2----And a global matchline L_G2-And is used for controlling the local precharge according to the third level_PRBAdjusting the second level. The protection circuit 123-3 is further used for matching the global match line L_G2A leakage protection is provided to prevent the second level from being erroneously changed. The detailed description about this point will be described with reference to fig. 4B in the following paragraphs.

Fig. 4B is a detailed circuit schematic diagram illustrating the second stage circuit of fig. 4A, according to some embodiments of the present disclosure. The global precharge circuit 120 includes a logic gate G1, an inverter I2, a transistor P2, and a transistor N2. In querying data D_CIs matched with data D₁Under the condition (i.e. the first stage circuit is based on the query data D)_CWhen it is determined not to adjust the first level), the logic gate G1 may be based on the global precharge control signal G_PR2Output control signal S₂. For example, the logic gate G1 can be implemented by, but not limited to, a NAND gate, and the NAND gate can be based on the enabling signal R_OAnd global precharge control signal G_PR2Output control signal S₂. The transistor P2 and the transistor N2 are coupled in series to adjust the second level.

In detail, the first terminal of the transistor P2 is used for receiving the voltage VDD, and the second terminal of the transistor P2 is used for receiving the voltage VDDTwo terminals coupled to a global match line L_G2And the control terminal of the transistor P2 is used for receiving the control signal S₂. The transistor P2 is controlled by the control signal S₂Is conducted to the global match line L_G2And (4) pre-charging. For example, when the signal R is enabled_OAnd global precharge control signal G_PR2When all are logic values 1, the control signal S₂Is a logical value 0. Under this condition, the transistor P2 is turned on to transmit the voltage VDD to the global match line L_G2To raise the second level to a high level (e.g., the level of the voltage VDD).

The inverter I2 is based on the enable signal R_O2Output control signal S₃. A first terminal of the transistor N2 is coupled to a global match line L_G2A second terminal of the transistor N2 is coupled to ground, and a control terminal of the transistor N2 is configured to receive the control signal S₃. The transistor N2 is controlled by the control signal S₃Conducting to pull down the second level to a low level. For example, when the signal R is enabled_OWhen the logic value is 0, the control signal S₃Is a logical value of 1. Under this condition, the transistor N2 is turned on to pull down the second level.

The local precharge circuit 123-1 includes a logic gate G2 and a transistor P3. In the second stage, there is a match line L to the global_G2During precharging, the logic gate G2 can be based on the local precharge control signal L_PROutput control signal S₄. For example, the logic gate G2 can be implemented by, but not limited to, a NAND gate, and the NAND gate can be based on the enabling signal R_OAnd local precharge control signal L_PROutput control signal S₄. A first terminal of the transistor P3 is coupled to receive the voltage VDD, and a second terminal of the transistor P3 is coupled to the local match line L_L2And the control terminal of the transistor P3 is used for receiving the control signal S₄. The transistor P3 is controlled by the control signal S₄Is conducted to the local match line L_L2And (4) pre-charging. For example, when the second level is high and the local precharge control signal L_PRLogic value 1, control signal S₄Is a logical value 0. Under this condition, the transistor P3 is turned on to pass the voltage VDD to the local match line L_L2To pull the third level to a high level.

The protection circuit 123-3 includes transistors N3-N6 and a transistor P4, wherein the transistor P4 and the transistor N3 operate as an inverter and are used for generating the control signal S according to a third level₅。

In detail, a first terminal of the transistor P4 is for receiving the voltage VDD, and a second terminal of the transistor P4 is for outputting the control signal S₅And the control terminal of the transistor P4 is coupled to the local match line L_L2. A first terminal of the transistor N3 is coupled to the second terminal of the transistor P4, and a control terminal of the transistor N3 is coupled to the local match line L_L2. A first terminal of the transistor N4 is coupled to the second terminal of the transistor N3, a second terminal of the transistor N4 is coupled to ground, and a control terminal of the transistor N4 is coupled to a global match line L_G2. The transistor N4 is selectively turned on according to the second level. A first terminal of the transistor N5 is coupled to the local match line L_L2And the control terminal of the transistor N5 is used for receiving the control signal S₅. The transistor N5 is used for controlling the output according to the control signal S₅Is selectively conducted. The first terminal of the transistor N6 is coupled to the second terminal of the transistor N5, the second terminal of the transistor N6 is coupled to ground, and the control terminal of the transistor N6 is configured to receive the local precharge control signal L_PRB. The transistor N6 is used for controlling the local precharge control signal L_PRBIs selectively conducted.

At the second level as high level and the third level as high level (i.e. query data D)_CIs matched with data D₂) Under the condition of (1), the transistors N3 and N4 are turned on and the transistor P4 is turned off to output the control signal S with logic value 0₅. Transistor N5 is responsive to this control signal S₅Is turned off to ensure that the second level is not affected. Thus, the second level is still high to reflect the query data D_CThere is a memory circuit 123-2 stored locally.

Alternatively, the second level is high and the third level is low (i.e. the query data D)_CMismatch to data D₂) Under the condition of (1), the transistor P4 is turned on and the transistor N3 is turned off to output the control signal S with logic value 1₅. Transistor N5 is responsive to this control signal S₅The power-on state is carried out,and transistor N6 is responsive to the local precharge control signal L_PRBConducting to pull down the second level to a low level. Thus, the second level reflects the query data D_CNot stored in local memory circuit 113.

Further, as previously described, if the second level is the low level or the local precharge control signal L_PRAt logic value 0, the local precharge circuit 123-1 does not match the local match line L_L2And (4) pre-charging. Under this condition, the third level and the control signal S₅The logical value of (c) may be floating (floating). The transistor N4 can be turned off according to the second level to cut off the local matchline L_L2-The floating level of the transistor (e.g., the path between transistor N3 and transistor P4). Similarly, the transistor N6 can be based on the local precharge control signal L having a logic value of 0_PRBIs turned off to cut off the control signal S₅Is turned on by a false conduction of the floating logic value (e.g., transistor N5).

In addition, if the memory device 100 further comprises a third-level circuit (not shown), the circuit structure of the third-level circuit is the same as that of the second-level circuit and is coupled to the same global match line L_G2. When the local match line L of the second stage circuit_L2-With a high level (i.e. query data D)_CMatching data D stored in the second stage circuit₂) And a local match line L of the third stage circuit_L2-With a low level (i.e. query data D)_CData D not matched with third stage circuit storage₂) The second level is pulled low. Under this condition, the transistor N4 in the second stage is turned off, resulting in the control signal S₅May be floating. In the third stage circuit, the transistor P4 is turned on to generate the control signal S having a logic value 1₅The transistor N5 responds to the control signal S₅Is turned on and the transistor N6 is responsive to the local precharge control signal L_PRBConducting to ensure that the second level can be pulled down correctly. Thus, the floating control signal S in the second stage circuit can be prevented₅The resulting effect.

Or when the second stage circuit and the third stage circuitLocal match lines L for each of the circuits_L2-All having a high level, a global match line L_G2Will remain high. Under this condition, the transistors N3 and N4 in each stage of circuit are turned on to generate the control signal S with logic value 0₅. As a result, the transistor N5 is turned off to hold the global match line L_G2The level of (c). The leakage protection operations described above with respect to the protection circuit 123-3 ensure that the memory device 100 operates correctly at various stages.

The number of circuits in fig. 4A and 4B is for example, and the disclosure is not limited thereto. In some embodiments, the second level circuitry may include more sets of local memory circuitry 123 coupled to the same global match line L_G2。

In summary, some embodiments of the present disclosure provide a memory device that can perform the precharge operation and the operation of the multi-stage circuit in different periods, and the precharge of the secondary circuit is selectively performed according to the matching result of the primary circuit. As a result, the power consumption and electromigration problems of the memory device can be significantly improved. Furthermore, some embodiments of the present disclosure further provide a protection circuit, which can provide a leakage protection for the selective precharge mechanism to ensure the correct operation of the memory device. In addition, through the control mechanism, the control signals transmitted by the controller circuit can be transmitted through the global matchlines and/or the local matchlines in each stage of circuit to complete the above-mentioned operations at different periods. Thus, the circuit area used by the memory device can be saved.

Although the embodiments of the present disclosure have been described above, the embodiments are not intended to limit the present disclosure, and those skilled in the art can make variations on the technical features of the present disclosure according to the explicit or implicit contents of the present disclosure, and all such variations may fall within the scope of patent protection sought by the present disclosure, in other words, the scope of patent protection of the present disclosure should be subject to the claims of the present specification.