阅读说明：本技术 在光子集成电路中的衬底耦合光栅耦合器 (Substrate coupled grating coupler in photonic integrated circuits ) 是由 王黎明 浦田良平 简·佩蒂凯维奇 吉尔·贝格尔 于 2020-12-30 设计创作，主要内容包括：本公开涉及在光子集成电路中的衬底耦合光栅耦合器。一种光子集成电路芯片,包括衬底和在所述衬底上的晶片。所述晶片本身包括具有锥形部分和光栅特征的光子光栅耦合器。所述光栅特征从所述锥形部分向所述衬底延伸。(The present disclosure relates to substrate coupled grating couplers in photonic integrated circuits. A photonic integrated circuit chip includes a substrate and a wafer on the substrate. The wafer itself includes a photonic grating coupler having a tapered portion and grating features. The grating features extend from the tapered portion toward the substrate.)

1. A Photonic Integrated Circuit (PIC) chip comprising:

a substrate;

a wafer on the substrate; and

a grating coupler within the wafer, the grating coupler comprising a tapered portion and a grating extending from the tapered portion toward the substrate.

2. The chip of claim 1, wherein the wafer comprises:

an insulator layer adjacent to the substrate;

a waveguide layer adjacent to the insulator layer; and

a cladding layer on a side of the waveguide layer opposite the insulator layer.

3. The chip of claim 2, wherein the tapered portion is located in the cladding.

4. The chip of claim 3, wherein the grating coupler is configured to transition an optical path between the tapered portion and the waveguide layer.

5. The chip of claim 2, wherein the grating does not extend into the cladding layer.

6. The chip of claim 2, wherein the grating comprises grating features in two different layers, a first layer of the grating features being closer to the substrate than the tapered portion.

7. The chip of claim 2, in which the grating extends into the insulator layer.

8. The chip of claim 7, wherein the grating extends from the waveguide layer to the substrate.

9. The chip of claim 8, wherein the grating comprises ribs extending through an entire thickness of the insulator layer.

10. A signal transfer assembly comprising:

a PIC chip comprising:

a substrate;

a wafer on the substrate; and

a grating coupler within the wafer, the grating coupler comprising a tapered portion and a grating, the grating extending from the tapered portion toward the substrate; and

a Printed Circuit Board (PCB) on which the PIC chips are mounted such that wafer sides of the PIC chips face the PCB.

11. The assembly of claim 10, further comprising patterned electrical contacts on a cladding of the wafer located furthest from the substrate, the electrical contacts establishing electrical communication between the PIC die and the PCB.

12. The assembly of claim 11, wherein the assembly defines an optical path along which optical signals can enter or exit the PIC chip, the optical path being incident on a side of the grating coupler corresponding to a side of the tapered portion from which the grating extends.

13. A method for constructing a portion of a photonic integrated circuit, comprising:

depositing a substrate;

depositing an insulator layer on the substrate;

depositing a waveguide layer on the insulator layer;

forming a first layer of grating features on the insulator layer or the waveguide layer; and

forming a tapered portion of a grating coupler that is farther from the substrate than a first layer of the grating features.

14. The method of claim 13, wherein the forming of the first layer of grating features comprises: before depositing the waveguide layer, a pattern is etched in the insulator layer and filled with a material.

15. The method of claim 14, wherein the forming of the first layer of grating features comprises: depositing and etching a layer of material on the substrate prior to depositing the insulator layer.

16. The method of claim 15, wherein the forming of the first layer of grating features further comprises: after the insulator layer has been deposited, a pattern is etched in the insulator layer and the pattern is filled with material.

17. The method of claim 13, wherein the forming of the tapered portion comprises depositing a material on top of the waveguide layer.

18. The method of claim 17, further comprising depositing a cladding layer over the waveguide layer such that the tapered portion is located within the cladding layer.

19. The method of claim 18, further comprising forming features in the tapered portion and the waveguide layer for transitioning a photonic signal between the tapered portion and the waveguide layer.

20. The method of claim 13, further comprising:

depositing a cladding layer over the waveguide layer;

patterning electrical contacts on the cladding; and

mounting a chip provided by the substrate, the insulator layer, the waveguide layer, and the cladding layer onto a PCB such that the cladding layer faces the PCB.

Technical Field

The present disclosure relates to substrate coupled grating couplers in photonic integrated circuits.

Background

Known Photonic Integrated Circuits (PICs) are provided in the form of chips that include thick substrate layers. The substrate layer is necessary to provide sufficient structural integrity to the chip to achieve the intended purpose. The wafer used to define the functionality of the PIC is typically deposited on top of the substrate. The wafer side of the PIC die is conventionally referred to as the top side because the wafer is on top, depending on the direction in which the layers of the die are stacked. Similarly, the terms "upper" and "lower" with reference to PIC die architecture are conventionally used to describe increasing and decreasing proximity to the outward facing surface of the wafer, respectively, regardless of the actual orientation of the die.

Photonic signals, such as those carried by fiber optic cables, pass into or out of the PIC through the coupler. There are many types of couplers, but grating couplers are typically used to transmit or receive photonic signals at angles transverse to the plane of the wafer. A typical grating coupler includes a flared portion provided by a portion of waveguide material that defines a generally triangular shape in a plane parallel to the plane of the wafer. The flared portion is sometimes referred to as a tapered portion because it tapers down from a wide end to a relatively narrow connection point to a waveguide of the PIC. A grating in the form of an uneven feature on the side of the tapered portion facing the chip cladding directs a photon signal into or out of the plane of the tapered portion.

In applications where the PIC with the grating coupler communicates with a Printed Circuit Board (PCB), the PIC is placed substrate side down on the PCB. Electrical contact pads are patterned on functional layers of the PCB opposite the substrate and are wire bonded to the PCB. PIC converts photonic signals to or from electrical signals carried by bond wires. The inductance of the wire increases with its length, so the frequency response of communication between the PIC and the PCB is limited by the length of the bond wire. Because the wire bonds extend from the opposite side of the PIC to the PCB, the length of the wire bonds must exceed the thickness of the entire PIC, including the substrate layers. Therefore, the communication frequency response between the PIC and the PCB arranged in this manner is limited by the minimum overall thickness of the PIC.

Disclosure of Invention

According to one aspect of the disclosure, a PIC die including a grating coupler may be mounted to a PCB such that a wafer side of the PIC die faces the PCB. The grating coupler may include a tapered portion and a grating feature. The grating features may be configured to direct optical signals received from the optical cable onto a waveguide layer within the wafer or to direct optical signals received from the waveguide layer out of the optical cable. The grating features may extend from the tapered portion towards the substrate of the chip. The grating feature may comprise two different layers, and one of the two different layers may be located closer to the substrate than the tapered portion.

According to another aspect, a Photonic Integrated Circuit (PIC) chip may include a substrate, a wafer on the substrate, and a grating coupler within the wafer, the grating coupler including a tapered portion and a grating extending from the tapered portion toward the substrate.

In some arrangements, the wafer may include an insulator layer adjacent the substrate, a waveguide layer adjacent the insulator layer, and a cladding layer on a side of the waveguide layer opposite the insulator layer.

In some arrangements, the tapered portion may be located in the cladding.

In some arrangements, the coupler may be configured to transition the optical path between the tapered section and the waveguide layer.

In some arrangements, the grating may not extend into the cladding.

In some arrangements, the grating may comprise grating features in two different layers, a first layer of the grating features being closer to the substrate than the tapered portion.

In some arrangements, the grating may extend into the insulator layer.

In some arrangements, the grating may extend from the waveguide layer to the substrate.

In some arrangements, the grating may comprise ribs extending through the entire thickness of the insulator layer.

In another aspect, a signal transfer component may include a PIC die including a substrate, a wafer on the substrate, and a grating coupler within the wafer, the grating coupler including a tapered portion and a grating. The grating may extend from the tapered portion towards the substrate. The signaling assembly may also include a Printed Circuit Board (PCB) on which the PIC die is mounted such that a wafer side of the PIC die faces the PCB.

In some arrangements, the signal transmission component may include patterned electrical contacts on the cladding of the wafer furthest from the substrate, the contacts establishing electrical communication between the chip and the PCB.

In some arrangements, the signal carrying component may define an optical path along which optical signals may enter or exit the PIC chip, the optical path being incident on a side of the grating coupler corresponding to a side of the tapered portion from which the grating extends.

In another aspect, a method for constructing a portion of a photonic integrated circuit may include depositing a substrate, depositing an insulator layer on the substrate, depositing a waveguide layer on the insulator layer, forming a first layer of grating features in the insulator layer or waveguide layer, and forming tapered portions of a grating coupler farther from the substrate than the first layer of grating features.

In some arrangements, the forming of the first layer of grating features may include, prior to depositing the waveguide layer, etching a pattern in the insulator layer and filling the pattern with a material.

In some arrangements, the forming of the first layer of grating features may include depositing and etching a layer of material on the substrate prior to depositing the insulator layer.

In some arrangements, the forming of the first layer of grating features may further comprise, after the insulator layer has been deposited, etching a pattern in the insulator layer and filling the pattern with a material.

In some arrangements, the forming of the tapered portion may include depositing a material on top of the waveguide layer.

In some arrangements, the method may include depositing a cladding layer on the waveguide layer such that the tapered portion is located within the cladding layer.

In some arrangements, the method may include forming features in the tapered portion and the waveguide layer for transitioning the photonic signal between the tapered portion and the waveguide layer.

In some arrangements, the method may include depositing a cladding layer on the waveguide layer, patterning electrical contacts on the cladding layer, and mounting a chip provided by the substrate, insulator layer, waveguide layer, and cladding layer to a PCB such that the cladding layer faces the PCB.

Drawings

Fig. 1A is a side view of a PIC chip according to a first aspect of the disclosure.

FIGS. 1B-1E show various stages in a process for fabricating the chip of FIG. 1A.

Fig. 2A is a side view of a PIC chip according to a second aspect of the disclosure.

Fig. 2B and 2C show stages in a process for manufacturing the chip of fig. 2A.

Fig. 3A is a side view of a PIC chip according to a third aspect of the disclosure.

Fig. 3B and 3C show stages in a process for manufacturing the chip of fig. 3A.

Fig. 4A is a side view of a PIC chip according to a fourth aspect of the disclosure.

Fig. 4B-4E show various stages in a process for fabricating the chip of fig. 4A.

Fig. 5 is a side view of a PIC chip in accordance with the fifth aspect of the invention.

DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION

Fig. 1 shows a flip-chip arrangement of PIC die 10 on PCB 14. In order of increasing proximity to the PCB 14, the chip 10 includes a substrate 18, a buried oxide or insulator layer 22, a waveguide layer 26, and a cladding layer 30. The substrate 18, insulator layer 22, waveguide layer 26, and cladding layer 30 may be made of any suitable material known for use in photonic circuits. For example, the substrate 18 may be silicon and the insulator layer 22 and cladding layer 30 may be silicon dioxide. Waveguide layer 26, including tapered portion 58, may be silicon alone or a combination of silicon and silicon dioxide. The cladding 30 may include additional materials, such as metals or other reflective materials, suspended in or laminated on the silica. In further examples, the cladding layer 30 may be one or more different dielectric layers. In other examples, the substrate 18, insulator layer 22, waveguide layer 26, and cladding layer 40 may be made of any of a variety of other materials. Suitable compositions include sets of materials having different degrees of transparency so that optical signals can be fed into or out of chip 10 through substrate 18 and insulator 22, or confined in waveguide layer 26 at different locations on chip 10.

The coupling material 34 is located on the opposite side of the substrate 18 from the insulator layer 22, the waveguide layer 26, and the cladding layer 30. The coupling material 34 is an optical medium for connecting an optical cable (not shown) to the chip 10. Light may propagate with little loss between the fiber optic cable and the PIC along an optical path 38, which optical path 38 extends through the coupling material 34. The optical path 38 continues from the coupling material 34 through the substrate 18 and insulator layer 22 to the grating section 42, and the grating section 42 redirects the optical path 38 along the waveguide layer 26.

Communication between the chip 10 and the PCB 14 is made through patterned electrical contacts 46 on the cladding 30, such as solder bumps, metal pads, or short wire bonds. The illustrated example is shown and described in one application, wherein optical signals received by the chip 10 are converted into electrical signals that are transmitted to the PCB 14 through the contacts 46. However, the principles of the present disclosure are generally reversible such that the same structures shown and described herein may be used in applications where the chip 10 receives electrical signals from the PCB 14 through the contacts 46, converts the electrical signals to optical signals, and transmits the optical signals out to the optical cable.

The orientation of the chip 10 shown in fig. 1A, with the wafer side facing the PCB 14, means that the contacts 46 can be relatively short. In particular, the contacts 46 may be shorter elements than are needed to establish communication between the wafer side of the chip 10 and the PCB 14 with the wafer side of the chip 10 facing away from the PCB 14. As a result, the contact 46 may have a relatively low inductance, allowing for a faster frequency response than may be achieved with longer elements.

The optical path 38 travels through the substrate 18 to reach the grating 42, the grating 42 extending from a side of the waveguide layer 26 opposite the substrate 18. Thus, the incidence of the optical path 38 on the coupler provided by the grating 42 and tapered portion 58 differs from typical known grating coupler arrangements in which the optical path 38 reaches or leaves the coupler from the side of the waveguide layer 26 where the grating features 50, 54 are located. Thus, in many applications, efficient design of the architecture of the chip 10 shown in fig. 1 requires derivation of the new shape, size, and spacing of the grating features 50, 54.

The grating 42 is formed of a patterned material in the waveguide layer 26 and the cladding layer 30. In the example shown, both the waveguide-side grating features 50 and the cladding-side grating features 54 are ribs of a material different from the material or materials that would otherwise comprise the layers corresponding to the respective sides of the grating 42, and are discontinuous from adjacent layers. In other examples, the grating 42 is provided by either or both of the material of the waveguide layer 26 extending to adjacent layers in the wafer and the material of adjacent layers in the wafer extending into the waveguide layer. Waveguide-side grating feature 50 may be, for example, silicon dioxide and cladding-side grating feature 54 may be, for example, polysilicon. The elements of the grating 42 are spaced and sized as necessary to redirect the optical path 38 onto the waveguide layer 26 from the angle of incidence of light received from the optical cable. The grating 42 cooperates with a flared or tapered section 58 in the waveguide layer 22. The spacing and relative size of the features in the grating 42 depend on the particular application and may be any combination or pattern of spacing and size effective to redirect the optical path 38 between the waveguide layer 26 and the incidence of the optical path 38 to or from the optical cable. For ease of illustration only, uniform sizes and spacings are depicted in fig. 1-5, and non-uniform spacing and size arrangements are contemplated in connection with any of the other features described herein.

In fig. 1A, the chip 10 is shown with a stacking direction 60 oriented downward, the stacking direction 60 being defined by the direction in which layers accumulate during the process for manufacturing the chip 10. In this process, the substrate 14 is provided as a bottom layer. Insulator layer 22, waveguide layer 26, and cladding layer 30, collectively referred to as a wafer, are sequentially deposited on top of substrate 14, as shown in fig. 1B-1E. The grating 42 or other waveguide features may be provided with an etching step between deposition steps. Referring specifically to fig. 1C and 1D, a pattern may be etched into waveguide layer 26 prior to depositing cladding layer 30. A material may be deposited to fill the pattern etched in waveguide layer 26 and any excess fill may be etched away to provide tapered portion 58. Another pattern may be etched into the tapered portion 58 and filled into the waveguide-side grating features 50 with another material. In other examples, the tapered portion 58 may be deposited and etched after the waveguide-side grating feature 50 is deposited and etched, and before the remainder of the waveguide layer 26 is deposited. Another layer of material may be deposited and etched to provide cladding-side grating features 54, and then the cladding-side grating features 54 may be covered by the deposition of cladding layer 30. Thus, in the process shown in FIGS. 1B-1E, the grating 42 features are produced in two different layers.

The grating 42 in the illustrated example redirects the received signal "down", or in the opposite direction closer to the stacking direction 60 of the chip 10. To this end, the grating 46 is designed to account for refraction of light along the optical path 38 as it passes through the coupling medium 34, the substrate 14, and the insulator layer 18 between the grating 42 and the fiber optic cable. The reference to the stacking direction 60 herein is for orientation purposes only, and the PIC die described and illustrated herein may be fabricated in any manner.

A number of architectures are capable of redirecting the light path 38 downward relative to the stacking direction 60. Further arrangements described below provide specific examples. In various arrangements, like reference numerals refer to like elements, e.g., each of the numbers 18, 118, 218, etc., refer to a substrate, unless otherwise specified.

In fig. 2A, a chip 110 arranged according to another example is shown arranged on a PCB 14. In chip 110, the tapered portion 158 or flared portion is located in the cladding layer 130, rather than in the waveguide layer 126. Thus, the grating 142 extends from the tapered portion 156 toward the substrate 114, or downward with respect to the stacking direction 60. The grating 142 allows the optical path 38 to enter the cladding 130 and extend along the cladding 130 into the tapered portion 158. The tapered section 158 directs the optical path 38 back into the waveguide layer 126 at the narrow end of the tapered section 158. Thus, the optical path 38 is incident on the side of the tapered portion 158 where the grating features 150, 156 are located.

During fabrication of chip 110, the pattern is etched into waveguide layer 126 and filled to create waveguide-side grating features 150, as shown in fig. 2B. Similar to the cladding-side grating features 154, the tapered portions 158 are created by depositing and etching a layer of material before the cladding 130 is deposited, as shown in FIG. 2C. In chip 110, a first layer of grating features 142 (referred to as waveguide-side grating features 150) is deposited before tapered portion 158 and closer to the substrate than tapered portion 158.

In fig. 3A, a chip 210 according to another alternative arrangement is shown arranged on the PCB 14. The grating 242 extends downward from the waveguide layer 226 and the tapered portion 258 and into the insulator layer 222 relative to the stacking direction 60. Thus, grating 242 does not extend into cladding layer 230. Instead of cladding side features, the grating 242 includes insulator side grating features 256, which insulator side grating features 256 may be, for example, polysilicon. Similar to chip 110 of fig. 2A, chip 210 of fig. 3A is oriented such that optical path 38 is incident on a side of the grating coupler corresponding to a side of tapered portion 258 where grating features 250, 256 are located.

During fabrication of chip 210, prior to depositing waveguide layer 226, a pattern is etched into insulator layer 226 and filled to provide a first layer of grating 242 features, referred to as insulator-side grating features 256, as shown in fig. 3B. Turning to fig. 3C, insulator-side grating features 256 are thus deposited and etched, followed by tapered portions 258 and waveguide-side grating features 250, followed by deposition of waveguide layer 226 or any other features at the same height as waveguide layer 226. In other examples, the waveguide layer 226 is deposited immediately after insulator-side grating features 256 are formed, and the pattern is etched into the waveguide layer 226 and filled to provide tapered portions 258 and waveguide-side grating features 250.

In fig. 4A, a chip 310 according to another alternative arrangement is shown arranged on the PCB 14. The insulator side grating features 356 of the grating 342 in the chip 310 extend from the waveguide layer 326 through the entire thickness of the insulator layer 326 to the substrate 314. Similar to chips 110, 210 of fig. 2A and 3A, chip 310 of fig. 4A is oriented such that optical path 38 is incident on a side of the grating coupler corresponding to a side of tapered portion 358 where grating features 350, 356 are located.

Insulator side grating features 356 can be created by steps performed before, after, or both before and after deposition of insulator layer 322. In a step shown in fig. 4B prior to deposition of insulator layer 322, a material for insulator side grating features 356, such as polysilicon, may be deposited on substrate 314 and etched into a desired pattern prior to deposition of insulator layer 322. Insulator layer 322 can then be deposited at the beginning of insulator side grating features 356 as shown in figure 4C. Alternatively or additionally, after the insulator layer 322 has been deposited, the pattern may be etched into the insulator layer 322 and filled with the material of the insulator side grating features 356 to obtain the grating features 356 extending through the insulator layer 322, as shown in fig. 4D. Whether the insulator side grating features 356 can be deposited in a single step depends on their design and size. Depositing a first portion of the design side grating feature 356 prior to depositing the insulator layer 322, then etching a pattern into the insulator layer 322 and filling the pattern with a second portion of the design side grating feature 356 enables designing an insulator side grating feature 356 that may not be deposited and etched as a single layer. In any case, as shown in FIG. 4E, the waveguide-side grating features 350 and tapered portions 358 are deposited and etched on top of the insulator layer 322, and thus farther from the substrate 318 than the insulator-side grating features 356.

In fig. 5, a chip 410 arranged according to another example is shown arranged on the PCB 14. In chip 410, a reflective coating 462, such as a metal layer, is placed on cladding 430 opposite waveguide layer 426 and grating 442. After the cladding 430 is deposited, a portion of the cladding 430 may be etched away to produce a reduced thickness portion, and the reflective coating 462 may be deposited on the etched surface of the cladding 430. The reflective coating 462 may be etched away from a substantial portion of the cladding 430 to leave only the reflective coating 462 on the reduced thickness portion of the cladding 430. The cladding 430 material may then be deposited on the reflective element 462, although this is not shown in FIG. 5. The arrangement shown in fig. 4A causes the optical path 38 to be incident on the grating coupler from the side of the tapered portion 458 where the grating features 450, 454 are located, by reflecting the optical path 38 from the top side of the chip 410 through the cladding-side grating features 454 onto the tapered portion 458.

The reflective coating 462 is positioned on the cladding 430 relative to the optical path 438 and the grating 442 such that an incoming signal along the optical path 430 will be reflected onto the grating 442 and a signal directed from the grating 442 onto the reflective coating 462 will be reflected out along the optical path 438. In the illustrated arrangement, the aforementioned interaction between the optical path 438, the grating 442, and the reflective coating 462 is achieved by directing the optical path 438 around the grating 442 on its way into or out of the chip 410. As the signal enters the chip 410 along the optical path 438, it travels to the reflective coating 462 without traversing the grating 442, and the reflective coating 462 directs the incoming signal to the grating 442, which then orients the signal along the waveguide layer 426. Similarly, if the optical path 438 is reversed, the output signal along the waveguide layer 426 will be directed by the grating 442 onto the reflective layer 462, and then the reflective layer 462 directs the signal out through the substrate 414 without traversing the grating 442 again. In an alternative arrangement, the chip 410 is configured such that the optical path 438 traverses the grating 442 twice. In this arrangement, the grating 442 first directs a signal to the reflective layer 462, and the reflective layer 462 directs the signal to another portion of the grating 442 that ultimately directs the signal onto the waveguide layer 426 or out of the chip 410 through the substrate 414, depending on the direction of the signal.

The architectures shown in fig. 2A-5 are all capable of allowing the optical path 38 to enter or exit the corresponding PIC chip from the side of the grating coupler where the grating features are located. Because grating couplers have previously been designed with grating features facing the top side of the chip from which the optical path enters or exits, grating designs similar to those of previous grating couplers can be used in the arrangements of fig. 2A-5.

It should be understood that any of the above-described features for redirecting the optical path 38 "up" or away from the wafer side of the PIC may be combined in a single chip, as appropriate for a given application. Such a combination may be configured for the desired redirection of the optical path 38 by appropriate design of the grating, taking into account the features implemented.

Although the subject matter herein has been described with reference to particular examples, it is to be understood that these examples are merely illustrative of the principles and applications. It is therefore to be understood that numerous modifications may be made to the illustrative examples and that other arrangements may be devised without departing from the spirit and scope of the subject matter defined by the appended claims.