阅读说明：本技术 显示装置及其制造方法 (Display device and method for manufacturing the same ) 是由 冈部达 家根田刚士 于 2019-02-27 设计创作，主要内容包括：在TFT层形成工序中,首先,在通过进行半导体层形成工序来形成树脂基板(10)上的半导体层之后,通过进行栅极绝缘膜形成工序来形成栅极绝缘膜(13)以覆盖半导体层,接着,通过进行第一金属膜成膜工序、第一光刻工序以及第一蚀刻工序来形成第一金属层(14a),进而,通过进行第二金属膜成膜工序、第二光刻工序以及第二蚀刻工序来形成第二金属层(15a),从而形成层叠有第一金属层(14a)及第二金属层(15a)的栅极层(16a)。(In the TFT layer forming step, a semiconductor layer on a resin substrate (10) is formed by performing a semiconductor layer forming step, a gate insulating film (13) is formed so as to cover the semiconductor layer by performing a gate insulating film forming step, a first metal film forming step, a first photolithography step, and a first etching step are performed to form a first metal layer (14a), and a second metal film forming step, a second photolithography step, and a second etching step are performed to form a second metal layer (15a), thereby forming a gate layer (16a) in which the first metal layer (14a) and the second metal layer (15a) are stacked.)

1. A method for manufacturing a display device includes:

a thin film transistor layer forming step of forming a thin film transistor layer in which a thin film transistor is provided for each sub-pixel on a resin substrate;

a light-emitting element layer forming step of forming a light-emitting element layer in which a light-emitting element is provided for each of the sub-pixels on the thin film transistor layer, the thin film transistor layer forming step including:

a semiconductor layer forming step of forming a semiconductor film on the resin substrate, and then patterning the semiconductor film to form a semiconductor layer;

a gate insulating film forming step of forming a gate insulating film so as to cover the semiconductor layer;

a first metal film forming step of forming a first metal film so as to cover the gate insulating film;

a first photolithography step of forming a first resist pattern by applying a resist to the first metal film and then exposing the resist to light through a first mask;

a first etching step of etching the first metal film exposed from the first resist pattern to form a first metal layer;

a first stripping step of stripping the first resist pattern used in the first etching step;

a second metal film forming step of forming a second metal film so as to cover the first metal layer exposed by the removal of the first resist pattern;

a second photolithography step of forming a second resist pattern by applying a resist to the second metal film and then exposing the resist to light through a second mask;

a second etching step of etching the second metal film exposed from the second resist pattern to form a second metal layer and a gate layer in which the first metal layer and the second metal layer are stacked;

and a second stripping step of stripping the second resist pattern used in the second etching step.

2. The method of manufacturing a display device according to claim 1, wherein the first mask and the second mask are common masks,

the exposure amount in the first photolithography step is smaller than the exposure amount in the second photolithography step.

3. The method of manufacturing a display device according to claim 2, comprising a conductor-making step of making a part of the semiconductor layer conductive using the second metal layer as a mask after the second etching step.

4. The method for manufacturing a display device according to claim 3, wherein the semiconductor film is formed of an oxide semiconductor,

the second etching step includes a step of etching a part of the gate insulating film using the second resist pattern as a mask.

5. The method of manufacturing a display device according to claim 1, comprising a conductor forming step of forming a conductor in a part of the semiconductor layer using the first metal layer as a mask before the second metal film forming step.

6. The method of manufacturing a display device according to claim 5, wherein a length of the second resist pattern is shorter than a length of the first resist pattern in a direction of a channel length of the semiconductor layer.

7. The method for manufacturing a display device according to claim 6, wherein the semiconductor film is formed of an oxide semiconductor,

the first etching step includes a step of etching a part of the gate insulating film using the first resist pattern as a mask.

8. The method for manufacturing a display device according to claim 6, wherein the semiconductor film is formed of an oxide semiconductor,

the second etching step includes a step of etching a part of the gate insulating film using the second resist pattern as a mask.

9. The method of manufacturing a display device according to claim 5, wherein the semiconductor film is formed of low-temperature polysilicon,

in the second photolithography step, the second resist pattern is formed so as to protrude from both end portions of the first metal layer in a channel length direction of the semiconductor layer.

10. The method of manufacturing a display device according to claim 9, wherein in the second etching step, the second metal layer is formed so as to cover both end portions of the first metal layer and a space between both end portions in a channel length direction of the semiconductor layer.

11. The method of manufacturing a display device according to any one of claims 1 to 10, wherein the light-emitting element is an organic electroluminescent element.

12. A display device is provided with:

a resin substrate;

a thin film transistor layer provided on the resin substrate, the thin film transistor layer being provided with a thin film transistor corresponding to each sub-pixel;

a light emitting element layer disposed on the thin film transistor layer and having a light emitting element disposed corresponding to each of the sub-pixels,

a semiconductor layer, a gate insulating film and a gate electrode layer are sequentially provided as the thin film transistor layer on the resin substrate,

the gate layer has a first metal layer provided on the gate insulating film and a second metal layer provided on the first metal layer,

the semiconductor layer has an intrinsic region provided so as to overlap with the gate layer and a pair of conductor regions provided so as to sandwich the intrinsic region,

offset regions are provided on the pair of conductor regions of the intrinsic region so as not to overlap with the first metal layer and the second metal layer,

the length of the second metal layer is equal to or less than the length of the first metal layer in the direction of the channel length of the semiconductor layer.

13. The display device according to claim 12, wherein the semiconductor layer is formed of low temperature polysilicon,

the boundary between the pair of conductor regions and the intrinsic region is provided so as to coincide with a step formed on the surface of the gate insulating film.

14. The display device according to claim 12, wherein the semiconductor layer is formed of an oxide semiconductor,

the boundary between the pair of conductor regions and the intrinsic region is aligned with the end portion of the gate insulating film.

15. A display device is provided with:

a resin substrate;

a thin film transistor layer provided on the resin substrate, the thin film transistor layer being provided with a thin film transistor corresponding to each sub-pixel;

a light emitting element layer disposed on the thin film transistor layer and having a light emitting element disposed corresponding to each of the sub-pixels,

a semiconductor layer made of low-temperature polysilicon, a gate insulating film, and a gate electrode layer are provided in this order as the thin film transistor layer on the resin substrate,

the gate layer has a first metal layer provided on the gate insulating film and a second metal layer provided on the first metal layer,

the semiconductor layer has an intrinsic region provided so as to overlap with the first metal layer and a pair of conductor regions provided so as to sandwich the intrinsic region,

the boundary between the pair of conductor regions and the intrinsic region is aligned with the end of the first metal layer,

in the gate layer overlapping with the intrinsic region, the second metal layer is provided so as to protrude from both end portions of the first metal layer in a direction of a channel length of the semiconductor layer and cover the first metal layer,

the gate layer not overlapping with the semiconductor layer has a portion of the gate layer where the width of the second metal layer is equal to or less than the width of the first metal layer.

16. A display device is provided with:

a resin substrate;

a thin film transistor layer provided on the resin substrate, the thin film transistor layer being provided with a thin film transistor corresponding to each sub-pixel;

a light emitting element layer disposed on the thin film transistor layer and having a light emitting element disposed corresponding to each of the sub-pixels,

a semiconductor layer, a gate insulating film and a gate electrode layer are sequentially provided as the thin film transistor layer on the resin substrate,

the thin film transistor includes a first thin film transistor and a second thin film transistor,

the semiconductor layer includes a first semiconductor layer and a second semiconductor layer provided so as to correspond to the first thin film transistor and the second thin film transistor,

the gate layer includes a first gate layer and a second gate layer provided so as to correspond to the first thin film transistor and the second thin film transistor,

the first gate layer and the second gate layer are provided with a first metal layer provided on the gate insulating film and a second metal layer provided on the first metal layer, respectively,

the first semiconductor layer has a first intrinsic region provided so as to overlap with the first gate layer and a pair of first conductor regions provided so as to sandwich the first intrinsic region,

offset regions are provided on the pair of first conductor regions of the first intrinsic region so as not to overlap the corresponding first metal layer and the second metal layer,

the boundary between the pair of first conductor regions and the first intrinsic region is set to be equal to the step formed on the surface of the gate insulating film,

the length of the corresponding second metal layer is equal to or less than the length of the corresponding first metal layer in the direction of the channel length of the first semiconductor layer,

the second semiconductor layer has a second intrinsic region provided so as to overlap with the corresponding first metal layer and a pair of second conductor regions provided so as to sandwich the second intrinsic region,

the boundaries between the pair of second conductor regions and the second intrinsic regions are arranged to be aligned with the ends of the corresponding first metal layers,

in the second gate layer overlapping the second intrinsic region, the corresponding second metal layer is provided so as to protrude from both end portions of the corresponding first metal layer in a direction of a channel length of the second semiconductor layer and cover the first metal layer,

the second gate layer that does not overlap with the second semiconductor layer has a portion of the second gate layer where the width of the corresponding second metal layer is equal to or less than the width of the corresponding first metal layer.

17. The display device according to claim 16,

the thin-film transistor layer includes: a first inorganic insulating film provided on the gate layer; an intermediate metal layer provided on the first inorganic insulating film; a second inorganic insulating film provided on the intermediate metal layer; and a source layer provided on the second inorganic insulating film,

the gate electrode layer has a gate line and a light emission control line,

the source layer has a source line and a power supply line,

a driving thin film transistor, a writing control thin film transistor, a threshold voltage compensation thin film transistor, and a light emission control thin film transistor each having a first terminal, a second terminal, and a control terminal are provided in the sub-pixel; and a capacitor having a lower electrode and an upper electrode,

the driving thin film transistor is configured to control the amount of current of the light emitting element,

in the write control thin film transistor, the control terminal is electrically connected to the gate line, the first terminal is electrically connected to the source line, and the second terminal is electrically connected to the first terminal of the driving thin film transistor,

in the threshold voltage compensation thin film transistor, the control terminal is electrically connected to the gate line, the first terminal is electrically connected to the second terminal of the driving thin film transistor, and the second terminal is electrically connected to the control terminal of the driving thin film transistor,

in the light emission controlling thin film transistor, the control terminal is electrically connected to the light emission control line, the first terminal is electrically connected to the second terminal of the driving thin film transistor, and the second terminal is electrically connected to the light emitting element,

in the capacitor, the lower electrode provided as the gate layer is electrically connected to a control terminal of the driving thin film transistor, and the upper electrode provided as the intermediate metal layer is electrically connected to the power supply line.

18. The display device according to claim 17, wherein the first thin film transistor is the driving thin film transistor.

19. The display device according to claim 17 or 18, wherein the first thin film transistor is the threshold voltage compensation thin film transistor.

20. The display device according to any one of claims 17 to 19, wherein the second thin film transistor is the write control thin film transistor.

21. The display device according to any one of claims 17 to 20, wherein the gate line and the lower electrode are arranged side by side with each other in each of the sub-pixels, and a distance between the first metal layer of the gate line and the first metal layer of the lower electrode arranged side by side is shorter than a distance between the second metal layer of the gate line and the second metal layer of the lower electrode arranged side by side.

22. The display device according to claim 21, wherein an end portion of the upper electrode on the gate line side is disposed between the first metal layer of the gate lines and the first metal layer of the lower electrode, which are arranged in a plan view.

23. The display device according to any one of claims 17 to 22, wherein the emission control line and the lower electrode are provided so as to be aligned with each other in each of the sub-pixels, and a distance between the first metal layer of the emission control line and the first metal layer of the lower electrode aligned with each other is shorter than a distance between the second metal layer of the emission control line and the second metal layer of the lower electrode aligned with each other.

24. The display device according to claim 23, wherein an end portion of the upper electrode on the light emission control line side is disposed between the first metal layer of the light emission control lines and the first metal layer of the lower electrode which are arranged in parallel with each other in a plan view.

25. The display device according to any one of claims 12 to 24, wherein the first metal layer and the second metal layer are formed of the same refractory metal.

26. The display device according to any one of claims 12 to 25, wherein the light-emitting element is an organic electroluminescent element.

Technical Field

The invention relates to a display device and a method of manufacturing the same.

Background

In recent years, as a display device replacing a liquid crystal display device, a self-luminous organic EL display device using an organic electroluminescence (hereinafter also referred to as EL) element has attracted attention. Among the organic EL display devices, a flexible organic EL display device has been proposed in which an organic EL element, various thin films, and the like are laminated on a flexible resin substrate.

For example, patent document 1 discloses a flexible display having a redundant design including a pair of sinusoidal metal wirings whose phases are shifted by about 180 degrees from each other.

Documents of the prior art

Patent document

Patent document 1: JP 2016-503515A

Disclosure of Invention

Problems to be solved by the invention

In addition, in the flexible display device, when the wiring is formed using a refractory metal such as molybdenum or titanium, for example, when a metal film made of a refractory metal is formed on the gate insulating film, there is a possibility that cracks may be generated in the gate insulating film due to high stress generated in the metal film. In this case, the wiring formed by patterning the metal film made of the refractory metal is disconnected, or moisture enters through a crack formed in the gate insulating film, so that the manufacturing yield is lowered, and the reliability of the display device is lowered. On the other hand, since the refractory metal has a high resistance ratio, the thickness of the refractory metal needs to be increased in order to reduce the wiring resistance. However, if the thickness of the metal film made of a refractory metal is increased, the stress generated in the metal film increases, and thus the above-described crack of the gate insulating film is likely to occur. Therefore, there is a trade-off relationship between reducing the wiring resistance of the wiring using the refractory metal and suppressing the occurrence of cracks in the gate insulating film.

The present invention has been made in view of the above, and an object thereof is to reduce wiring resistance by suppressing the occurrence of cracks in a gate insulating film.

Means for solving the problems

In order to achieve the above object, a method for manufacturing a display device according to the present invention includes: a thin film transistor layer forming step of forming a thin film transistor layer on the resin substrate, the thin film transistor layer including a thin film transistor provided for each sub-pixel; a light-emitting element layer forming step of forming a light-emitting element layer on the thin film transistor layer, the light-emitting element layer having a light-emitting element provided for each of the sub-pixels, the thin film transistor layer forming step including: a semiconductor layer forming step of forming a semiconductor film on the resin substrate, and then patterning the semiconductor film to form a semiconductor layer; a gate insulating film forming step of forming a gate insulating film so as to cover the semiconductor layer; a first metal film forming step of forming a first metal film so as to cover the gate insulating film; a first photolithography step of forming a first resist pattern by applying a resist to the first metal film and then exposing the resist to light through a first mask; a first etching step of etching the first metal film exposed from the first resist pattern to form a first metal layer; a first stripping step of stripping the first resist pattern used in the first etching step; a second metal film forming step of forming a second metal film so as to cover the first metal layer exposed by the removal of the first resist pattern; a second photolithography step of forming a second resist pattern by applying a resist to the second metal film and then exposing the resist to light through a second mask; a second etching step of etching the second metal film exposed from the second resist pattern to form a second metal layer and a gate layer in which the first metal layer and the second metal layer are stacked; and a second stripping step of stripping the second resist pattern used in the second etching step.

Further, a display device according to the present invention includes: a resin substrate; a thin film transistor layer provided on the resin substrate, the thin film transistor layer being provided with a thin film transistor corresponding to each sub-pixel; a light emitting element layer disposed on the thin film transistor layer and having a light emitting element disposed corresponding to each of the sub-pixels, a semiconductor layer, a gate insulating film and a gate electrode layer are sequentially provided as the thin film transistor layer on the resin substrate, wherein the gate layer has a first metal layer provided on the gate insulating film and a second metal layer provided on the first metal layer, the semiconductor layer has an intrinsic region provided so as to overlap with the gate layer and a pair of conductor regions provided so as to sandwich the intrinsic region, offset regions are provided on the pair of conductor regions of the intrinsic region so as not to overlap with the first metal layer and the second metal layer, the length of the second metal layer is equal to or less than the length of the first metal layer in the direction of the channel length of the semiconductor layer.

Further, a display device according to the present invention includes: a resin substrate; a thin film transistor layer provided on the resin substrate, the thin film transistor layer being provided with a thin film transistor corresponding to each sub-pixel; a light-emitting element layer provided on the thin-film transistor layer, a light-emitting element being arranged for each of the sub-pixels, and a semiconductor layer made of low-temperature polysilicon, a gate insulating film, and a gate layer being provided in this order as the thin-film transistor layer on the resin substrate, wherein the gate layer includes a first metal layer provided on the gate insulating film and a second metal layer provided on the first metal layer, the semiconductor layer includes an intrinsic region provided so as to overlap with the first metal layer and a pair of conductor regions provided so as to sandwich the intrinsic region, a boundary between the pair of conductor regions and the intrinsic region is provided so as to be aligned with an end of the first metal layer, and the second metal layer is provided in the gate layer overlapping with the intrinsic region so as to protrude from both ends of the first metal layer in a direction of a channel length of the semiconductor layer and cover the first metal layer And a gate layer which is not overlapped with the semiconductor layer and has a portion where the width of the second metal layer is equal to or less than the width of the first metal layer on the gate layer.

Further, a display device according to the present invention includes: a resin substrate; a thin film transistor layer provided on the resin substrate, the thin film transistor layer being provided with a thin film transistor corresponding to each sub-pixel; a light-emitting element layer provided on the thin-film transistor layer, a light-emitting element being provided for each of the sub-pixels, and a semiconductor layer, a gate insulating film, and a gate layer being provided in this order as the thin-film transistor layer on the resin substrate, wherein the thin-film transistor includes a first thin-film transistor and a second thin-film transistor, the semiconductor layer includes a first semiconductor layer and a second semiconductor layer provided so as to correspond to the first thin-film transistor and the second thin-film transistor, the gate layer includes a first gate layer and a second gate layer provided so as to correspond to the first thin-film transistor and the second thin-film transistor, and the first gate layer and the second gate layer each include a first metal layer provided on the gate insulating film and a second metal layer provided on the first metal layer, the first semiconductor layer has a first intrinsic region provided so as to overlap with the first gate layer and a pair of first conductor regions provided so as to sandwich the first intrinsic region, offset regions are provided so as not to overlap with the corresponding first metal layer and second metal layer on the pair of first conductor region sides of the first intrinsic region, a boundary between the pair of first conductor regions and the first intrinsic region is provided so as to coincide with a step formed on the surface of the gate insulating film, a length of the corresponding second metal layer is equal to or less than a length of the corresponding first metal layer in a channel length direction of the first semiconductor layer, and the second semiconductor layer has a second intrinsic region provided so as to overlap with the corresponding first metal layer and a pair of second conductor regions provided so as to sandwich the second intrinsic region, the boundary between the pair of second conductor regions and the second intrinsic region is aligned with the end portion of the corresponding first metal layer, the corresponding second metal layer of the second gate layer overlapping the second intrinsic region is formed to protrude from the end portion of the corresponding first metal layer in the direction of the channel length of the second semiconductor layer so as to cover the corresponding first metal layer, and the second gate layer not overlapping the second semiconductor layer has a portion of the second gate layer where the width of the corresponding second metal layer is equal to or less than the width of the corresponding first metal layer.

Advantageous effects

According to the present invention, since the gate layer of the thin film transistor layer is formed by stacking the first metal layer formed by the first metal film forming step, the first photolithography step, and the first etching step and the second metal layer formed by the second metal film forming step, the second photolithography step, and the second etching step on the gate insulating film, generation of cracks in the gate insulating film can be suppressed, and wiring resistance of the gate layer can be reduced.

Brief description of the drawings

Fig. 1 is a plan view showing a schematic configuration of an organic EL display device according to a first embodiment of the present invention.

Fig. 2 is a plan view showing a schematic configuration of a display region of an organic EL display device according to a first embodiment of the present invention.

Fig. 3 is a cross-sectional view showing a detailed structure of a display region of the organic EL display device according to the first embodiment of the present invention.

Fig. 4 is an equivalent circuit diagram showing a pixel circuit of the organic EL display device according to the first embodiment of the present invention.

Fig. 5 is a plan view of a TFT layer constituting an organic EL display device according to a first embodiment of the present invention.

Fig. 6 is a cross-sectional view of the TFT layer along line VI-VI in fig. 5.

Fig. 7 is a cross-sectional view of the TFT layer along line VII-VII in fig. 5.

Fig. 8 is a cross-sectional view showing an organic EL layer constituting an organic EL display device according to a first embodiment of the present invention.

Fig. 9 is a sectional view showing a step of forming a semiconductor layer in the method of manufacturing an organic EL display device according to the first embodiment of the present invention, and corresponds to fig. 7.

Fig. 10 is a sectional view showing a first metal film forming step in the method for manufacturing an organic EL display device according to the first embodiment of the present invention, and corresponds to fig. 6.

Fig. 11 is a sectional view showing a first photolithography step in the method for manufacturing an organic EL display device according to the first embodiment of the present invention, and corresponds to fig. 6.

Fig. 12 is a sectional view showing a first etching step in the method for manufacturing an organic EL display device according to the first embodiment of the present invention, and corresponds to fig. 6.

Fig. 13 is a sectional view showing a second metal film formation step in the method for manufacturing an organic EL display device according to the first embodiment of the present invention, and corresponds to fig. 6.

Fig. 14 is a sectional view showing a second photolithography step in the method for manufacturing an organic EL display device according to the first embodiment of the present invention, and corresponds to fig. 6.

Fig. 15 is a sectional view showing a second etching step in the method for manufacturing an organic EL display device according to the first embodiment of the present invention, and corresponds to fig. 6.

Fig. 16 is a sectional view showing a conductor-making step in the method for manufacturing an organic EL display device according to the first embodiment of the present invention, and corresponds to fig. 6.

Fig. 17 is a cross-sectional view of a TFT layer constituting a modification of the organic EL display device according to the first embodiment of the present invention, and corresponds to fig. 6.

Fig. 18 is a cross-sectional view of a TFT layer constituting a modification of the organic EL display device according to the first embodiment of the present invention, and corresponds to fig. 7.

Fig. 19 is a sectional view showing a second photolithography step in the manufacturing method of the modification of the organic EL display device according to the first embodiment of the present invention, and corresponds to fig. 17.

Fig. 20 is a sectional view showing a second etching step in the method for manufacturing a modification of the organic EL display device according to the first embodiment of the present invention, and corresponds to fig. 17.

Fig. 21 is a sectional view showing a conductor forming step in a manufacturing method of a modification of the organic EL display device according to the first embodiment of the present invention, and corresponds to fig. 17.

Fig. 22 is a plan view of a TFT layer constituting an organic EL display device according to a second embodiment of the present invention.

Fig. 23 is a cross-sectional view of the TFT layer along the line XXIII-XXIII in fig. 22.

Fig. 24 is a sectional view showing a conductor-making step in the method for manufacturing an organic EL display device according to the second embodiment of the present invention, and corresponds to fig. 23.

Fig. 25 is a sectional view showing a second metal film formation step in the method for manufacturing an organic EL display device according to the second embodiment of the present invention, and corresponds to fig. 23.

Fig. 26 is a sectional view showing a second photolithography step in the method for manufacturing an organic EL display device according to the second embodiment of the present invention, and corresponds to fig. 23.

Fig. 27 is a sectional view showing a second etching step in the method for manufacturing an organic EL display device according to the second embodiment of the present invention, and corresponds to fig. 23.

Fig. 28 is a cross-sectional view of a TFT layer constituting a modification of the organic EL display device according to the second embodiment of the present invention, and corresponds to fig. 23.

Fig. 29 is a plan view of a TFT layer constituting an organic EL display device according to a third embodiment of the present invention.

Fig. 30 is a cross-sectional view of the TFT layer along line XXX-XXX in fig. 29.

Fig. 31 is a sectional view showing a second photolithography step in the method for manufacturing an organic EL display device according to the third embodiment of the present invention, and corresponds to fig. 30.

Fig. 32 is a sectional view showing a second etching step in the method for manufacturing an organic EL display device according to the third embodiment of the present invention, and corresponds to fig. 30.

Fig. 33 is a plan view of a TFT layer constituting an organic EL display device according to a fourth embodiment of the present invention.

Description of the reference numerals

M first mask, second mask

P sub-pixel

R-resist

Ra first resist Pattern

Second resist pattern of Rb, Rbb, Rbc, Rbe

Step difference of S

Y offset region

9a first initialization TFT (first TFT)

9b threshold Voltage Compensation TFT (first TFT)

9c write control TFT (second TFT)

9d drive TFT (first TFT)

9e Power supply TFT (second TFT)

9f light emission control TFT (second TFT)

9g second initialization TFT (second TFT)

9h capacitor

10 resin substrate layer

12 polysilicon film (semiconductor film)

12a, 12ad, 12b, 12bd, 12cd, 12dd semiconductor layers

12aa, 12ba, 12ca, 12da (one) conductor region

12ab, 12bb, 12cb, 12db (another) conductor region

12ac, 12bc, 12cc, 12dc intrinsic region

13. 13b Gate insulating film

14 first metal film

14a, 14ae, 14b, 14d, 14e, 14g first metal layer

15 second metal film

15a, 15ae, 15b, 15d, 15ee, 15ge, 15gf

16a, 16ae, 16b, 16d gate electrodes (gate layer, lower electrode, control terminal)

16g, 16ge, 16gf gate lines (gate layer)

16e, 16ee luminescence control line (gate layer)

17, 17b, 17e first interlayer insulating film (first inorganic insulating film)

18c, 18cb capacitor electrode (middle metal layer, upper electrode)

18i initialization power line (middle metal layer)

19, 19b, 19e second interlayer insulating film (second inorganic insulating film)

20f Source line (Source layer)

20g power line (Source layer)

30 a-30 e TFT layer

35 organic EL element (light emitting element)

40 organic EL element layer (light-emitting element layer)

50 organic EL display device

Detailed Description

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following embodiments.

First embodiment

Fig. 1 to 21 show a display device and a method of manufacturing the same according to a first embodiment of the present invention. In the following embodiments, an organic EL display device having an organic EL element is exemplified as a display device having a light-emitting element. Here, fig. 1 is a plan view showing a schematic configuration of an organic EL display device 50 according to the present embodiment. Fig. 2 is a plan view schematically showing the structure of the display region D of the organic EL display device 50. Fig. 3 is a cross-sectional view showing a detailed configuration of the display region D of the organic EL display device 50. Fig. 4 is an equivalent circuit diagram showing the pixel circuit 45 of the organic EL display device 50. Fig. 5 is a plan view of the TFT layer 30a constituting the organic EL display device 50. Fig. 6 and 7 are cross-sectional views of the TFT layer 30a along the lines VI-VI and VII-VII in fig. 5. Fig. 8 is a cross-sectional view showing the organic EL layer 33 constituting the organic EL display device 50.

As shown in fig. 1, the organic EL display device 50 has, for example, a display region D for performing image display arranged in a rectangular shape and a frame region F arranged around the display region D. In the present embodiment, although the rectangular display region D is shown, the rectangle also includes a substantially rectangular shape such as a shape with an arc-shaped edge, a shape with an arc-shaped corner, or a shape with a cutout in a part of the edge.

In the display region D, as shown in fig. 2, a plurality of sub-pixels P are arranged in a matrix form. As shown in fig. 2, in the display region D, for example, a sub-pixel P having a red light emitting region Er for red display, a sub-pixel P having a green light emitting region Eg for green display, and a sub-pixel P having a blue light emitting region Eb for blue display are provided adjacent to each other. In the display region D, for example, one pixel is formed by three adjacent subpixels P having a red light-emitting region Er, a green light-emitting region Eg, and a blue light-emitting region Eb.

A terminal portion T is provided at the right end portion in fig. 1 of the frame region F. In the frame region F, as shown in fig. 1, between the display region D and the terminal portion T, a bent portion B that can be bent by 180 ° (U-shape) with the longitudinal direction in the drawing as an axis of bending is provided so as to extend in one direction (the longitudinal direction in the drawing).

As shown in fig. 3, the organic EL display device 50 includes a resin substrate layer 10 provided as a resin substrate, a Thin Film Transistor (TFT) layer 30a provided on the resin substrate layer 10, and an organic EL element layer 40 provided as a light-emitting element layer on the TFT layer 30 a.

The resin substrate layer 10 is made of, for example, polyimide resin.

As shown in fig. 3, the TFT layer 30a includes a base film 11 provided on the resin substrate layer 10, a first initialization TFT9a provided as a pixel circuit 45 (see fig. 4) for each sub-pixel P on the base film 11, a threshold voltage compensation TFT9b, a write control TFT9c, a drive TFT9d, a power supply TFT9e, a light emission control TFT9f, a second initialization TFT9g, and a capacitor 9h, and a planarization film 21 provided on each of the TFTs 9a to 9g and the capacitor 9 h. Here, in the TFT layer 30a, a plurality of pixel circuits 45 are arranged in a matrix corresponding to the plurality of sub-pixels P. In the present embodiment, the pixel circuit 45 having the configuration shown in fig. 4 is exemplified, but the present invention is not limited to the configuration of the pixel circuit 45. In addition, as shown in fig. 2, in the TFT layer 30a, a plurality of gate lines 16g are provided as a gate layer so as to extend parallel to each other in the lateral direction in the drawing. As shown in fig. 2, in the TFT layer 30a, a plurality of emission control lines 16e are provided as a gate layer so as to extend in parallel with each other in the lateral direction in the drawing. As shown in fig. 2, in the TFT layer 30a, a plurality of initialization power supply lines 18i are provided as intermediate metal layers so as to extend parallel to each other in the lateral direction in the drawing. As shown in fig. 2, the emission control lines 16e are provided adjacent to the gate lines 16g and the initialization power supply lines 18i in a plan view. In the TFT layer 30a, as shown in fig. 2, a plurality of source lines 20f are provided as a source layer so as to extend in parallel with each other in the vertical direction in the drawing. In addition, as shown in fig. 2, in the TFT layer 30a, a plurality of power supply lines 20g are provided as a source layer so as to extend in parallel with each other in the longitudinal direction in the drawing. As shown in fig. 2, each power supply line 20g is provided adjacent to each source line 20f in a plan view.

Here, each of the first to second initializing TFTs 9a to 9g includes: a first terminal (see circular number 1 in fig. 4) and a second terminal (see circular number 2 in fig. 4) which are arranged so as to be spaced apart from each other; and a control terminal for controlling conduction between the first terminal and the second terminal. As described in fig. 4, the definitions of the first terminal and the second terminal are common to all of the TFTs 9a to 9 g.

As shown in fig. 4, the first initializing TFT9a has a control terminal electrically connected to the corresponding gate line 16g, a first terminal electrically connected to the gate electrode 16a of the capacitor 9h described later, and a second terminal electrically connected to the corresponding initializing power supply line 18i in each sub-pixel P. Here, the first initialization TFT9a is configured to initialize the voltage applied to the control terminal of the driving TFT9d by applying the voltage of the initialization power supply line 18i to the capacitor 9 h. In addition, the control terminal of the first initialization TFT9a is electrically connected to the gate line 16g, and the gate line 16g is scanned before the gate line 16g electrically connected to the control terminals of the threshold voltage compensation TFT9b, the write control TFT9c, and the second initialization TFT9 g.

As shown in fig. 4, the threshold-voltage compensating TFT9b has, in each sub-pixel P, a control terminal electrically connected to the corresponding gate line 16g, a first terminal electrically connected to the second terminal of the driving TFT9d, and a second terminal electrically connected to the control terminal of the driving TFT9 d. Here, the threshold voltage compensating TFT9b is configured to put the driving TFT9d in a diode-connected state in response to selection of the gate line 16g to compensate for the threshold voltage of the driving TFT9 d.

As shown in fig. 4, the write control TFT9c has, in each subpixel P, a control terminal electrically connected to the corresponding gate line 16g, a first terminal electrically connected to the corresponding source line 20f, and a second terminal electrically connected to the first terminal of the driving TFT9 d. Here, the write control TFT9c is configured to apply the voltage of the source line 20f to the first terminal of the driving TFT9d in response to selection of the gate line 16 g.

As shown in fig. 4, the driving TFT9d has, in each sub-pixel P, a control terminal electrically connected to the first terminal of the first initialization TFT9a and the second terminal of the threshold voltage compensation TFT9b, a first terminal electrically connected to each of the second terminals of the write control TFT9c and the power supply TFT9e, and a second terminal electrically connected to each of the first terminals of the threshold voltage compensation TFT9b and the emission control TFT9 f. Here, the driving TFT9d is configured to apply a driving current corresponding to a voltage applied between its control terminal and its first terminal to the first terminal of the light emission controlling TFT9f, thereby controlling the amount of current of the organic EL element 35.

Specifically, as shown in fig. 3 and 6, the driving TFT9d has a semiconductor layer 12ad, a gate insulating film 13, a gate electrode (control terminal) 16a, a first interlayer insulating film 17, a second interlayer insulating film 19, and a first terminal 20a and a second terminal 20b, which are provided in this order on a base film 11. Here, as shown in fig. 5 and 6, the semiconductor layer 12ad is provided in a substantially H-shape on the base film 11. As shown in fig. 5 and 6, the semiconductor layer 12ad includes an intrinsic region 12ac provided to overlap with the gate electrode 16a in a plan view, and a pair of conductor regions 12aa and 12ab (dotted portions in fig. 5) provided to sandwich the intrinsic region 12 ac. As shown in fig. 5, the middle portion of the intrinsic region 12ac is substantially V-shaped in plan view. As shown in fig. 3, 6, and 7, the gate insulating film 13 is provided so as to cover the semiconductor layer 12 ad. As shown in fig. 6, the surface of the gate insulating film 13 exposed from the gate electrode 16a has a two-step level difference S formed by a first etching step and a second etching step, which will be described later, along the peripheral edge of the gate electrode 16 a. As shown in fig. 3, 5, and 6, the gate electrode 16a is provided in an island shape having a rectangular shape in a plan view so as to overlap the intrinsic region 12ac of the semiconductor layer 12ad on the gate insulating film 13. As shown in fig. 5 and 6, the gate electrode 16a includes a first metal layer 14a provided on the gate insulating film 13 and a second metal layer 15a provided on the first metal layer 14 a. As shown in fig. 5 to 7, the length of the second metal layer 15a is equal to or less than the length of the first metal layer 14a in the direction L (lateral direction in fig. 5) of the channel length of the intrinsic region 12ac of the semiconductor layer 12a and the direction orthogonal thereto (longitudinal direction in fig. 5). The first metal layer 14a and the second metal layer 15a are made of the same refractory metal such as tungsten, tantalum, molybdenum, niobium, titanium, and molybdenum nitride. Also, as shown in fig. 6, the intrinsic region 12ac of the semiconductor layer 12ad is provided to match the first metal layer 14 a. In the present specification, "matching" includes not only a case where the side surfaces of the two target layers are positioned on the same plane in the vertical direction but also a case where the side surfaces of the two target layers are continuously formed into inclined surfaces having a tapered shape or the like, and includes, not strictly limited to a case where the side surfaces are aligned, a side surface shift of about 2 μm to 3 μm due to a difference in etching rate or the like. As shown in fig. 3, 6, and 7, the first interlayer insulating film 17 is provided so as to cover the gate electrode 16a, the emission control line 16e, and the gate line 16 g. As shown in fig. 3, 6, and 7, the second interlayer insulating film 19 is provided on the first interlayer insulating film 17 via a capacitor electrode 18c described later. As shown in fig. 3, the first terminal 20a and the second terminal 20b are provided on the second interlayer insulating film 19 so as to be spaced apart from each other. As shown in fig. 3, the first terminal 20a and the second terminal 20b are electrically connected to the conductor region 12aa and the conductor region 12ab of the semiconductor layer 12ad, respectively, via contact holes formed in the laminated film of the gate insulating film 13, the first interlayer insulating film 17, and the second interlayer insulating film 19. As shown in fig. 7, the gate line 16g in which the first metal layer 14g and the second metal layer 15g are stacked and the emission control line 16e in which the first metal layer 14e and the second metal layer 15e are stacked have the same stacked structure as the stacked structure of the gate electrode 16 a.

As shown in fig. 4, the power supply TFT9e has, in each sub-pixel P, a control terminal electrically connected to the corresponding light emission control line 16e, a first terminal electrically connected to the corresponding power supply line 20g, and a second terminal electrically connected to the first terminal of the driving TFT9 d. Here, the power supply TFT9e is configured to apply the voltage of the power supply line 20g to the first terminal of the driving TFT9d in response to selection of the light emission control line 16 e.

As shown in fig. 4, the light emission controlling TFT9f has, in each sub-pixel P, a control terminal electrically connected to the corresponding light emission control line 16e, a first terminal electrically connected to the second terminal of the driving TFT9d, and a second terminal electrically connected to the first electrode 31 of the organic EL element 35 described later. Here, the light emission controlling TFT9f is configured to apply the above-described drive current to the organic EL element 35 in response to selection of the light emission control line 16 e.

Specifically, as shown in fig. 3, the light emission controlling TFT9f has a semiconductor layer 12ae, a gate insulating film 13, a gate electrode (control terminal) 16b, a first interlayer insulating film 17, a second interlayer insulating film 19, and a first terminal 20c and a second terminal 20d, which are provided in this order on a base film 11. Here, the semiconductor layer 12ae is provided in an island shape on the base film 11, and includes an intrinsic region and a pair of conductor regions provided with the intrinsic region therebetween, similarly to the semiconductor layer 12 ad. In addition, as shown in fig. 3, the gate insulating film 13 is provided so as to cover the semiconductor layer 12 ae. In addition, as shown in fig. 3, the gate electrode 16b is provided on the gate insulating film 13 so as to overlap with the intrinsic region of the semiconductor layer 12 ae. As shown in fig. 3, the first interlayer insulating film 17 and the second interlayer insulating film 19 are sequentially provided so as to cover the gate electrode 16 b. In addition, as shown in fig. 3, the first terminal 20c and the second terminal 20d are provided on the second interlayer insulating film 19 so as to be spaced apart from each other. As shown in fig. 3, the first terminal 20c and the second terminal 20d are electrically connected to the pair of conductor regions of the semiconductor layer 12ae through contact holes formed in the stacked film of the gate insulating film 13, the first interlayer insulating film 17, and the second interlayer insulating film 19, respectively. In addition, the first initialization TFT9a, the threshold voltage compensation TFT9b, the write control TFT9c, the power supply TFT9e, and the second initialization TFT9g have substantially the same configuration as the light emission control TFT9 f.

As shown in fig. 4, the second initializing TFT9g has, in each sub-pixel P, its control terminal electrically connected to the corresponding gate line 16g, its first terminal electrically connected to the organic EL element 35, and its second terminal electrically connected to the corresponding initializing power supply line 18 i. Here, the second initializing TFT9g is configured to reset the electric charges accumulated in the first electrode 31 of the organic EL element 35 in response to the selection of the gate line 16 g.

As shown in fig. 5 and 7, the capacitor 9h includes a gate electrode 16a provided as a lower electrode, a first interlayer insulating film 17 provided as a first inorganic insulating film on the gate electrode 16a, and a capacitor electrode 18c provided as an upper electrode and an intermediate metal layer on the first interlayer insulating film 17 so as to overlap with the gate electrode 16a in a plan view. As shown in fig. 4, the capacitor 9h is electrically connected to the gate electrode 14a of the driving TFT9d, the first terminal of the first initialization TFT9a and the second terminal of the threshold voltage compensation TFT9b, and the capacitor electrode 18c is electrically connected to the corresponding power supply line 20g in each sub-pixel P, by forming the gate electrode 14a of the capacitor with the gate electrode 14a of the driving TFT9 d. Here, the capacitor 9h is configured to store the voltage of the corresponding source line 20f when the corresponding gate line 16g is in the selected state, and to maintain the voltage applied to the gate electrode 16a of the driving TFT9d when the corresponding gate line 16g is in the unselected state by holding the stored voltage. As shown in fig. 5, the capacitor electrode 18c is provided outside the peripheral end of the gate electrode 16a over the entire periphery of the peripheral end of the gate electrode 16 a. As shown in fig. 5 and 7, the capacitor electrode 18c is provided with an opening 18m exposing the first interlayer insulating film 17. As shown in fig. 6 and 7, a second interlayer insulating film 19 is provided as a second inorganic insulating film on the capacitor electrode 18c so as to cover the capacitor electrode 18 c. The second interlayer insulating film 19 is provided with a connection line 20e, and the connection line 20e is electrically connected to the gate electrode 16a via a contact hole formed in the first interlayer insulating film 17 and the second interlayer insulating film 19 exposed from the opening 18m of the capacitor electrode 18 c.

Here, as shown in fig. 5, in each sub-pixel P, a gate line 16g and a gate electrode (lower electrode) 16a (lower side portion in the figure) are provided so as to be aligned with each other. As shown in fig. 7, the distance Wa between the first metal layer 14g of the gate line 16g and the first metal layer 14a of the gate electrode (lower electrode) 16a is shorter than the distance Wb between the second metal layer 15g of the gate line 16g and the second metal layer 15a of the gate electrode (lower electrode) 16 a. As shown in fig. 5 and 7, the end of the capacitor electrode (upper electrode) 18c on the gate line 16g side is disposed between the first metal layer 14g of the gate line 16g and the first metal layer 14a of the gate electrode (lower electrode) 16a, which are arranged in a row, in a plan view.

In each sub-pixel, the light emission control line 16e and the gate electrode (lower electrode) 16a (upper side portion in the figure) are arranged in line with each other as shown in fig. 5. As shown in fig. 7, the distance Wc between the first metal layer 14e of the light emission control line 16e and the first metal layer 14a of the gate electrode (lower electrode) 16a arranged to each other is shorter than the distance Wb between the second metal layer 15e of the light emission control line 16e and the second metal layer 15a of the gate electrode (lower electrode) 16a arranged to each other. As shown in fig. 5 and 7, the end of the capacitor electrode (upper electrode) 18c on the light-emission control line 16e side is disposed between the first metal layer 14e of the light-emission control line 16e and the first metal layer 14a of the gate electrode (lower electrode) 16a, which are arranged in a line, in plan view.

As shown in fig. 3, the organic EL element layer 40 corresponds to the plurality of pixel circuits 45, and includes a plurality of organic EL elements 35 provided as a plurality of light emitting elements so as to be arranged in a matrix on the planarization film 21, and a sealing film 39 provided so as to cover the respective organic EL elements 35.

As shown in fig. 3, the organic EL element 35 has a first electrode 31 provided on the planarization film 21, an organic EL layer 33 provided on the first electrode 31, and a second electrode 34 provided on the organic EL layer 33 in a common manner over the entire display region D.

As shown in fig. 3, the first electrode 31 is electrically connected to the second terminal 20d of the emission control TFT9f of each sub-pixel P via a contact hole formed on the planarization film 21. The first electrode 31 has a function of injecting holes (holes) into the organic EL layer 33. In addition, in order to improve the hole injection efficiency into the organic EL layer 33, the first electrode 31 is preferably formed of a material having a large work function. Examples of the material constituting the first electrode 31 include metal materials such as silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au), titanium (Ti), ruthenium (Ru), manganese (Mn), indium (In), iridium (Yb), lithium fluoride (LiF), platinum (Pt), palladium (Pd), molybdenum (Mo), iridium (Ir), and tin (Sn). The material constituting the first electrode 31 may be an alloy such as asbestos (At)/asbestos oxide (AtO 2). In addition, the material constituting the first electrode 31 may be, for example, a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), or the like. The first electrode 31 may be formed by stacking a plurality of layers made of the above-described materials. Examples of the compound material having a large work function include Indium Tin Oxide (ITO) and Indium Zinc Oxide (IZO).

The peripheral end of the first electrode 31 is covered with an edge cover 32 provided in a lattice shape over the entire display region D. Here, as a material constituting the edge cover 32, for example, a positive photosensitive resin such as a polyimide resin, an acrylic resin, a silicone resin, or a novolac resin can be cited.

As shown in fig. 8, the organic EL layer 33 includes a hole injection layer 1, a hole transport layer 2, a light-emitting layer 3, an electron transport layer 4, and an electron injection layer 5, which are provided in this order on the first electrode 31.

The hole injection layer 1 is also called an anode buffer layer, and has a function of bringing the energy levels of the first electrode 31 and the organic EL layer 33 close to each other to improve the efficiency of hole injection from the first electrode 31 into the organic EL layer 33. Examples of the material constituting the hole injection layer 1 include triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, phenylenediamine derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, and stilbene derivatives.

The hole transport layer 2 has a function of improving the efficiency of transporting holes from the first electrode 31 to the organic EL layer 33. Examples of the material constituting the hole transport layer 2 include porphyrin derivatives, aromatic tertiary amine compounds, styrylamine derivatives, polyvinylcarbazole, polyparaphenylene vinylene, polysilane, triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, pyrazolone derivatives, phenylenediamine derivatives, arylamine derivatives, amine-substituted chalcone derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, stilbene derivatives, hydrogenated amorphous silicon, zinc sulfide, and zinc selenide.

The light-emitting layer 3 is a region in which holes and electrons are injected from the first electrode 31 and the second electrode 34, respectively, and are recombined when a voltage is applied to the first electrode 31 and the second electrode 34. Here, the light-emitting layer 3 is formed of a material having high light-emitting efficiency. Examples of the material constituting the light-emitting layer 3 include metal oxide compounds [ 8-hydroxyquinoline metal complexes ], naphthalene derivatives, anthracene derivatives, diphenylethylene derivatives, vinyl acetone derivatives, triphenylamine derivatives, butadiene derivatives, coumarin derivatives, benzoxazole derivatives, oxadiazole derivatives, oxazole derivatives, benzimidazole derivatives, thiadiazole derivatives, benzothiazole derivatives, styryl derivatives, styrylamine derivatives, bisstyrylbenzene derivatives, triphenylvinylbenzene derivatives, perylene derivatives, violene derivatives, aminopyrene derivatives, pyridine derivatives, rhodamine derivatives, acridine derivatives, phenoxazone, quinacridone derivatives, polyparavinylene phenylene, polysilane, and the like.

The electron transport layer 4 has a function of efficiently moving electrons to the light emitting layer 3. Here, as a material constituting the electron transport layer 4, for example, as an organic compound, oxadiazole derivatives, triazole derivatives, benzoquinone derivatives, naphthoquinone derivatives, anthraquinone derivatives, tetracyanoanthraquinone dimethane derivatives, diphenoquinone derivatives, fluorenone derivatives, silicon derivatives, metal oxygen compounds, and the like can be cited.

The electron injection layer 5 has a function of increasing efficiency of injecting electrons from the second electrode 34 into the organic EL layer 33 by bringing energy levels of the second electrode 34 and the organic EL layer 33 close to each other, and by this function, a driving voltage of the organic EL element 35 can be reduced. In addition, the electron injection layer 5 is also referred to as a cathode buffer layer. Here, as a material constituting the electron injection layer 5, for example, lithium fluoride (LiF) and magnesium fluoride (MgF) can be cited₂) Calcium fluoride (CaF)₂) Strontium fluoride (SrF)₂) Barium fluoride (BaF)₂) Such an inorganic basic compound, alumina (Al)₂O₃) Strontium oxide (SrO), and the like.

As shown in fig. 3, the second electrode 34 is provided to cover the organic EL layer 33 of each sub-pixel P and the edge cover 32 common to all sub-pixels P. The second electrode 34 has a function of injecting electrons into the organic EL layer 33. The second electrode 34 is more preferably made of a material having a small work function in order to improve the efficiency of electron injection into the organic EL layer 33. Examples of the material constituting the second electrode 34 include silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au), calcium (Ca), titanium (Ti), yttrium (Y), sodium (Na), ruthenium (Ru), manganese (Mn), indium (In), magnesium (Mg), lithium (Li), ytterbium (Yb), and lithium fluoride (LiF). The second electrode 34 may be made of, for example, magnesium (Mg)/copper (Cu), magnesium (Mg)/silver (Ag), sodium (Na)/potassium (K), asbestos (At)/asbestos oxide (AtO)₂) Lithium (Li)/aluminum (Al), lithium (Al)/calcium (Ca)/aluminum (Al), lithium fluoride (LiF)/calcium (Ca)/aluminum (Al), and the like. The second electrode 34 may be formed of a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), Indium Tin Oxide (ITO), or Indium Zinc Oxide (IZO). The second electrode 34 may be formed by laminating a plurality of layers made of the above-described materials. Examples of the material having a small work function include magnesium (Mg), lithium (Li), lithium fluoride (LiF), magnesium (Mg)/copper (Cu), magnesium (Mg)/silver (Ag), sodium (Na)/potassium (K), lithium (Li)/aluminum (Al), lithium (Li)/calcium (Ca)/aluminum (Al), lithium fluoride (LiF)/calcium (Ca)/aluminum (Al).

As shown in fig. 3, the sealing film 39 includes a first sealing inorganic insulating film 36 provided so as to cover the second electrode 34, a sealing organic film 37 provided on the first sealing inorganic insulating film 36, and a second sealing inorganic insulating film 38 provided so as to cover the sealing organic film 37, and has a function of blocking moisture, oxygen, or the like to protect the organic EL layer 33. Here, the first sealing inorganic insulating film 36 and the second sealing inorganic insulating film 38 are made of, for example, silicon oxide (SiO)₂) Alumina (Al)₂O₃) Silicon nitride (Si)₃N₄) And silicon nitride (SiNx (x is a positive number)), silicon carbonitride (SiCN), and the like. In addition, seal upThe organic film 37 is made of an organic material such as an acrylic resin, a polyurea resin, a parylene resin, a polyimide resin, or a polyamide resin.

In the organic EL display device 50 configured as described above, if the corresponding light-emission control line 16e is selected to be in an inactive state in each sub-pixel P, the organic EL element 35 is in a non-light-emission state. In this non-light emission state, by selecting the corresponding gate line 16g (electrically connected to the first initialization TFT9a), a gate signal is input to the first initialization TFT9a via its gate line 16g, so that the first initialization TFT9a is in a conducting state, and the voltage of the corresponding initialization power supply line 18i is applied to the capacitor 9h while the driving TFT9d is brought into a conducting state. Thereby, the electric charge of the capacitor 9h is discharged, and the voltage applied to the control terminal (gate electrode) 16a of the driving TFT9d is initialized. Next, when the corresponding gate line 16g (electrically connected to the threshold voltage compensation TFT9b, the write control TFT9c, and the second initialization TFT9g) is selected to be in an active state, the threshold voltage compensation TFT9b and the write control TFT9c are in an on state, a predetermined voltage corresponding to a source signal transmitted via the corresponding source line 20f is written into the capacitor 9h via the diode-connected driving TFT9d, and the second initialization TFT9g is in an on state, and an initialization signal is applied to the first electrode 31 of the organic EL element 35 via the corresponding initialization power line 18i, whereby the charge accumulated in the first electrode 31 is reset. Thereafter, the corresponding light emission control line 16e is selected, the power supply TFT9e and the light emission control TFT9f are turned on, and a drive current corresponding to the voltage applied to the control terminal (gate electrode) 16a of the drive TFT9d is supplied from the corresponding power supply line 20g to the organic EL element 35. In this way, in the organic EL display device 50, the organic EL element 35 emits light at a luminance corresponding to the drive current in each sub-pixel P, and image display is performed.

Next, a method for manufacturing the organic EL display device 50 according to the present embodiment will be described. The method for manufacturing the organic EL display device 50 according to the present embodiment includes: the method includes a TFT layer forming step and an organic EL element layer forming step, which are performed in this order by a semiconductor layer forming step, a gate insulating film forming step, a first metal film forming step, a first photolithography step, a first etching step, a first stripping step, a second metal film forming step, a second photolithography step, a second etching step, a second stripping step, and a conductor forming step. Fig. 9 is a sectional view showing a step of forming a semiconductor layer in the method of manufacturing the organic EL display device 50, and corresponds to fig. 7. Fig. 10, 11, 12, 13, 14, 15, and 16 are cross-sectional views showing the first metal film forming step, the first photolithography step, the first etching step, the second metal film forming step, the second photolithography step, the second etching step, and the conductor forming step in the method for manufacturing the organic EL display device 50, respectively, and correspond to fig. 6.

< TFT layer Forming Process >

First, an inorganic insulating film (having a thickness of about 1000 nm) such as a silicon oxide film is formed on the resin substrate layer 10 formed on the glass substrate by, for example, a plasma cvd (chemical Vapor deposition) method, thereby forming the base film 11.

Next, an amorphous silicon film (having a thickness of about 50 nm) is formed over the entire substrate on which the base film 11 is formed by a plasma CVD method, for example, and the amorphous silicon film is crystallized by laser annealing or the like to form a polysilicon film 12 (see the two-dot chain line in fig. 9), and then the polysilicon film 12 is patterned to form a semiconductor layer 12a and the like as shown in fig. 9 (a semiconductor layer forming step).

Then, an inorganic insulating film (about 100 nm) such as a silicon oxide film is formed on the entire substrate on which the semiconductor layer 12a and the like are formed by, for example, a plasma CVD method, and the gate insulating film 13 is formed so as to cover the semiconductor layer 12a (gate insulating film forming step).

Further, a molybdenum film (having a thickness of about 125 nm) is formed by, for example, a sputtering method on the entire substrate on which the gate insulating film 13 is formed, and as shown in fig. 10, the first metal film 14 is formed so as to cover the gate insulating film 13 (first metal film forming step).

Next, after applying the resist R on the first metal film 14, as shown in fig. 11, the resist R (two-dot chain line in fig. 11) is exposed through the first mask M to form a first resist pattern Ra (first photolithography step).

Further, the first metal film 14 exposed from the first resist pattern Ra is etched to form first metal layers 14a, 14e, 14g, and the like as shown in fig. 12 (first etching step). Here, in the first etching step, since the surface layer of the gate insulating film 13 underlying the first metal film 14 is also etched, a step of one level is formed on the surface of the gate insulating film 13 as shown in fig. 12.

Thereafter, the first resist pattern Ra used in the first etching step is stripped (first stripping step).

Further, a molybdenum film (having a thickness of about 125 nm) is formed by, for example, sputtering so as to cover the first metal layers 14a, 14e, and 14g exposed by stripping the first resist pattern Ra, and a second metal film 15 is formed as shown in fig. 13 (second metal film forming step).

Next, after a resist R is applied to the second metal film 15, the resist R is exposed to light through a second mask M to form a second resist pattern Rb as shown in fig. 14 (second photolithography step). Here, by setting the exposure amount in the second photolithography step to be larger than the exposure amount in the first photolithography step, a common mask to the first mask M can be used for the second mask M.

Further, the second metal film 15 exposed from the second resist pattern Rb is etched to form second metal layers 15a, 15e, and 15g, and a gate layer including a gate electrode 16a, a light-emitting control line 16e, and a gate line 16g in which the first metal layers 14a, 14e, and 14g and the second metal layers 15a, 15e, and 15g are stacked, respectively, as shown in fig. 15 (second etching step). Here, in the second etching step, since the surface layer of the gate insulating film 13 underlying the second metal film 14 is also etched again, a step S of two steps is formed on the surface of the gate insulating film 13 as shown in fig. 15. Further, it is found that the gate electrode layer including the gate electrode 16a, the emission control line 16e, and the gate line 16g is formed by repeating the formation of the metal film and the patterning twice, based on the two-step difference S formed on the surface of the gate insulating film 13.

Thereafter, the second resist pattern Rb used in the second etching step is removed (second removal step).

Next, impurity ions are doped into the semiconductor layer 12a or the like by using the gate electrode 16a, the light emission control line 16e, and the gate line 16g as masks, whereby a part of the semiconductor layer 12a or the like is made conductive as shown in fig. 16, and semiconductor layers 12ad, 12ae or the like having a conductor region 12aa, a conductor region 12ab, and an intrinsic region 12ac are formed (a conductive step). In addition, although the manufacturing method in which the conductor forming step is performed after the second peeling step is exemplified in the present embodiment, the conductor forming step may be performed before the second peeling step.

Then, an inorganic insulating film (having a thickness of about 100 nm) such as a silicon oxide film is formed on the entire substrate on which the semiconductor layers 12ad, 12ae and the like are formed by, for example, a plasma CVD method, thereby forming the first interlayer insulating film 17.

Next, a metal film such as a molybdenum film (having a thickness of about 250 nm) is formed on the entire substrate on which the first interlayer insulating film 17 is formed, for example, by a sputtering method, and then the metal film is patterned to form an intermediate metal layer such as the capacitor electrode 18c and the initializing power supply line 18 i. The intermediate metal layer may be used together with the gate layer as a routing line for routing a data signal line from a terminal of the terminal section T to the display region D. In this case, in order to adjust the wiring resistance of the routing wiring, it is preferable that the gate layer and the intermediate metal layer be made of the same metal material and have the same film thickness. Therefore, the intermediate metal layer is preferably formed as a metal laminated film of the first metal layer and the second metal layer by the same process as the gate layer.

Further, an inorganic insulating film (having a thickness of about 500 nm) such as a silicon oxide film is formed on the entire substrate on which the capacitor electrode 18c and the like are formed, for example, by a plasma CVD method, and after the second interlayer insulating film 19 is formed, a stacked film of the gate insulating film 13, the first interlayer insulating film 17, and the second interlayer insulating film 19 is patterned to form a contact hole.

Then, a titanium film (having a thickness of about 30 nm), an aluminum film (having a thickness of about 300 nm), a titanium film (having a thickness of about 50 nm), and the like are sequentially formed over the entire substrate having the contact holes formed thereon by, for example, a sputtering method, and after the source metal film is formed, the source metal film is patterned to form the connection wiring 20e, the source line 20f, the power supply line 20g, and the like.

Finally, the planarization film 21 is formed by applying a polyimide-based photosensitive resin film (having a thickness of about 2 μm) over the entire substrate on which the connection wiring 20e and the like are formed, for example, by a spin coating method or a slit coating method, and then pre-baking, exposing, developing, and post-baking the applied film.

As described above, the TFT layer 30a may be formed.

< organic EL element layer Forming Process >

On the planarization film 21 of the TFT layer 30a, after the first electrode 31, the edge cap 32, the organic EL layer 33 (the hole injection layer 1, the hole transport layer 2, the light-emitting layer 3, the electron transport layer 4, the electron injection layer 5), and the second electrode 34 are formed using a known method, the organic EL element layer 40 is formed by forming the sealing film 39 (the first sealing inorganic insulating film 36, the sealing organic film 37, the second sealing inorganic insulating film 38).

After that, a protective sheet (not shown) is stuck on the surface of the substrate on which the sealing film 39 is formed, and then laser light is irradiated from the glass substrate side of the resin substrate layer 10 to peel the glass substrate from the lower surface of the resin substrate layer 10, and further the protective sheet (not shown) is stuck on the lower surface of the resin substrate layer 10 from which the glass substrate is peeled.

As described above, the organic EL display device 50 of the present embodiment can be manufactured.

In addition, although the organic EL display device 50 including the TFT layer 30a and the method for manufacturing the same are illustrated in this embodiment, an organic EL display device including the TFT layer 30b instead of the TFT layer 30a and the method for manufacturing the same may be used. Here, fig. 17 and 18 are cross-sectional views of the TFT layer 30b constituting a modification of the organic EL display device 50 of the present embodiment, and correspond to fig. 6 and 7.

In the TFT layer 30a of the present embodiment, the semiconductor layer 12ad and the like are formed of low-temperature polysilicon, but in the TFT layer 30b of the modified example, the semiconductor layer 12bd and the like are formed of an oxide semiconductor. Therefore, in the TFT layer 30b, the sectional shape of the gate insulating film 13b underlying the semiconductor layer 12bd of the TFTs 9a to 9g is different from that of the TFT layer 30a only in the first interlayer insulating film 17b, the capacitor electrode 18cb, and the second interlayer insulating film 19b, and the other structure is substantially the same as that of the TFT layer 30 a.

As shown in fig. 17, when the description is made by taking the driving TFT9d as a representative, the driving TFT9d includes a semiconductor layer 12bd, a gate insulating film 13b, a gate electrode 16b, a first interlayer insulating film 17b, a second interlayer insulating film 19b, and a first terminal 20a (see fig. 3) and a second terminal 20b (see fig. 3) which are provided in this order on the base film 11. Here, the semiconductor layer 12bd is provided in a substantially H-shape on the base film 11, similarly to the semiconductor layer 12 ad. The semiconductor layer 12bd includes an intrinsic region 12bc provided so as to overlap with the gate electrode 16b in plan view, and a pair of conductor regions 12ba and 12bb provided so as to sandwich the intrinsic region 12bc, similarly to the semiconductor layer 12 ad. In addition, the intermediate portion of the intrinsic region 12bc is provided in a substantially V-shape in plan view, similarly to the intrinsic region 12 ac. As shown in fig. 17 and 18, the gate insulating film 13b is provided in an island shape so as to match the gate electrode 16b, the emission control line 16e, and the gate line 16 g. As shown in fig. 17, the gate electrode 16b is provided on the gate insulating film 13b in an island shape having a rectangular shape in a plan view so as to overlap the intrinsic region 12bc of the semiconductor layer 12 bd. As shown in fig. 17, the gate electrode 16b includes a first metal layer 14b provided on the gate insulating film 13b and a second metal layer 15b provided on the first metal layer 14 b. The first metal layer 14b and the second metal layer 15b are made of the same refractory metal such as tungsten, tantalum, molybdenum, niobium, titanium, and molybdenum nitride. In addition, the intrinsic region 12bc of the semiconductor layer 12bd is provided so as to match the first metal layer 14b of the gate electrode 16 b. As shown in fig. 17 and 18, the first interlayer insulating film 17b is provided so as to cover the gate electrode 16b, the emission control line 16e, and the gate line 16 g. As shown in fig. 17 and 18, the second interlayer insulating film 19b is provided on the first interlayer insulating film 17b via the capacitor electrode 18 cb.

The organic EL display device including the TFT layer 30b can be manufactured as follows. Here, fig. 19, 20, and 21 are sectional views showing the second photolithography step, the second etching step, and the conductor forming step in the manufacturing method of the modified example of the organic EL display device according to the present embodiment, respectively, and correspond to fig. 17.

First, in the semiconductor layer forming step of the method for manufacturing the organic EL display device 50, an oxide semiconductor film (having a thickness of about 30nm to 100 nm) such as InGaZO4 is formed by a sputtering method over the entire substrate on which the base film 11 is formed, and then the oxide semiconductor film is subjected to photolithography, etching, and resist stripping to form the semiconductor layer 12b (see fig. 19).

Thereafter, as shown in fig. 19, after the gate insulating film forming step, the first metal film forming step, the first photolithography step, the first etching step, the first peeling step, and the second metal film forming step of the method for manufacturing the organic EL display device 50 are sequentially performed, the resist R is applied to the second metal film 15, and then the resist R is exposed through the second mask M to form the second resist pattern Rbb (second photolithography step).

Further, the second metal film 15 exposed from the second resist pattern Rbb, the first metal layer 14a formed in the first etching step, and the gate insulating film 13 are etched, and as shown in fig. 20, a gate layer including the gate electrode 16b and the like in which the first metal layer 14b and the second metal layer 15b are stacked and a gate insulating film 13b are formed (second etching step).

Thereafter, the second resist pattern Rbb used in the second etching step is peeled off (second peeling step).

Next, plasma treatment such as hydrogen plasma treatment or helium plasma treatment is performed on the semiconductor layer using the gate electrode 16b or the like as a mask, whereby a part of the semiconductor layer is made conductive as shown in fig. 21, and the semiconductor layer 12bd having the conductor region 12ba, the conductor region 12bb, and the intrinsic region 12bc is formed (a conductive step). In the present modification, the manufacturing method in which the conductor forming step is performed after the second peeling step is exemplified, but the conductor forming step may be performed before the second peeling step.

After that, in the same manner as the method for manufacturing the organic EL display device 50, the first interlayer insulating film 17b, the capacitor electrode 18cb, the initialization power supply line 18i, the connection wiring 20e, the source line 20f, the power supply line 20g, the planarization film 21, and the like are formed to form the TFT layer 30b, and the organic EL display device including the TFT layer 30b can be manufactured by performing the organic light emitting element layer forming step.

As described above, according to the organic EL display device 50 and the method of manufacturing the same of the present embodiment, the first metal layers 14a, 14e, and 14g formed by the first metal film forming step, the first photolithography step, and the first etching step and the second metal layers 15a, 15e, and 15g formed by the second metal film forming step, the second photolithography step, and the second etching step are stacked on the gate insulating film 13, and the gate electrode 16a including the TFT layer 30a, the emission control line 16e, and the gate layer including the gate line 16g are formed.

In addition, according to the organic EL display device 50 and the method of manufacturing the same of the present embodiment, in the second etching step, since the residue of the first metal film 14 remaining in the first etching step can be removed, for example, the inter-wiring leakage between the gate electrode 16a and the gate line 16g and the emission control line 16e with a narrow interval can be suppressed.

Second embodiment

Fig. 22 to 28 show a second embodiment of the display device and the method for manufacturing the same according to the present invention. Here, fig. 22 is a plan view of the TFT layer 30c constituting the organic EL display device according to the present embodiment. In addition, fig. 23 is a sectional view of the TFT layer 30c along the line XXIII-XXIII in fig. 22. In the following embodiments, the same portions as those in fig. 1 to 21 are assigned the same reference numerals, and detailed description thereof is omitted.

In the first embodiment, the organic EL display device 50 and the method of manufacturing the same are exemplified in which the conductor forming step is performed after the second etching step, but in the present embodiment, the organic EL display device and the method of manufacturing the same are exemplified in which the conductor forming step is performed before the second metal film forming step.

Like the organic EL display device 50 of the first embodiment, the organic EL display device of the present embodiment includes a display region D and a frame region F provided around the display region D. In addition, the organic EL display device of the present embodiment includes the resin substrate layer 10, the TFT layer 30c provided on the resin substrate layer 10, and the organic EL element layer 40 provided on the TFT layer 30c, similarly to the organic EL display device 50 of the first embodiment described above.

The TFT layer 30c includes, similarly to the TFT layer 30a of the organic EL display device 50 of the first embodiment, the following: a base film 11 provided on the resin substrate layer 10, a first initialization TFT9a provided on the base film 11 corresponding to each sub-pixel P, a threshold voltage compensation TFT9b, a write control TFT9c, a driving TFT9d, a power supply TFT9e, a light emission control TFT9f, a second initialization TFT9g, and a capacitor 9 h; a planarization film 21 provided on the TFTs 9a to 9g and the capacitor 9 h.

As shown in fig. 23, the driving TFT9d includes a semiconductor layer 12cd, a gate insulating film 13, a gate electrode 16c, a first interlayer insulating film 17, a second interlayer insulating film 19, and a first terminal 20a (see fig. 3) and a second terminal 20b (see fig. 3) which are provided in this order on a base film 11. Here, the semiconductor layer 12cd is formed of low-temperature polysilicon, and is provided in a substantially H-shape on the base film 11 as shown in fig. 22 and 23. As shown in fig. 23, the semiconductor layer 12cd includes an intrinsic region 12cc provided so as to overlap with the gate electrode 16c in a plan view, and a pair of conductor regions 12ca and 12cb provided so as to sandwich the intrinsic region 12 cc. As shown in fig. 22, the middle portion of the intrinsic region 12cc is formed in a substantially V-shape in plan view. As shown in fig. 22 and 23, an offset region Y is provided on the pair of conductor regions 12ca and 12cb side of the intrinsic region 12cc so as not to overlap with the first metal layer 14c and the second metal layer 15c, which will be described later. In addition, as shown in fig. 23, the gate insulating film 13 is provided so as to cover the semiconductor layer 12 cd. Further, on the surface of the gate insulating film 13 exposed from the gate electrode 16a, along the peripheral end of the gate electrode 16c, there is a two-step level difference S formed by the first etching step and the second etching step. Further, the boundaries of the pair of conductor regions 12ca, 12cb and the intrinsic region 12cc are set so as to be aligned with the step S formed on the surface of the gate insulating film 13. As shown in fig. 22 and 23, the gate electrode 16c is provided in an island shape having a rectangular shape in a plan view on the gate insulating film 13 so as to overlap the intrinsic region 12cc of the semiconductor layer 12 cd. In addition, as shown in fig. 23, the gate electrode 16c includes a first metal layer 14c provided on the gate insulating film 13 and a second metal layer 15c provided on the first metal layer 14 c. As shown in fig. 22 and 23, the length of the second metal layer 15c is equal to or less than the length of the first metal layer 14c in the direction L (lateral direction in fig. 22) of the channel length of the intrinsic region 12cc of the semiconductor layer 12cd and the direction orthogonal thereto (longitudinal direction in fig. 22). The first metal layer 14c and the second metal layer 15c are made of the same refractory metal such as tungsten, tantalum, molybdenum, niobium, titanium, and molybdenum nitride. Also, the intrinsic region 12cc of the semiconductor layer 12cd is provided to match the first metal layer 14a which becomes the first metal layer 14 c. In addition, as shown in fig. 23, the first interlayer insulating film 17 is provided so as to cover the gate electrode 16c, the emission control line 16e, and the gate line 16 g. In addition, as shown in fig. 23, the second interlayer insulating film 19 is provided on the first interlayer insulating film 17 via the capacitance electrode 18 c. The first terminal 20a and the second terminal 20b are electrically connected to the pair of conductor regions 12ca and 12cb of the semiconductor layer 12cd, respectively, via contact holes formed in the laminated film of the gate insulating film 13, the first interlayer insulating film 17, and the second interlayer insulating film 19.

The first initialization TFT9a, the threshold voltage compensation TFT9b, the write control TFT9c, the power supply TFT9e, the emission control TFT9f, and the second initialization TFT9g have the same configuration as the driving TFT9d described above, except that the capacitor electrode 18c is not interposed.

The organic EL display device having the TFT layer 30c with the above-described structure is flexible, and each sub-pixel P is configured such that, similarly to the organic EL display device 50 of the first embodiment: the light-emitting layer 3 of the organic EL layer 33 is caused to emit light appropriately through the first initialization TFT9a, the threshold voltage compensation TFT9b, the write control TFT9c, the driving TFT9d, the power supply TFT9e, the light-emission control TFT9f, and the second initialization TFT9g, thereby displaying an image.

Next, a method for manufacturing an organic EL display device having the TFT layer 30c of the present embodiment will be described. In addition, the method for manufacturing an organic EL display device of the present embodiment includes: a TFT layer forming step of sequentially performing a semiconductor layer forming step, a gate insulating film forming step, a first metal film forming step, a first photolithography step, a first etching step, a first peeling step, a conductor forming step, a second metal film forming step, a second photolithography step, a second etching step, and a second peeling step; and an organic EL element layer forming step. Fig. 24, 25, 26, and 27 are sectional views showing the conductor forming step, the second metal film forming step, the second photolithography step, and the second etching step in the method for manufacturing an organic EL display device according to the present embodiment, respectively, and correspond to fig. 23.

First, after the first lift-off step of the method for manufacturing the organic EL display device 50 described in the first embodiment, impurity ions are doped into the semiconductor layer 12a and the like using the first metal layer 14a as a mask, so that a part of the semiconductor layer 12a and the like is made conductive as shown in fig. 24, and the semiconductor layer 12cd and the like having the conductor region 12ca, the conductor region 12cb, and the intrinsic region 12cc are formed (a conductive step). In addition, although the manufacturing method in which the conductor forming step is performed after the first peeling step is exemplified in the present embodiment, the conductor forming step may be performed before the first peeling step.

Next, for example, a molybdenum film (having a thickness of about 125 nm) is formed by sputtering so as to cover the first metal layer 14a and the like, and a second metal film 15 is formed as shown in fig. 25 (second metal film forming step).

After that, after a resist R is applied to the second metal film 15, the resist R (two-dot chain line in fig. 26) is exposed through a second mask M to form a second resist pattern Rbc as shown in fig. 26 (second photolithography step). Here, by setting the exposure amount in the second photolithography step to be larger than the exposure amount in the first photolithography step, a common mask to the first mask M can be used for the second mask M. In addition, in the direction L of the channel length of the semiconductor layer 12cd, the length of the second resist pattern Rbc is shorter than the length of the first resist pattern Ra.

Further, the second metal film 15 exposed from the second resist pattern Rbc is etched to form a second metal layer 15c and the like, and a gate layer including the gate electrode 16c and the like in which the first metal layer 14c and the second metal layer 15c are stacked is formed, as shown in fig. 27 (second etching step). Here, in the second etching step, since the surface layer of the gate insulating film 13 underlying the second metal film 14 is also etched again, a step S of two steps is formed on the surface of the gate insulating film 13 as shown in fig. 27.

After the second resist pattern Rbc used in the second etching step is peeled off (second peeling step), the first interlayer insulating film 17, the capacitor electrode 18c, the initialization power supply line 18i, the connection wiring 20e, the source line 20f, the power supply line 20g, the planarization film 21, and the like are formed to form the TFT layer 30c, and then the organic EL element layer forming step is performed, whereby an organic EL display device including the TFT layer 30c can be manufactured.

Although the organic EL display device having the TFT layer 30c and the method for manufacturing the same are illustrated in this embodiment, the organic EL display device having the TFT layer 30d instead of the TFT layer 30c and the method for manufacturing the same may be used. Here, fig. 28 is a cross-sectional view of a TFT layer 30d constituting a modification of the organic EL display device of the present embodiment, and corresponds to fig. 23.

In the TFT layer 30c of the present embodiment, the semiconductor layer 12cd and the like are formed of low-temperature polysilicon, but in the TFT layer 30d of the modified example, the semiconductor layer 12dd and the like are formed of an oxide semiconductor. Therefore, in the TFT layer 30d, the structure is substantially the same as that of the TFT layer 30c except that the sectional shape of the gate insulating film 13d underlying the semiconductor layer 12dd of the TFTs 9a to 9g is different from that of the TFT layer 30c only in the first interlayer insulating film 17b, the capacitor electrode 18cb, and the second interlayer insulating film 19 b.

As shown in fig. 28, when the description is made by taking the driving TFT9d as a representative, the driving TFT9d includes a semiconductor layer 12bd, a gate insulating film 13b, a gate electrode 16b, a first interlayer insulating film 17b, a second interlayer insulating film 19b, and a first terminal 20a (see fig. 3) and a second terminal 20b (see fig. 3) which are provided in this order on the base film 11. Here, the semiconductor layer 12dd is provided in a substantially H-shape on the base film 11, similarly to the semiconductor layer 12 cd. As shown in fig. 28, the semiconductor layer 12dd includes an intrinsic region 12dc provided so as to overlap with the gate electrode 16b in plan view, and a pair of conductor regions 12da and 12db provided so as to sandwich the intrinsic region 12dc, similarly to the semiconductor layer 12 cd. In addition, the intermediate portion of the intrinsic region 12dc is formed in a substantially V-shape in plan view, similarly to the intrinsic region 12 cc. As shown in fig. 28, an offset region Y is provided on the pair of conductor regions 12da and 12db of the intrinsic region 12dc so as not to overlap with the first metal layer 14d and the second metal layer 15d, which will be described later. As shown in fig. 28, the gate insulating film 13d is provided in an island shape so as to match the gate electrode 16d, the emission control line 16e, and the gate line 16 g. Further, boundaries between the pair of conductor regions 12da, 12db and the intrinsic region 12dc are provided so as to be aligned with end portions of the gate insulating film 13 d. As shown in fig. 28, the gate electrode 16d is provided in an island shape having a rectangular shape in plan view so as to overlap the intrinsic region 12dc of the semiconductor layer 12dd on the gate insulating film 13. As shown in fig. 28, the gate electrode 16d includes a first metal layer 14d provided on the gate insulating film 13d and a second metal layer 15d provided on the first metal layer 14 d. The first metal layer 14d and the second metal layer 15d are made of the same refractory metal such as tungsten, tantalum, molybdenum, niobium, titanium, and molybdenum nitride. In addition, as shown in fig. 28, the first interlayer insulating film 17b is provided so as to cover the gate electrode 16d, the emission control line 16e, and the gate line 16 g. In addition, as shown in fig. 28, a second interlayer insulating film 19b is provided on the first interlayer insulating film 17b via the capacitance electrode 18 cb.

The organic EL display device including the TFT layer 30d can be manufactured by combining the manufacturing method of the present embodiment and the manufacturing method of the modified example of the first embodiment.

As described above, according to the organic EL display device and the method of manufacturing the same of the present embodiment, the first metal layer 14a formed by the first metal film forming step, the first photolithography step, and the first etching step and the second metal layer 15a formed by the second metal film forming step, the second photolithography step, and the second etching step are stacked on the gate insulating film 13, and the gate layer including the gate electrode 16c of the TFT layer 30c is formed. Here, since the thickness of the first metal film 14 formed in the first metal film forming step is half of the total thickness of the first metal film 14 and the second metal film 15, the stress generated in the first metal film 14 can be relaxed as compared with the case where the first metal film 14 and the second metal film 15 are formed together. Further, since the thickness of the second metal film 15 formed in the second metal film forming step is half of the total thickness of the first metal film 14 and the second metal film 15, the stress generated in the second metal film 15 can be relaxed as compared with the case where the first metal film 14 and the second metal film 15 are formed together. Thus, even if the total thickness of the first metal film 14 and the second metal film 15 is increased in order to reduce the wiring resistance of the gate layer including the gate electrode 16c, the stress generated in the first metal film 14 and the second metal film 15 is relaxed, and therefore, the generation of cracks in the gate insulating film 13 underlying the stress is suppressed. Therefore, the generation of cracks in the gate insulating film 13 can be suppressed, and the wiring resistance of the gate layer including the gate electrode 16c can be reduced.

In addition, according to the organic EL display device and the method of manufacturing the same of the present embodiment, since the residue of the first metal film 14 remaining in the first etching step can be removed in the second etching step, it is possible to suppress, for example, the inter-wiring leakage between the gate electrode 16c and the gate line 16g, and the emission control line 16e with a narrow interval.

In addition, according to the organic EL display device and the method of manufacturing the same of the present embodiment, since the TFTs 9a to 9g having the offset region Y are provided, the S value (the rising coefficient of the subthreshold region) of the TFTs 9a to 9g can be increased or the leak current can be reduced.

Third embodiment

Fig. 29 to 32 show a display device and a method of manufacturing the same according to a third embodiment of the present invention. Here, fig. 29 is a plan view of a TFT layer 30e constituting an organic EL display device according to a third embodiment of the present invention. In addition, fig. 30 is a sectional view of the TFT layer 30e along the line XXX-XXX in fig. 29.

In the first and second embodiments, the organic EL display device including the TFT layers 30a to 30d provided so that the side surface of the second metal layer is aligned with the side surface of the first metal layer in the gate electrode of the TFT is exemplified, but in the present embodiment, the organic EL display device including the TFT layer 30e in which a part of the second metal layer 15ae is provided so as to protrude from the end portion of the first metal layer 14ae in the gate electrode of the TFT is exemplified.

Like the organic EL display device 50 of the first embodiment, the organic EL display device of the present embodiment includes a display region D and a frame region F provided around the display region D. In addition, the organic EL display device of the present embodiment includes a resin substrate layer 10, a TFT layer 30e provided on the resin substrate layer 10, and an organic EL element layer 40 provided on the TFT layer 30e, as in the organic EL display device 50 of the first embodiment described above.

The TFT layer 30e includes, as with the TFT layer 30a of the organic EL display device 50 of the first embodiment described above, a base film 11 provided on the resin substrate layer 10, a first initialization TFT9a provided on the base film 11 for each sub-pixel P, a threshold voltage compensation TFT9b, a write control TFT9c, a driving TFT9d, a power supply TFT9e, a light emission control TFT9f, a second initialization TFT9g, and a capacitor 9h, and a planarization film 21 provided on each of the TFTs 9a to 9g and the capacitor 9 h.

As shown in fig. 30, the driving TFT9d includes a semiconductor layer 12cd, a gate insulating film 13, a gate electrode 16ae, a first interlayer insulating film 17e, a second interlayer insulating film 19e, and a first terminal 20a (see fig. 3) and a second terminal 20b (see fig. 3) which are provided in this order on a base film 11. Here, the semiconductor layer 12cd is formed of low-temperature polysilicon, and is provided in a substantially H-shape on the base film 11 as shown in fig. 29 and 30. As shown in fig. 30, the semiconductor layer 12cd includes an intrinsic region 12cc provided so as to overlap with the gate electrode 16c in a plan view, and a pair of conductor regions 12ca and 12cb provided so as to sandwich the intrinsic region 12 cc. As shown in fig. 29, the middle portion of the intrinsic region 12cc is formed in a substantially V-shape in plan view. In addition, as shown in fig. 30, the gate insulating film 13 is provided so as to cover the semiconductor layer 12 cd. In addition, as shown in fig. 30, the boundaries of the pair of conductor regions 12ca, 12cb and the intrinsic region 12cc are disposed so as to be aligned with the end portions of the first metal layer 14ae of the gate electrode 16 ae. As shown in fig. 29 and 31, the gate electrode 16ae is provided in an island shape having a rectangular shape in a plan view on the gate insulating film 13 so as to overlap the intrinsic region 12cc of the semiconductor layer 12 cd. In addition, as shown in fig. 30, the gate electrode 16ae includes a first metal layer 14ae provided on the gate insulating film 13 and a second metal layer 15ae provided on the first metal layer 14 ae. In addition, as shown in fig. 29 and 30, in the portion of the gate electrode 16ae overlapping the intrinsic region 12cc, the second metal layer 15ae is provided so as to protrude from both end portions of the first metal layer 14ae and cover the first metal layer 14ae in the direction L of the channel length of the semiconductor layer 12 cd. As shown in fig. 29, the portion a of the gate electrode 16ae which does not overlap with the semiconductor layer 12cd is set so that the width of the second metal layer 15ae is equal to or less than the width of the first metal layer 14 a. As shown in fig. 29, the portion a of the light emission control line 16ee which does not overlap with the semiconductor layer 12cd is set so that the width of the second metal layer 15ee is equal to or less than the width of the first metal layer 14 e. In addition, as shown in fig. 29, a portion a of the gate line 16ge which does not overlap with the semiconductor layer 12cd is set so that the width of the second metal layer 15ge is equal to or less than the width of the first metal layer 14 g. The first metal layer 14ae and the second metal layer 15ae are made of, for example, the same refractory metal such as tungsten, tantalum, molybdenum, niobium, titanium, or molybdenum nitride. Also, the intrinsic region 12cc of the semiconductor layer 12cd is set to match the first metal layer 14 ae. In addition, as shown in fig. 30, the first interlayer insulating film 17 is provided so as to cover the gate electrode 16ae, the emission control line 16ee, and the gate line 16 ge. In addition, as shown in fig. 30, a second interlayer insulating film 19e is provided on the first interlayer insulating film 17e via the capacitance electrode 18 c. The first terminal 20a and the second terminal 20b are electrically connected to the pair of conductor regions 12ca and 12cb of the semiconductor layer 12cd, respectively, via contact holes formed in the laminated film of the gate insulating film 13, the first interlayer insulating film 17e, and the second interlayer insulating film 19 e.

The first initialization TFT9a, the threshold voltage compensation TFT9b, the write control TFT9c, the power supply TFT9e, the emission control TFT9f, and the second initialization TFT9g have the same configuration as the driving TFT9d described above, except that the capacitor electrode 18c is not interposed.

The organic EL display device having the TFT layer 30e with the above-described structure is flexible, and is configured to display an image by appropriately emitting light from the light-emitting layer 3 of the organic EL layer 33 through the first initializing TFT9a, the threshold voltage compensating TFT9b, the write controlling TFT9c, the driving TFT9d, the power supplying TFT9e, the light-emission controlling TFT9f, and the second initializing TFT9g in each sub-pixel P, similarly to the organic EL display device 50 of the first embodiment.

Next, a method for manufacturing an organic EL display device having the TFT layer 30e of the present embodiment will be described. In addition, the method for manufacturing an organic EL display device of the present embodiment includes: the method includes a TFT layer forming step and an organic EL element layer forming step, which are performed in this order by a semiconductor layer forming step, a gate insulating film forming step, a first metal film forming step, a first photolithography step, a first etching step, a first peeling step, a conductor forming step, a second metal film forming step, a second photolithography step, a second etching step, and a second peeling step. Here, fig. 31 and 32 are sectional views showing a second photolithography step and a second etching step in the method for manufacturing an organic EL display device according to the present embodiment, respectively, and correspond to fig. 30.

First, after the first lift-off step of the method for manufacturing the organic EL display device 50 described in the first embodiment, impurity ions are doped into the semiconductor layer 12a and the like using the first metal layer 14a as a mask, so that a part of the semiconductor layer 12a and the like is made conductive as shown in fig. 24, and the semiconductor layer 12cd and the like having the conductor region 12ca, the conductor region 12cb, and the intrinsic region 12cc are formed (a conductive step). In addition, although the manufacturing method in which the conductor forming step is performed after the first peeling step is exemplified in the present embodiment, the conductor forming step may be performed before the first peeling step.

Next, for example, a molybdenum film (having a thickness of about 125 nm) is formed by sputtering so as to cover the first metal layer 14a and the like, and a second metal film 15 is formed as shown in fig. 25 (second metal film forming step).

After that, a resist R is applied to the second metal film 15 (two-dot chain line in fig. 31), and then, as shown in fig. 31, the resist R is exposed through a second mask M to form a second resist pattern Rbe (second photolithography step). Here, in the second photolithography step, the second resist pattern Rbe is formed so as to protrude from both end portions of the first metal layer 14a in the direction L of the channel length of the semiconductor layer 12 cd.

Further, the second metal film 15 exposed from the second resist pattern Rbe is etched to form the second metal layers 15ae, 15ee, and 15gef, and a gate layer including the gate electrode 16ae, the light-emission control line 16ee, and the gate line 16ge, in which the first metal layers 14a, 14e, and 14g, and the second metal layers 15ae, 15ee, and 15ge are stacked, respectively, as shown in fig. 32 (second etching step). Here, in the second etching step, the second metal layer 15ae is formed so as to cover both end portions of the first metal layer 14ae and between both end portions thereof in the direction L of the channel length of the semiconductor layer 12 cd. In the second etching step, the surface layer of the gate insulating film 13 underlying the second metal film 14 is also etched again, so that a step S of two levels is formed on the surface of the gate insulating film 13 as shown in fig. 32.

After the second resist pattern Rbe used in the second etching step is removed (second removal step), the first interlayer insulating film 17, the capacitor electrode 18c, the initialization power supply line 18i, the connection wiring 20e, the source line 20f, the power supply line 20g, the planarization film 21, and the like are formed to form the TFT layer 30e, and then the organic EL element layer forming step is performed, whereby an organic EL display device including the TFT layer 30e can be manufactured.

As described above, according to the organic EL display device and the method of manufacturing the same of the present embodiment, the first metal layer 14ae formed by the first metal film formation step, the first photolithography step, and the first etching step and the second metal layer 15ae formed by the second metal film formation step, the second photolithography step, and the second etching step are stacked on the gate insulating film 13, and the gate layer including the gate electrode 16ae of the TFT layer 30e is formed. Here, since the thickness of the first metal film 14 formed in the first metal film forming step is half of the total thickness of the first metal film 14 and the second metal film 15, the stress generated in the first metal film 14 can be relaxed as compared with the case where the first metal film 14 and the second metal film 15 are formed together. Further, since the thickness of the second metal film 15 formed in the second metal film forming step is half of the total thickness of the first metal film 14 and the second metal film 15, the stress generated in the second metal film 15 can be relaxed as compared with the case where the first metal film 14 and the second metal film 15 are formed together. Thus, even if the total thickness of the first metal film 14 and the second metal film 15 is increased in order to reduce the wiring resistance of the gate layer including the gate electrode 16ae, the stress generated in the first metal film 14 and the second metal film 15 is relaxed, and therefore, the generation of cracks in the gate insulating film 13 underlying the stress is suppressed. Therefore, generation of cracks in the gate insulating film 13 can be suppressed, and the wiring resistance of the gate layer including the gate electrode 16ae can be reduced.

In addition, according to the organic EL display device and the method of manufacturing the same of the present embodiment, in the second etching step, since the residue of the first metal film 14 remaining in the first etching step can be removed, it is possible to suppress, for example, inter-wiring leakage between the gate electrode 16ae and the gate line 16ge and the emission control line 16ee at narrow intervals.

In addition, according to the organic EL display device and the method of manufacturing the same of the present embodiment, the boundary between the pair of conductor regions 12ca, 12cb and the intrinsic region 12cc is provided so as to be aligned with the end portion of the first metal layer 14a of the gate electrode 16ae, and the second metal layer 15ae of the gate electrode 16ae is provided so as to protrude from both end portions of the first metal layer 14a in the direction L of the channel length of the semiconductor layer 12cd and cover the first metal layer 14a, so that TFTs 9a to 9g having no offset region Y can be formed.

In addition, although the structure in which the semiconductor layer is formed of low-temperature polysilicon is described as an example in this embodiment, the present invention can also be applied to a case in which the semiconductor layer is formed of an oxide semiconductor layer. In this case, the gate insulating film is not aligned with the end portion of the gate electrode, and the entire surface of the contact hole or the like provided on the underlying layer or the semiconductor layer is removed, as in the case where the semiconductor layer is formed of low-temperature polysilicon. Here, the conductor formation process is performed through the gate insulating film. The step formed on the gate insulating film, and the shape of the intrinsic region and the conductor region of the semiconductor layer are the same as those in the case where the semiconductor layer is formed of low-temperature polysilicon.

Fourth embodiment

Fig. 33 shows a fourth embodiment of the display device and the method for manufacturing the same according to the present invention. Here, fig. 33 is a plan view of the TFT layer 30f constituting the organic EL display device of the present embodiment.

In the second embodiment, the organic EL display device having the TFT layer 30c provided with the TFTs 9a to 9g having the offset region Y is exemplified; although the third embodiment has exemplified the organic EL display device having the TFT layer 30e provided with the TFTs 9a to 9g having no offset region Y in the TFT layer 30e, the present embodiment exemplifies the organic EL display device having the TFT layer 30f obtained by combining the TFTs 9a, 9b, and 9d having the offset region Y and the TFTs 9c, 9e, 9f, and 9g having no offset region Y.

Specifically, if the TFT having the offset region Y is used as the first TFT and the TFT having no offset region Y is used as the second TFT, as shown in fig. 33, the organic EL display device may be provided with a TFT layer 30f in which a first initialization TFT9a (not shown), a threshold voltage compensation TFT9b, and a driving TFT9d are provided as the first TFT, and a write control TFT9c, a power supply TFT9e, a light emission control TFT9f, and a second initialization TFT9g (not shown) are provided as the second TFT.

Here, in the first semiconductor layer having the first intrinsic region and the pair of first conductor regions, and the first TFT (9a, 9b, and 9d) having the first gate layer, as shown in fig. 23, the offset region Y is provided on the first conductor region 12ca and 12cb side of the pair of first intrinsic regions 12cc so as not to overlap with the first metal layer 14a and the second metal layer 15a, the boundaries of the pair of first conductor regions 12ca and 12cb and the first intrinsic region 12cc are provided so as to be aligned with the step S formed on the surface of the gate insulating film 13, and the length of the second metal layer 15a is equal to or less than the length of the first metal layer 14a in the direction L of the channel length of the first semiconductor layer 12 cd.

In addition, in the second TFTs (9c, 9e, 9f, and 9g) including the second semiconductor layer having the second intrinsic region and the pair of second conductor regions and the second gate layer, as shown in fig. 33 (see fig. 30), the boundaries of the pair of second conductor regions 12ca, 12cb and the second intrinsic region 12cc are provided in alignment with the end portions of the first metal layers 14e and 14g, and on the second gate layer (the light emission control line 16ee and the gate line 16gf) overlapping with the second intrinsic region 12cc, the second metal layers 15ee and 15gf are provided so as to protrude from both end portions of the first metal layers 14e and 14g and cover the first metal layers 14e and 14g in the direction L of the channel length of the second semiconductor layer 12 cd. As shown in fig. 33, the portions of the second gate layer (the light emission control line 16ee and the gate line 16gf) that do not overlap the second intrinsic region 12cc are set so that the widths of the second metal layers 15ee and 15gf are equal to or less than the widths of the first metal layers 14e and 14 g.

In this embodiment, although the structure in which the semiconductor layer is formed of low-temperature polysilicon is illustrated, the semiconductor layer may be formed of an oxide semiconductor layer.

Other embodiments

In each of the above embodiments, the organic EL layer having a 5-layer laminated structure of the hole injection layer, the hole transport layer, the light emitting layer, the electron transport layer, and the electron injection layer is exemplified, but the organic EL layer may have a 3-layer laminated structure of the hole injection layer/hole transport layer, the light emitting layer, and the electron transport layer/electron injection layer, for example.

In addition, although the organic EL display device in which the first electrode is an anode and the second electrode is a cathode has been illustrated in the above embodiments, the present invention can also be applied to an organic EL display device in which the laminated structure of organic EL layers is reversed, and the first electrode is a cathode and the second electrode is an anode.

In addition, although the organic EL display device including the top gate TFT is illustrated in each of the above embodiments, the present invention is also applicable to an organic EL display device including a bottom gate TFT.

In addition, although the organic EL display device 50 including the sealing film 39 in which the sealing organic film 37 is provided between the first inorganic sealing insulating film 36 and the second inorganic sealing insulating film 38 has been illustrated in the above embodiments, the present invention is an organic EL display device in which an organic vapor-deposited film is formed between the first inorganic sealing insulating film 36 and the second inorganic sealing insulating film 38, and then the organic vapor-deposited film is ashed to cover foreign matter with the organic vapor-deposited film. According to the structure of the sealing film, even if foreign matter exists in the display region, the sealing performance can be ensured by the second sealing inorganic insulating film, and the reliability can be improved.

In addition, in each of the above embodiments, the organic EL display device is exemplified as the display device, but the present invention is not limited to the organic EL display device and can be applied to any flexible display device. For example, the present invention can be applied to a flexible display device having a QLED or the like, which is a light-emitting element using a quantum dot-containing layer.

Industrial applicability

As described above, the present invention is useful for a flexible display device.