阅读说明：本技术 基于开关控制的采样电路 (Sampling circuit based on switch control ) 是由 程龙 于 2020-12-09 设计创作，主要内容包括：本发明揭示了一种基于开关控制的采样电路,所述采样电路包括：运算放大器AMP,包括输入端和输出端；采样电容,与运算放大器AMP的输入端相连；反馈电容,电性连接于运算放大器AMP的输入端和输出端之间；第一开关,电性连接于信号输入端Vin和采样电容之间；第二开关,电性连接于运算放大器AMP的输入端之间；第三开关及第四开关,分别电性连接于Vcm驱动电路和第二开关之间；其中,所述第二开关、第三开关及第四开关为NMOS管,且满足Vth2＞Vth3、Vth2＞Vth4,Vth2、Vth3、Vth4分别为第二开关、第三开关和第四开关的阈值电压。本发明通过控制NMOS管开关的阈值,可以将第二开关产生的误差量通过第三开关和第四开关提前释放到Vcm驱动电路中,可有效提高采样电路的采样精度。(The invention discloses a sampling circuit based on switch control, which comprises: an operational Amplifier (AMP) including an input terminal and an output terminal; the sampling capacitor is connected with the input end of the operational amplifier AMP; the feedback capacitor is electrically connected between the input end and the output end of the operational amplifier AMP; the first switch is electrically connected between the signal input end Vin and the sampling capacitor; the second switch is electrically connected between the input ends of the operational amplifier AMP; the third switch and the fourth switch are respectively and electrically connected between the Vcm driving circuit and the second switch; the second switch, the third switch and the fourth switch are NMOS transistors, and the threshold voltages of the second switch, the third switch and the fourth switch are respectively Vth2 > Vth3, Vth2 > Vth4, Vth2, Vth3 and Vth 4. According to the invention, by controlling the threshold value of the NMOS tube switch, the error generated by the second switch can be released to the Vcm driving circuit in advance through the third switch and the fourth switch, and the sampling precision of the sampling circuit can be effectively improved.)

1. A sampling circuit based on switch control, the sampling circuit comprising:

an operational Amplifier (AMP) including an input terminal and an output terminal;

the sampling capacitor is connected with the input end of the operational amplifier AMP;

the feedback capacitor is electrically connected between the input end and the output end of the operational amplifier AMP;

the first switch is electrically connected between the signal input end Vin and the sampling capacitor;

the second switch is electrically connected between the input ends of the operational amplifier AMP;

the third switch and the fourth switch are respectively and electrically connected between the Vcm driving circuit and the second switch;

the second switch, the third switch and the fourth switch are NMOS transistors, and the threshold voltages of the second switch, the third switch and the fourth switch are respectively Vth2 > Vth3, Vth2 > Vth4, Vth2, Vth3 and Vth 4.

2. The sampling circuit based on the switch control of claim 1, wherein the operational amplifier comprises a first input terminal and a second input terminal, the sampling capacitor comprises a first sampling capacitor Cs1 connected to the first input terminal and a second sampling capacitor Cs2 connected to the second input terminal, and the feedback capacitor comprises a first feedback capacitor Cf1 electrically connected between the first input terminal and the output terminal and a second feedback capacitor Cf2 electrically connected between the second input terminal and the output terminal.

3. The switching control based sampling circuit of claim 2, wherein the first switch comprises a first switch S1 electrically connected between the signal input terminal Vin and a first sampling capacitor Cs1 and a first switch S1' electrically connected between the signal input terminal Vin and a second sampling capacitor Cs 2.

4. The sampling circuit based on the switch control as claimed in claim 2, wherein the first sampling capacitor Cs1 and the second sampling capacitor Cs2 are the same, and the first feedback capacitor Cf1 and the second feedback capacitor Cf2 are the same.

5. The sampling circuit based on the switch control as claimed in claim 2, wherein the first sampling capacitor Cs1 and the second sampling capacitor Cs2 are bottom plate sampling capacitors, and the bottom plate of the first sampling capacitor Cs1 is connected to the first input terminal of the operational amplifier, and the bottom plate of the second sampling capacitor Cs2 is connected to the second input terminal of the operational amplifier.

6. The switch control based sampling circuit of claim 1, wherein the control clock of the first switch is CLKS, the control clocks of the second, third and fourth switches are CLKS1, and the falling edge of CLKS1 is ahead of the falling edge of CLKS.

7. The switching control based sampling circuit of claim 6, wherein the sampling circuit comprises:

in the first state, the first switch, the second switch, the third switch and the fourth switch are all conducted, and the sampling capacitor samples;

in the second state, the first switch is turned on, the second switch is turned off, the third switch and the fourth switch are turned on, and the error delta Q generated by the second switch is released to the Vcm driving circuit in advance through the third switch and the fourth switch;

in the third state, the first switch is turned on, the second switch is turned off, the third switch and the fourth switch are turned off, and the input signal of the input end Vin is stored in the sampling capacitor;

and in the fourth state, the first switch, the second switch, the third switch and the fourth switch are all closed, and the sampling capacitor is used for holding.

8. The switch control based sampling circuit of claim 1, wherein the threshold voltages Vth3, Vth4 of the third and fourth switches are equal or different.

9. The sampling circuit based on the switch control as claimed in claim 1, wherein the second switch is a SVT NMOS transistor, and the third switch and the fourth switch are LVT NMOS transistors, or the second switch is a HVT NMOS transistor, and the third switch and the fourth switch are SVT NMOS transistors.

Technical Field

The invention belongs to the technical field of sampling circuits, and particularly relates to a sampling circuit based on switch control.

Background

Referring to fig. 1, a sampling circuit in the prior art is shown, which includes an operational amplifier AMP, sampling capacitors Cs1/Cs2, feedback capacitors Cf1/Cf2, and a plurality of switches (S1, S1', S2, S3, S4), where the sampling capacitors Cs are bottom plate sampling capacitors, the clocks of the switches S2, S3, S4 drop first at the end of sampling, that is, the bottom plate is turned off first, then the switches S1, S1' are turned off, and Vin signals are stored in the sampling capacitors Cs.

Referring to fig. 2, the control clock of S1 and S1' is CLKS, the control clock of S2, S3 and S4 is CLKS1, and the falling edge of CLKS1 is earlier than the falling edge of CLKS. However, during the falling edge of the control clock CLKS1 at S2, S3, S4 (Δ t), there are still Charge Injection (Charge Injection) and clock Feedthrough (CLK feedthru) that affect the high impedance node (AMP input) and create a differential component that affects the sampling accuracy.

Therefore, in view of the above technical problems, it is necessary to provide a sampling circuit based on switch control.

Disclosure of Invention

The invention aims to provide a sampling circuit based on switch control so as to improve sampling precision.

In order to achieve the above object, an embodiment of the present invention provides the following technical solutions:

a sampling circuit based on switch control, the sampling circuit comprising:

an operational Amplifier (AMP) including an input terminal and an output terminal;

the sampling capacitor is connected with the input end of the operational amplifier AMP;

the feedback capacitor is electrically connected between the input end and the output end of the operational amplifier AMP;

the first switch is electrically connected between the signal input end Vin and the sampling capacitor;

the second switch is electrically connected between the input ends of the operational amplifier AMP;

the third switch and the fourth switch are respectively and electrically connected between the Vcm driving circuit and the second switch;

the second switch, the third switch and the fourth switch are NMOS transistors, and the threshold voltages of the second switch, the third switch and the fourth switch are respectively Vth2 > Vth3, Vth2 > Vth4, Vth2, Vth3 and Vth 4.

In one embodiment, the operational amplifier includes a first input terminal and a second input terminal, the sampling capacitor includes a first sampling capacitor Cs1 connected to the first input terminal and a second sampling capacitor Cs2 connected to the second input terminal, and the feedback capacitor includes a first feedback capacitor Cf1 electrically connected between the first input terminal and the output terminal and a second feedback capacitor Cf2 electrically connected between the second input terminal and the output terminal.

In one embodiment, the first switch includes a first switch S1 electrically connected between the signal input terminal Vin and the first sampling capacitor Cs1 and a first switch S1' electrically connected between the signal input terminal Vin and the second sampling capacitor Cs 2.

In one embodiment, the first sampling capacitor Cs1 is the same as the second sampling capacitor Cs2, and the first feedback capacitor Cf1 is the same as the second feedback capacitor Cf 2.

In one embodiment, the first sampling capacitor Cs1 and the second sampling capacitor Cs2 are bottom plate sampling capacitors, and the bottom plate of the first sampling capacitor Cs1 is connected to the first input terminal of the operational amplifier, and the bottom plate of the second sampling capacitor Cs2 is connected to the second input terminal of the operational amplifier.

In one embodiment, the control clock of the first switch is CLKS, the control clocks of the second switch, the third switch and the fourth switch are CLKS1, and the falling edge of CLKS1 is earlier than the falling edge of CLKS.

In one embodiment, the sampling circuit includes:

in the first state, the first switch, the second switch, the third switch and the fourth switch are all conducted, and the sampling capacitor samples;

in the second state, the first switch is turned on, the second switch is turned off, the third switch and the fourth switch are turned on, and the error delta Q generated by the second switch is released to the Vcm driving circuit in advance through the third switch and the fourth switch;

in the third state, the first switch is turned on, the second switch is turned off, the third switch and the fourth switch are turned off, and the input signal of the input end Vin is stored in the sampling capacitor;

and in the fourth state, the first switch, the second switch, the third switch and the fourth switch are all closed, and the sampling capacitor is used for holding.

In one embodiment, the threshold voltages Vth3, Vth4 of the third and fourth switches are equal or different.

In one embodiment, the second switch is an SVT NMOS transistor, and the third switch and the fourth switch are LVT NMOS transistors, or the second switch is an HVT NMOS transistor, and the third switch and the fourth switch are SVT NMOS transistors.

Compared with the prior art, the invention has the following advantages:

according to the invention, the second switch can be controlled to be closed relative to the third switch and the fourth switch by controlling the threshold value of the NMOS tube switch, so that the error generated by the second switch is released to the Vcm driving circuit in advance through the third switch and the fourth switch, the high-resistance point of the operational amplifier input is not affected, and the sampling precision of the sampling circuit can be effectively improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a circuit schematic of a prior art sampling circuit;

FIG. 2 is a timing diagram of control clocks CLKS and CLKS1 of the prior art;

FIG. 3 is a schematic circuit diagram of a sampling circuit in accordance with an embodiment of the present invention;

fig. 4 is a timing diagram of the control clock CLKS1 in an embodiment of the invention.

Detailed Description

The present invention will be described in detail below with reference to embodiments shown in the drawings. The embodiments are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to the embodiments are included in the scope of the present invention.

The invention discloses a sampling circuit based on switch control, which comprises:

an operational Amplifier (AMP) including an input terminal and an output terminal;

the sampling capacitor is connected with the input end of the operational amplifier AMP;

the feedback capacitor is electrically connected between the input end and the output end of the operational amplifier AMP;

the first switch is electrically connected between the signal input end Vin and the sampling capacitor;

the second switch is electrically connected between the input ends of the operational amplifier AMP;

the third switch and the fourth switch are respectively and electrically connected between the Vcm driving circuit and the second switch;

the second switch, the third switch and the fourth switch are NMOS transistors, and the threshold voltages of the second switch, the third switch and the fourth switch are respectively Vth2 > Vth3, Vth2 > Vth4, Vth2, Vth3 and Vth 4.

The present invention is further illustrated by the following specific examples.

Referring to fig. 3, in an embodiment of the present invention, a sampling circuit based on switch control includes:

an operational Amplifier (AMP) including a first input terminal, a second input terminal, and an output terminal;

the sampling capacitor is connected with the input end of the operational amplifier AMP;

the feedback capacitor is electrically connected between the input end and the output end of the operational amplifier AMP;

the first switch is electrically connected between the signal input end Vin and the sampling capacitor;

the second switch is electrically connected between the input ends of the operational amplifier AMP;

the third switch and the fourth switch are respectively and electrically connected between the Vcm driving circuit and the second switch;

specifically, the sampling capacitor in this embodiment includes a first sampling capacitor Cs1 connected to the first input terminal and a second sampling capacitor Cs2 connected to the second input terminal, and the feedback capacitor includes a first feedback capacitor Cf1 electrically connected between the first input terminal and the output terminal and a second feedback capacitor Cf2 electrically connected between the second input terminal and the output terminal.

Preferably, the first sampling capacitor Cs1 is the same as the second sampling capacitor Cs2, the first feedback capacitor Cf1 is the same as the second feedback capacitor Cf2, and the Vcm driving circuit connected to the third switch and the fourth switch is the same.

In addition, the first sampling capacitor Cs1 and the second sampling capacitor Cs2 are bottom plate sampling capacitors, a bottom plate of the first sampling capacitor Cs1 is connected to the first input terminal of the operational amplifier, and a bottom plate of the second sampling capacitor Cs2 is connected to the second input terminal of the operational amplifier.

The first switch in this embodiment includes a first switch S1 electrically connected between the signal input terminal Vin and the first sampling capacitor Cs1, and a first switch S1' electrically connected between the signal input terminal Vin and the second sampling capacitor Cs2, a second switch S2 electrically connected between the first input terminal and the second input terminal of the operational amplifier AMP, and a third switch S3 and a fourth switch S4 electrically connected between the Vcm driving circuit and the second switch S2, respectively.

In the invention, the second switch S2, the third switch S3 and the fourth switch S4 are all NMOS transistors, and the threshold voltages of Vth2 > Vth3, Vth2 > Vth4 are met, and Vth2, Vth3 and Vth4 are respectively the threshold voltages of the second switch S2, the third switch S3 and the fourth switch S4. For example, the second switch S2 may be an SVT NMOS transistor (Standard Vth) and the third switch S3 and the fourth switch S4 are LVT NMOS transistors (Low Vth), or the second switch S2 is an HVT NMOS transistor (High Vth) and the third switch S3 and the fourth switch S4 are SVT NMOS transistors (Standard Vth).

Preferably, the third switch S3 and the fourth switch S4 in this embodiment use the same NMOS transistor, and satisfy Vth3 — Vth 4. Of course, in other embodiments, the third switch S3 and the fourth switch S4 may be different NMOS transistors.

Referring to fig. 2, the control clocks in this embodiment are the same as those in the prior art, the control clock of the first switches S1 and S1' is CLKS, the control clock of the second switch S2, the third switch S3 and the fourth switch S4 is CLKS1, and the falling edge of CLKS1 is earlier than that of CLKS.

The sampling circuit of the present invention includes:

in the first state, the first switches S1 and S1', the second switch S2, the third switch S3 and the fourth switch S4 are all turned on, and the sampling capacitor performs sampling (Sample);

in the second state, the first switches S1 and S1' are turned on, the second switch S2 is turned off, the third switch S3 and the fourth switch S4 are turned on, and the error amount Δ Q generated by the second switch S3 is released to the Vcm driver circuit in advance through the third switch S3 and the fourth switch S4;

in the third state, the first switches S1 and S1' are turned on, the second switch S2 is turned off, the third switch S3 and the fourth switch S4 are turned off, and the input signal at the input terminal Vin is stored in the sampling capacitor;

in the fourth state, the first switches S1 and S1', the second switch S2, the third switch S3, and the fourth switch S4 are all turned off, and the sampling capacitor is held (Hold).

As shown in fig. 4, during the falling of CLKS1 in this embodiment, since Vth2 > Vth3 and Vth2 > Vth4, the second switch S2 is turned off first with respect to the third switch S3 and the fourth switch S4, which corresponds to the second state in this embodiment.

Therefore, in the falling process of CLKS1, in the period (T1-T2) after the second switch S2 is turned off and before the third switch S4 and the fourth switch S4 are turned off, the error amount Δ Q generated by the second switch S2 due to Charge Injection (Charge Injection) and clock feed-through (CLK feed through) can be released to the Vcm driving circuit in advance through the third switch S3 and the fourth switch S4, the high-resistance point of the operational input is not affected, and the sampling precision can be effectively improved.

The technical scheme shows that the invention has the following beneficial effects:

according to the invention, the second switch can be controlled to be closed relative to the third switch and the fourth switch by controlling the threshold value of the NMOS tube switch, so that the error generated by the second switch is released to the Vcm driving circuit in advance through the third switch and the fourth switch, the high-resistance point of the operational amplifier input is not affected, and the sampling precision of the sampling circuit can be effectively improved.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.