阅读说明：本技术 套刻误差检测图形及方法 (Overlay error detection pattern and method ) 是由 陈媛 邱瑾玉 耿玉慧 宋之洋 于 2020-12-15 设计创作，主要内容包括：本发明提供一种套刻误差检测图形及方法。包括第一图形及第二图形,形成于上下叠置的两个膜层上,第一图形和第二图形上下对应设置且中心点位于同一垂线上；第一图形包括单个第一矩形图案,第二图形包括单个或多个第二矩形图案,第一矩形图案的长边与短边的比值小于第二矩形图案的长边与短边的比值,第二矩形图案的中间部分沿垂直第一矩形图案方向的正投影落在第一矩形图案内,与中间部分相连接的两端的正投影位于第一矩形图形外。本发明在实现量测目的的前提下可以减少图形占用的平面面积,这使得其可以分布于晶粒中,因而其切割道film stack与晶粒内器件更加接近,可以有效减小套刻误差,提高生产良率和降低生产成本。(The invention provides an overlay error detection graph and a method. The film comprises a first pattern and a second pattern which are formed on two films which are superposed up and down, wherein the first pattern and the second pattern are arranged correspondingly up and down, and the central points are positioned on the same vertical line; the first graph comprises a single first rectangular pattern, the second graph comprises a single or a plurality of second rectangular patterns, the ratio of the long side to the short side of the first rectangular pattern is smaller than the ratio of the long side to the short side of the second rectangular pattern, the orthographic projection of the middle part of the second rectangular pattern along the direction vertical to the first rectangular pattern falls in the first rectangular pattern, and the orthographic projection of the two ends connected with the middle part is positioned outside the first rectangular pattern. The invention can reduce the plane area occupied by the pattern on the premise of realizing the measurement purpose, so that the pattern can be distributed in the crystal grains, the cutting path film stack is closer to devices in the crystal grains, the overlay error can be effectively reduced, the production yield is improved, and the production cost is reduced.)

1. An overlay error detection pattern is characterized by comprising a first pattern and a second pattern, wherein the first pattern and the second pattern are formed on two film layers which are overlapped up and down, the first pattern and the second pattern are correspondingly arranged up and down, and the central points of the first pattern and the second pattern are positioned on the same vertical line; the first graph comprises a single first rectangular pattern, the second graph comprises a single or a plurality of second rectangular patterns, and when the number of the second rectangular patterns is multiple, the second rectangular patterns are distributed at intervals in parallel; the ratio of the long side to the short side of the first rectangular pattern is smaller than that of the long side to the short side of the second rectangular pattern, the orthographic projection of the middle part of the second rectangular pattern along the direction perpendicular to the first rectangular pattern falls in the first rectangular pattern, and the orthographic projection of the two ends connected with the middle part is positioned outside the first rectangular pattern.

2. The overlay error detection pattern of claim 1 wherein the long side of the first rectangular pattern and the long side of the second rectangular pattern are each 2 μm or less.

3. The overlay error detection pattern according to claim 2, wherein the second rectangular pattern is single, a long side of the second rectangular pattern is parallel to a long side of the first rectangular pattern, a long side dimension of the second rectangular pattern is larger than a long side dimension of the first rectangular pattern, and a short side dimension of the second rectangular pattern is smaller than a short side dimension of the first rectangular pattern and larger than a distance between the long side of the second rectangular pattern and the long side of the first rectangular pattern.

4. The overlay error detection pattern according to claim 3, wherein the first rectangular pattern has a long side of 1 μm and a short side of 0.8 μm, the second rectangular pattern has a long side of 1.2 μm and a short side of 0.5 μm, and the second rectangular pattern has a long side spaced apart from the first rectangular pattern by 0.15 μm.

5. The overlay error detection pattern according to claim 2, wherein the number of the second rectangular patterns is 3, the long sides of the second rectangular patterns are parallel to the short sides of the first rectangular patterns, the pitch between adjacent second rectangular patterns is the same as the size of the short sides of the second rectangular patterns, the size of the short sides of the second rectangular patterns is smaller than the shortest distance between the long sides of the second rectangular patterns and the short sides of the first rectangular patterns, and the size of the short sides and/or the long sides of the second rectangular patterns located in the middle is the same as or different from that of the second rectangular patterns located on both sides thereof.

6. The overlay error detection pattern according to claim 5, wherein the first rectangular pattern has a long side of 1.2 μm and a short side of 1 μm, all of the second rectangular patterns have a long side of 1.2 μm and a short side of 0.15 μm, and the shortest distance between the long side of the second rectangular pattern and the short side of the first rectangular pattern is 0.225 μm.

7. The overlay error detection pattern according to claim 2, wherein the number of the second rectangular patterns is 3, the long sides of the second rectangular patterns are parallel to the short sides of the first rectangular patterns, the distance between adjacent second rectangular patterns is the same as the size of the short sides of the second rectangular patterns, the size of the short sides of the second rectangular patterns is larger than the shortest distance between the long sides of the second rectangular patterns and the short sides of the first rectangular patterns, and the size of the short sides and/or the long sides of the second rectangular patterns located in the middle is the same as or different from the size of the short sides and/or the long sides of the second rectangular patterns located on both sides thereof.

8. The overlay error detection pattern according to claim 7, wherein the first rectangular patterns have a long side of 1.2 μm and a short side of 1 μm, all of the second rectangular patterns have a long side of 1.2 μm and a short side of 0.2 μm, and the shortest distance between the long side of the second rectangular pattern and the short side of the first rectangular pattern is 0.1 μm.

9. The overlay error detection pattern according to claim 2, wherein the number of the second rectangular patterns is 5, the long sides of the second rectangular patterns are parallel to the short sides of the first rectangular patterns, the pitch between adjacent second rectangular patterns is close to the pitch between device structures in the same die, the size of the short side of the second rectangular pattern is smaller than the shortest distance between the long side of the second rectangular pattern and the short side of the first rectangular pattern, and the size of the short side and/or the long side of the second rectangular pattern located in the middle is the same as or different from the size of the short side and/or the long side of the second rectangular pattern located on both sides of the second rectangular pattern.

10. The overlay error detection pattern according to claim 9, wherein the first rectangular pattern has a long side of 1.2 μm and a short side of 1 μm, all of the second rectangular patterns have a long side of 1.2 μm and a short side of 0.1 μm, and the shortest distance between the long side of the second rectangular pattern and the short side of the first rectangular pattern is 0.15 μm.

11. An overlay error detection method, wherein the overlay error detection method is performed based on the overlay error detection pattern of any one of claims 1 to 10.

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to a photoetching process, and particularly relates to an overlay error detection graph and a method.

Background

Photolithography, which is a very important process in the semiconductor chip manufacturing process, uses a photo-like printing technique to print a fine pattern on a mask plate onto a wafer by exposure to light. With the rapid development of semiconductor manufacturing technology and the increasing functions of consumer electronics, the device integration level is higher and higher, and the feature size of semiconductor devices is continuously reduced, so as to provide higher and higher requirements for the photolithography process. One of the most important tasks in the photolithography process is to perform an interlayer alignment, i.e. overlay alignment (overlay), to ensure the alignment between the current pattern (i.e. the current layer pattern) and the pattern already existing on the silicon wafer (i.e. the previous layer pattern), and the overlay accuracy is to measure the alignment accuracy between the current layer pattern and the previous layer pattern. High resolution scanning electron microscopes (CD-SEM) are often used in the prior art to measure overlay error. CD-SEM is a method for detecting secondary electrons or backscattered electrons to resolve patterns for measurement purposes. The CD-SEM based overlay error may be used as a reference metrology data for optimizing optical metrology measurements. When using CD-SEM to measure overlay error, firstly, an overlay error detection pattern often called CD-SEM target is made on the pattern layer. The existing CD-SEM target is designed by simulating a semiconductor device (the CD-SEM target is generally the same shape and the same size as the semiconductor device pattern). For example, as shown in fig. 1 and fig. 2, the patterns of the front layer and the current layer are separately arranged or overlapped, and a plurality of pattern measurement center points need to be selected under the same lens viewing angle, because of the design of the analog semiconductor device, the CD-SEM target has a large design size (14 × 14um), and is usually placed in a scribe lane to avoid occupying the wafer effective area, and is affected by the scribe lane film stack and stress, the measurement result is easily different from the actual value of the etching error in the die, which leads to the decrease of the overlay accuracy and finally the performance decrease or even complete failure of the device, which leads to the decrease of the production yield and the increase of the production cost.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an overlay error detection pattern and a method thereof, for solving the problems that the overlay error detection pattern used in the prior art adopts a design of an analog semiconductor device, has a large design size, is usually placed in a scribe line, and is affected by a scribe line film stack and stress, and a measurement result is easily different from a true value of an intra-wafer overlay error, so that overlay accuracy is reduced, and finally, device performance is reduced or even completely failed, so that production yield is reduced and production cost is increased.

In order to achieve the above and other related objects, the present invention provides an overlay error detection pattern, which includes a first pattern and a second pattern, where the first pattern and the second pattern are formed on two stacked film layers, the first pattern and the second pattern are disposed in a corresponding manner, and center points of the first pattern and the second pattern are located on a same vertical line, the first pattern includes a single first rectangular pattern, the second pattern includes a single or multiple second rectangular patterns, and when the number of the second rectangular patterns is multiple, the multiple second rectangular patterns are distributed in parallel at intervals; the ratio of the long side to the short side of the first rectangular pattern is smaller than that of the long side to the short side of the second rectangular pattern, the orthographic projection of the middle part of the second rectangular pattern along the direction perpendicular to the first rectangular pattern falls in the first rectangular pattern, and the orthographic projection of the two ends connected with the middle part is positioned outside the first rectangular pattern.

Optionally, both the long side of the first rectangular pattern and the long side of the second rectangular pattern are less than or equal to 2 μm.

In an alternative, the second rectangular pattern is single, the long side of the second rectangular pattern is parallel to the long side of the first rectangular pattern, the size of the long side of the second rectangular pattern is larger than the size of the long side of the first rectangular pattern, and the size of the short side of the second rectangular pattern is smaller than the size of the short side of the first rectangular pattern and larger than the distance between the long side of the second rectangular pattern and the long side of the first rectangular pattern.

More optionally, the long side of the first rectangular pattern is 1 μm and the short side is 0.8 μm, the long side of the second rectangular pattern is 1.2 μm and the short side is 0.5 μm, and a distance between the long side of the second rectangular pattern and the long side of the first rectangular pattern is 0.15 μm.

In another alternative, the number of the second rectangular patterns is 3, the long sides of the second rectangular patterns are parallel to the short sides of the first rectangular patterns, the distance between adjacent second rectangular patterns is the same as the size of the short sides of the second rectangular patterns, the size of the short sides of the second rectangular patterns is smaller than the shortest distance between the long sides of the second rectangular patterns and the short sides of the first rectangular patterns, and the size of the short sides and/or the long sides of the second rectangular patterns in the middle is the same as or different from that of the short sides and/or the long sides of the second rectangular patterns on both sides.

More optionally, the long sides of the first rectangular patterns are 1.2 μm and the short sides are 1 μm, the long sides of the second rectangular patterns are 1.2 μm and the short sides are 0.15 μm, and the shortest distance between the long sides of all the second rectangular patterns and the short sides of the first rectangular patterns is 0.225 μm.

In yet another alternative, the number of the second rectangular patterns is 3, the long sides of the second rectangular patterns are parallel to the short sides of the first rectangular patterns, the distance between the adjacent second rectangular patterns is the same as the size of the short sides of the second rectangular patterns, the size of the short sides of the second rectangular patterns is larger than the shortest distance between the long sides of the second rectangular patterns and the short sides of the first rectangular patterns, and the size of the short sides and/or the long sides of the second rectangular patterns in the middle is the same as or different from the size of the short sides and/or the long sides of the second rectangular patterns on both sides thereof.

More optionally, the long sides of the first rectangular patterns are 1.2 μm and the short sides are 1 μm, the long sides of all the second rectangular patterns are 1.2 μm and the short sides are 0.2 μm, and the shortest distance between the long sides of the second rectangular patterns and the short sides of the first rectangular patterns is 0.1 μm.

In another alternative, the number of the second rectangular patterns is 5, the long sides of the second rectangular patterns are parallel to the short sides of the first rectangular patterns, the distance between the adjacent second rectangular patterns is close to the distance between the device structures in the same die, the size of the short sides of the second rectangular patterns is smaller than the shortest distance between the long sides of the second rectangular patterns and the short sides of the first rectangular patterns, and the size of the short sides and/or the long sides of the second rectangular patterns in the middle is the same as or different from that of the second rectangular patterns on the two sides of the second rectangular patterns.

More optionally, the long sides of the first rectangular patterns are 1.2 μm and the short sides are 1 μm, the long sides of all the second rectangular patterns are 1.2 μm and the short sides are 0.1 μm, and the shortest distance between the long sides of the second rectangular patterns and the short sides of the first rectangular patterns is 0.15 μm.

The invention also provides an overlay error detection method based on the overlay error detection pattern in any scheme.

As described above, the overlay error detection pattern and method of the present invention have the following advantages: the application provides an improved overlay error detection graph, the design is ingenious, the floor area of the graph occupied can be reduced on the premise of achieving the measuring purpose, the graph can be distributed in a crystal grain (die), therefore, a cutting line film stack is closer to a device in the crystal grain, the overlay error can be effectively reduced, more accurate data are provided for intra-crystal grain overlay measurement (die overlay) and mask correction (mask correction), and the improvement of the production yield and the reduction of the production cost are facilitated. And because the structure is regular, the corresponding key size can be directly and automatically generated by a script or a database through inputting, the time cost of photomask research and development can be reduced, and the research and development efficiency can be improved.

Drawings

Fig. 1 and 2 are schematic structural diagrams illustrating an overlay error detection pattern in the prior art.

Fig. 3 to 6 are schematic structural diagrams illustrating alignment error detection patterns provided by the present invention in different examples.

Description of the element reference numerals

11-a first graphic; 12-second figure

Detailed Description

The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will become apparent to those skilled in the art from the present disclosure.

Please refer to fig. 3 to 6. It should be understood that the structures, ratios, sizes, and the like shown in the drawings and described in the specification are only used for matching with the disclosure of the specification, so as to be understood and read by those skilled in the art, and are not used to limit the conditions under which the present invention can be implemented, so that the present invention has no technical significance, and any structural modification, ratio relationship change, or size adjustment should still fall within the scope of the present invention without affecting the efficacy and the achievable purpose of the present invention. In addition, the terms such as "upper", "lower", "left", "right", "middle" and "one" used in the present specification are for clarity of description, and are not intended to limit the scope of the present invention, and changes or modifications of the relative relationship may be made without substantial technical changes.

As shown in fig. 3 to 6, the present invention provides an overlay error detection pattern, where the overlay error detection pattern includes a first pattern 11 and a second pattern 12, the first pattern 11 and the second pattern 12 are formed on two films stacked up and down, the first pattern 11 and the second pattern 12 are disposed up and down correspondingly, and center points of the first pattern 11 and the second pattern 12 are located on a same vertical line; the first pattern 11 comprises a single first rectangular pattern, the second pattern 12 comprises a single or a plurality of second rectangular patterns, and when the number of the second rectangular patterns is multiple, the plurality of second rectangular patterns are distributed at intervals in parallel; the ratio of the long side to the short side of the first rectangular pattern is smaller than that of the long side to the short side of the second rectangular pattern, the orthographic projection of the middle part of the second rectangular pattern in the direction perpendicular to the first rectangular pattern falls in the first rectangular pattern, the orthographic projection of the two ends connected with the middle part is positioned outside the first rectangular pattern, and the sizes of the two ends positioned outside the first rectangular pattern are preferably the same. It should be noted that the long side refers to the longer of the two sides of the rectangle, and the short side refers to the shorter of the two sides of the rectangle. The overlay error detection graph has ingenious design, the boundaries of the first graph and the second graph are not overlapped as much as possible under the condition of meeting the overlay detection requirement, the first graph and the second graph can be conveniently and quickly identified by detection equipment during overlay detection (particularly, the identification difficulty is increased because the graph in a front film layer is blocked by a current film layer), and the floor plan area occupied by the graphs can be reduced on the premise of realizing the measurement purpose, so that the graphs can be distributed in a crystal (die), the cutting path film stack is closer to an intra-crystal device, the overlay error can be effectively reduced, more accurate data are provided for intra-crystal overlay measurement (inde overlay) and mask correction (mask correction), and the overlay error is beneficial to improving the production yield and reducing the production cost. And because the structure is regular, the corresponding key size can be directly and automatically generated by a script or a database through inputting, the time cost of photomask research and development can be reduced, and the research and development efficiency can be improved.

It should be noted that "first", "second", and the like in the present embodiment are merely for convenience of description and are not in a limiting sense in nature. The overlay error detection patterns are designed before the photoetching process and then input into photoetching equipment, a front film layer is formed firstly through photoetching, one of a first pattern 11 and a second pattern 12 is formed in the front film layer, then a layer of photoresist is coated on the surface of the front film layer, the exposed photoresist layer is a current film layer, at the moment, one of the first pattern 11 and the second pattern 12 is displayed in the current film layer (not etched), at the moment, a detection tool is needed, for example, a CD-SEM is adopted to detect the sizes of the first pattern 11 and the second pattern 12 and the distance between the first pattern 11 and the second pattern 12 or the coordinate value of a detected specific point and compare the detected value with the initially designed value to obtain an overlay error, and if the error is within a process tolerance range, the next step of etching and other processes are carried out; if the error is out of the process tolerance range and cannot be corrected, the current photoresist layer is completely removed, a new photoresist layer is coated again (i.e. rework process, rework process), and then a new round of overlay alignment detection is performed after exposure. The photoetching process is the only process capable of reworking in the manufacturing process of the semiconductor chip, the yield of the photoetching process is improved by improving the detection precision of the overlay error, the problem products are prevented from flowing into the next procedure, the production efficiency is improved, and the production cost is reduced.

In a preferred example, the long sides of the first rectangular pattern 11 and the second rectangular pattern 12 are both less than or equal to 2 μm, such as 0.7-1.5 μm (inclusive), and more preferably 0.8-1.2 μm, and this size design makes the distribution positions of the first pattern 11 and the second pattern 12 more flexible, and the patterns can be distributed not only in the scribe lines but also in the chip dies, or overlay error detection patterns can be set in the chip dies and the scribe lines as required.

The upper and lower positions of the first pattern 11 and the second pattern 12 are not strictly limited, as long as the upper and lower positions are corresponding and are centrosymmetric when the design is performed, and the central points are located on the same vertical line. In one example, the first pattern 11 is formed on a previous film layer, the second pattern 12 is formed on a current film layer, the current film layer is a photoresist layer, and the previous film layer may be an oxide layer or a metal layer. Of course, in other examples, the second pattern 12 may be formed on the front layer film layer and the first pattern 11 may be formed on the photoresist layer, which may be selected according to process preference, but is preferred if allowed, so that the CD-SEM can more clearly identify the patterns in the current layer and the front layer during the subsequent overlay detection.

The specific form of the first and second rectangular patterns may also be process dependent. For example, if the CD-SEM is formed in the front film layer, according to different process designs, the CD-SEM may be a rectangular groove (the entire pattern is a groove), the depth of the groove may be the same as or smaller than the thickness of the front film layer, or the depth may decrease stepwise from the circumference of the rectangle to the center of the rectangle, or may be a rectangular ring structure, that is, only four sides of the rectangle are used as a channel, and the inside of the rectangle is not hollowed, or may be another structure, or the circumference of the pattern in the front film layer is specially processed to facilitate the recognition of the boundary. Preferably, the pattern in the front film layer is preferably a groove, and the color depth inside and outside the groove is identified by the difference displayed by CD-SEM.

In one example, as shown in fig. 3, the second rectangular pattern is single, the long side of the second rectangular pattern is parallel to the long side of the first rectangular pattern, the size of the long side of the second rectangular pattern is larger than the size of the long side of the first rectangular pattern, both ends of the long side of the second rectangular pattern are located at the periphery of the first rectangular pattern, and the size of the short side of the second rectangular pattern is smaller than the size of the short side of the first rectangular pattern and larger than the distance between the long side of the second rectangular pattern and the long side of the first rectangular pattern, so that the orthographic projection of the middle part of the second rectangular pattern along the direction of the first rectangular pattern completely falls within the first rectangular pattern. The design is simple, the overlay alignment error can be detected quickly, for example, the overlay alignment error can be determined by detecting the deviation of the coordinate values of the central points of the first graph 11 and the second graph 12 during detection, rework can be judged without subsequent operation if the deviation is too large, and the sizes of the first graph 11 and the second graph 12 are detected if the central points do not have the deviation. In a specific example, the long side of the first rectangular pattern is 1 μm and the short side is 0.8 μm, the long side of the second rectangular pattern is 1.2 μm and the short side is 0.5 μm, and the distance between the long side of the second rectangular pattern and the long side of the first rectangular pattern is 0.15 μm.

In another example, as shown in fig. 4, the number of the second rectangular patterns is 3, the long sides of the second rectangular patterns are parallel to the short sides of the first rectangular patterns, the pitch between adjacent second rectangular patterns is the same as the size of the short sides of the second rectangular patterns, and the size of the short sides of the second rectangular patterns is smaller than the shortest distance between the long sides of the second rectangular patterns and the short sides of the first rectangular patterns. In a further example, the first rectangular patterns have a long side of 1.2 μm and a short side of 1 μm, all of the second rectangular patterns have a long side of 1.2 μm and a short side of 0.15 μm, and the shortest distance between the long side of the second rectangular pattern and the short side of the first rectangular pattern, that is, the distance between the outermost second rectangular pattern and the short side of the first rectangular pattern, is 0.225 μm. That is, in the present embodiment, the long side sizes of all the second rectangular patterns are the same and the short side sizes are the same. In this design, the second rectangular patterns are distributed as many as possible in a limited space, which contributes to further reducing pattern deformation caused by film stress and the like, thereby contributing to improvement of detection accuracy. In other examples, the second rectangular pattern located in the middle and the second rectangular patterns located on both sides thereof may have the same long side size and different short side sizes (the long side and the short side sizes of the second rectangular patterns on both sides are preferably the same to improve stress distribution uniformity), or the short side sizes are the same and the long side sizes are different, or the long side and the short side sizes are different, and it is preferable that all the second rectangular patterns have the same specification size from the viewpoint of simplifying the process.

In another example, as shown in fig. 5, there are 3 second rectangular patterns, and this embodiment considers the detection accuracy and the graph forming difficulty together, where the long sides of the second rectangular patterns are parallel to the short sides of the first rectangular patterns, the distance between adjacent second rectangular patterns is the same as the size of the short sides of the second rectangular patterns, and the size of the short sides of the second rectangular patterns is greater than the shortest distance between the long sides of the second rectangular patterns and the short sides of the first rectangular patterns. In a further example, the first rectangular patterns have a long side of 1.2 μm and a short side of 1 μm, all of the second rectangular patterns have a long side of 1.2 μm and a short side of 0.2 μm, and the shortest distance between the long side of the second rectangular pattern and the short side of the first rectangular pattern is 0.1 μm. That is, in the present embodiment, the long side sizes of all the second rectangular patterns are the same and the short side sizes are the same. In this design, the second rectangular patterns with larger size are distributed in a limited space as much as possible, which is beneficial to reducing the forming difficulty of the second pattern 12. In other examples, the second rectangular pattern located in the middle and the second rectangular patterns located on both sides thereof may have the same long side size and different short side sizes (the long side and the short side sizes of the second rectangular patterns on both sides are preferably the same to improve stress distribution uniformity), or the short side sizes are the same and the long side sizes are different, or the long side and the short side sizes are different, and it is preferable that all the second rectangular patterns have the same specification size from the viewpoint of simplifying the process.

In yet another example, the number of the second rectangular patterns is 5, the long sides of the second rectangular patterns are parallel to the short sides of the first rectangular patterns, the pitch between adjacent second rectangular patterns is the same as the size of the short sides of the second rectangular patterns, and the size of the short sides of the second rectangular patterns is smaller than the shortest distance between the long sides of the second rectangular patterns and the short sides of the first rectangular patterns. In a further example, the first rectangular patterns have a long side of 1.2 μm and a short side of 1 μm, all of the second rectangular patterns have a long side of 1.2 μm and a short side of 0.1 μm, and the shortest distance between the long side of the second rectangular pattern and the short side of the first rectangular pattern is 0.15 μm. That is, in the present embodiment, the long side sizes of all the second rectangular patterns are the same and the short side sizes are the same. In this design, as many second rectangular patterns with smaller dimensions as possible are distributed in a limited space, and the pitch between the second rectangular patterns is close to the pitch between device structures in the same die (for example, the pitch between adjacent contact holes), so that by detecting the deviation between the dimension of the second pattern 12 and a design value, whether the setting of the lithography parameters is reasonable can be evaluated, which is helpful for improving the process yield. In other examples, the second rectangular pattern located in the middle and the second rectangular patterns located on both sides thereof may have the same long side size and different short side sizes (the long side and the short side sizes of the second rectangular patterns on both sides are preferably the same to improve stress distribution uniformity), or the short side sizes are the same and the long side sizes are different, or the long side and the short side sizes are different, and it is preferable that all the second rectangular patterns have the same specification size from the viewpoint of simplifying the process.

The invention further provides an overlay error detection method, which is performed based on the overlay error detection pattern in any of the above schemes, and the introduction of the overlay error detection pattern is referred to the above contents, which are not repeated for brevity. The alignment error detection method can be used for respectively forming the first graph and the second graph on the front film layer and the current film layer, and then detecting the sizes of the first graph and the second graph and the positions of the specific coordinate points by using an alignment detection tool, such as a CD-SEM (compact disc-scanning electron microscope) and comparing the sizes with an initial preset value, so that the alignment error is obtained and the mask correction is carried out accordingly, and the process production yield is improved.

In summary, the present invention provides an overlay error detection pattern and method. The alignment error detection pattern comprises a first pattern and a second pattern, the first pattern and the second pattern are formed on two film layers which are overlapped up and down, the first pattern and the second pattern are arranged correspondingly up and down, and the central points of the first pattern and the second pattern are positioned on the same vertical line; the first graph comprises a single first rectangular pattern, the second graph comprises a single or a plurality of second rectangular patterns, and when the number of the second rectangular patterns is multiple, the second rectangular patterns are distributed at intervals in parallel; the ratio of the long side to the short side of the first rectangular pattern is smaller than that of the long side to the short side of the second rectangular pattern, the long side of the first rectangular pattern and the long side of the second rectangular pattern are both smaller than or equal to 2 micrometers, the orthographic projection of the middle part of the second rectangular pattern along the direction perpendicular to the first rectangular pattern falls in the first rectangular pattern, and the orthographic projection of the two ends connected with the middle part is positioned outside the first rectangular pattern. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value. The overlay error detection graph has ingenious design, can reduce floor plan area occupied by the graph on the premise of realizing the measurement purpose, and can be distributed in a crystal grain (die), so that the film stack of the graph is closer to a device in the crystal grain, and the overlay error can be effectively reduced, thereby providing more accurate data for intra-crystal overlay measurement (index overlay) and mask correction (mask correction), and being beneficial to improving the production yield and reducing the production cost. And because the structure is regular, the corresponding key size can be directly and automatically generated by a script or a database through inputting, the time cost of photomask research and development can be reduced, and the research and development efficiency can be improved.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.