阅读说明：本技术 积和运算器、逻辑运算器件、神经形态器件及积和运算方法 (Product-sum arithmetic unit, logical operation device, neuromorphic device, and product-sum arithmetic method ) 是由 伊藤邦恭 柴田龙雄 于 2018-10-11 设计创作，主要内容包括：本发明提供一种积和运算器,其具有：多个积运算部,其对与输入值对应的具有上升部、信号部和下降部的输入信号乘以权重来生成输出信号,并输出所述输出信号；和运算部,其运算多个所述积运算部各自输出的所述输出信号的总和；以及校正部,其执行基于包含第一值和第二值中的至少一者的校正值来校正所述输出信号的总和的校正处理,其中,所述第一值是通过由所述输入信号的所述上升部引起的流入多个所述积运算部的可变电阻中的电流而被并入于所述总和的值,所述第二值是通过由所述输入信号的所述下降部引起的流入多个所述积运算部的可变电阻中的电流而被并入于所述总和的值。(The present invention provides a product-sum arithmetic unit, comprising: a plurality of product calculation units that multiply an input signal having a rising unit, a signal unit, and a falling unit, which correspond to an input value, by a weight to generate an output signal and output the output signal; and a calculation unit that calculates a sum of the output signals output by the plurality of product calculation units; and a correction section that performs correction processing of correcting a sum total of the output signals based on a correction value including at least one of a first value and a second value, wherein the first value is a value that is incorporated in the sum total by a current flowing into variable resistors of the plurality of product operation sections caused by the rising section of the input signal, and the second value is a value that is incorporated in the sum total by a current flowing into variable resistors of the plurality of product operation sections caused by the falling section of the input signal.)

1. A product-sum operator, comprising:

a plurality of product calculation units that multiply an input signal having a rising unit, a signal unit, and a falling unit, which correspond to an input value, by a weight to generate an output signal and output the output signal;

and a calculation unit that calculates a sum of the output signals output by the plurality of product calculation units; and

a correction section that performs a correction process of correcting a sum total of the output signals based on a correction value including at least one of a first value and a second value, wherein the first value is a value incorporated in the sum total by a current flowing into variable resistors of the plurality of product operation sections caused by the rising section of the input signal, and the second value is a value incorporated in the sum total by a current flowing into variable resistors of the plurality of product operation sections caused by the falling section of the input signal.

2. The product-sum operator according to claim 1,

each of the product operation units includes a magnetoresistance effect element exhibiting a magnetoresistance effect.

3. The product-sum operator according to claim 1,

each of the plurality of product operation portions includes a variable resistance element having a write terminal, a common terminal, and a read terminal.

4. A product-sum operator according to any one of claims 1 to 3,

further comprising an input unit for inputting a correction input signal having the rising unit and the falling unit to the product calculation unit,

the product operation unit further multiplies the correction input signal by a weight to generate a correction output signal and outputs the correction output signal,

the sum operation unit further calculates a sum of the correction output signals output from the plurality of product operation units,

the correction unit performs the correction processing with a sum of the correction output signals as the correction value.

5. A product-sum operator according to any one of claims 1 to 4,

a correction value storage unit for storing the correction value is also provided.

6. A product-sum operator according to any one of claims 1 to 5,

the input signal is input to the product operation unit via a resistor.

7. A logical operation device characterized in that,

having a product-sum operator as claimed in any one of claims 1 to 6.

8. A neuromorphic device characterized by,

having a product-sum operator as claimed in any one of claims 1 to 6.

9. A product-sum operation method performed by the product-sum operator according to any one of claims 1 to 6, comprising:

a product calculation step of multiplying an input signal having a rising section, a signal section, and a falling section corresponding to an input value by a weight to generate an output signal and outputting the output signal;

and a calculation step of calculating a sum of the output signals output in the product calculation step; and

a correction step of performing correction processing of correcting a sum of the output signals based on a correction value including at least one of a first value and a second value, wherein the first value is a value incorporated in the sum by a current flowing into variable resistors of the plurality of product operation sections caused by the rising section of the input signal, and the second value is a value incorporated in the sum by a current flowing into variable resistors of the plurality of product operation sections caused by the falling section of the input signal.

Technical Field

The invention relates to a product-sum arithmetic unit, a logical operation device, a neuromorphic device, and a product-sum arithmetic method.

Background

In order to improve power consumption, which is one of the disadvantages of the conventional neural network, research using a memory bank, which is a passive element that records a passing charge and changes resistance, has been actively conducted.

In a conventional neural network, weights are accumulated for input data, and the total value of all the weights is input to an activation function to obtain an output. Therefore, an attempt has been made to realize product-sum operation by an analog circuit by combining two or more resistance variable elements whose resistances continuously change and reading the sum of current values output thereafter.

In the learning process of the neural network, the resistance value is changed so that the memory bank allocated to each synapse is given a predetermined weight, and the value is maintained even when the power supply is turned off. In the inference process, Pulse Width Modulation (PWM) control is used in which the length of a voltage Pulse is changed in accordance with the level of input data by using the value of a bank holding information.

For example, non-patent document 1 discloses a method of performing an operation of a neural network using a resistance variable element such as a memory bank. Here, in the calculation of the neural network, the sum of output signals output from the plurality of variable resistance elements to which an input signal as a voltage pulse is input is calculated. It is desirable to perform the operation of the sum of the output signals as accurately as possible.

Documents of the prior art

Non-patent document

Non-patent document 1: geoffrey W.Burr, Robert M.Shelby, Abu Sebastian, Sangbum Kim, Seyoung Kim, Severin Sidler, Kumar Virwani, Masatoshi Ishii, Pritiash Narayanan, Alessandro Fumarola, Lucas L.Sanches, Irem Boybab, Manual Le Gallo, Kibing Moon, Jiyoo Wo, Hyunsang Hwang & Yussuf Lebleblici, Advancin Physics: x,2,89(2017)

Disclosure of Invention

Problems to be solved by the invention

The variable resistance element has a circuit configuration in which a parasitic capacitance and a parasitic resistance are connected in parallel as an equivalent circuit, and an inrush current due to charging and discharging of each variable resistance element to and from the parasitic capacitance is generated by input of an input signal as a voltage pulse. Therefore, as one of measures to alleviate the heat generation of the circuit and the load on the circuit due to the inrush current, the speed of change of the voltage of the rising portion and the falling portion of the input signal is reduced.

However, when the rate of change in the voltage of the rising portion and the falling portion is reduced, a current also flows into the parasitic resistance of each variable resistance element, and therefore, the value due to the current may be incorporated into the sum of the output signals described above, and the accuracy of the sum calculation may be reduced.

Accordingly, an object of the present invention is to provide a product-sum operator, a logical operation device, a neuromorphic device, and a product-sum operation method capable of performing an accurate product-sum operation.

Means for solving the problems

In one aspect, the present invention provides a product-sum calculator including: a plurality of product calculation units that multiply an input signal having a rising unit, a signal unit, and a falling unit, which correspond to an input value, by a weight to generate an output signal and output the output signal; and a calculation unit that calculates a sum of the output signals output by the plurality of product calculation units; and a correction section that performs correction processing of correcting a sum total of the output signals based on a correction value including at least one of a first value and a second value, wherein the first value is a value that is incorporated in the sum total by a current flowing into variable resistors of the plurality of product operation sections caused by the rising section of the input signal, and the second value is a value that is incorporated in the sum total by a current flowing into variable resistors of the plurality of product operation sections caused by the falling section of the input signal.

In one aspect of the present invention, each of the plurality of product operation units includes a magnetoresistance effect element exhibiting a magnetoresistance effect.

In one aspect of the present invention, each of the plurality of product operation portions includes a variable resistance element having a write terminal, a common terminal, and a read terminal.

The product-sum calculator according to an aspect of the present invention further includes an input unit that inputs a correction input signal having the rising unit and the falling unit to the product operation unit, the product operation unit further multiplies the correction input signal by a weight to generate a correction output signal and outputs the correction output signal, the sum operation unit further calculates a sum of the correction output signals output by the plurality of product operation units, and the correction unit executes the correction process with the sum of the correction output signals as the correction value.

The product-sum calculator according to an aspect of the present invention further includes a correction value storage unit that stores the correction value.

In the product-sum calculator according to the aspect of the present invention, the input signal is input to the product operation unit via a resistor.

In addition, an aspect of the present invention provides a logical operation device having any one of the product-sum operators described above.

In another aspect, the present invention provides a neuromorphic device having any one of the product-sum operators described above.

In addition, an aspect of the present invention provides a product-sum operation method, including: a product calculation step of multiplying an input signal having a rising section, a signal section, and a falling section corresponding to an input value by a weight to generate an output signal and outputting the output signal; and a calculation step of calculating a sum of the output signals output in the product calculation step; and a correction step of performing correction processing of correcting a sum total of the output signals based on a correction value including at least one of a first value and a second value, wherein the first value is a value incorporated in the sum total by a current flowing into variable resistors of the plurality of product operation sections caused by the rising section of the input signal, and the second value is a value incorporated in the sum total by a current flowing into variable resistors of the plurality of product operation sections caused by the falling section of the input signal.

Effects of the invention

According to the product-sum operator, the logical operation device, the neuromorphic device, and the product-sum operation method described above, the product-sum operator, the logical operation device, the neuromorphic device, and the product-sum operation method capable of performing accurate product-sum operation can be provided.

Drawings

Fig. 1 is a diagram showing an example of a partial configuration of a product-sum calculator according to the first embodiment.

Fig. 2 is a diagram showing an example of the variable resistance element according to the first embodiment.

Fig. 3 is a diagram showing an example of an equivalent circuit of a partial configuration of the product-sum calculator according to the first embodiment.

Fig. 4 is a diagram showing an example of an inrush current when an input signal passes through the product operation unit 111 according to the first embodiment.

Fig. 5 is a diagram showing an example of the correction input signal according to the first embodiment.

Fig. 6 is a diagram for explaining an example of the sum calculating unit, the correcting unit, and the data processing unit according to the first embodiment.

Fig. 7 is a diagram for explaining an example of the neural network operation performed by the product-sum calculator according to the first embodiment.

Fig. 8 is a diagram for explaining an example of the sum calculating unit, the correcting unit, and the data processing unit according to the second embodiment.

Fig. 9 is a diagram for explaining an example of the sum calculating unit, the correcting unit, and the data processing unit in the third embodiment.

Detailed Description

[ first embodiment ]

An example of the structure of the product-sum calculator according to the first embodiment will be described with reference to fig. 1 and 2.

Fig. 1 is a diagram showing an example of a partial configuration of a product-sum calculator according to the first embodiment. As shown in fig. 1, the product-sum operator 1 includes: product operation units 111, 121, 211, 221, … …, k11, and k 21; input units 101E, 201E, … …, k 01E; resistors 101Q, 201Q, … …, k 01Q; sum operation units 10S, 20S; correction units (10H, 20H); data processing units 10D and 20D.

Fig. 2 is a diagram showing an example of the variable resistance element according to the first embodiment. The product operation unit 111 is a variable resistance element, for example, a magnetoresistive element shown in fig. 2. As shown in fig. 1 and 2, the product calculation unit 111 includes a variable resistor 111R, a read terminal 111X, a common terminal 111Y, and a write terminal 111Z. The product operation units 121, 211, 221, … …, k11, and k21 shown in fig. 1 are variable resistance elements, and for example, magnetoresistance effect elements similar to the elements shown in fig. 2 each have: variable resistors 121R, 211R, 221R, … …, k11R, k 21R; readout terminals 121X, 211X, 221X, … …, k11X, k 21X; common terminals 121Y, 211Y, 221Y, … …, k11Y, k 21Y; write terminals 121Z, 211Z, 221Z, … …, k11Z, k 21Z. In the following description, the product operation unit 111 is appropriately exemplified, but the same applies to the other product operation units 121, 211, 221, … …, k11, and k 21.

Here, as shown in fig. 2, for example, the variable resistor 111R included in the product operation unit 111 includes: a magnetization pinned layer 1111, a nonmagnetic layer 1112, a first region 1113, a magnetic wall 1114, a second region 1115, a first magnetization supply layer 1116, and a second magnetization supply layer 1117. In the following description using fig. 2, the x-axis, y-axis, and z-axis shown in fig. 2 are used. The x, y and z axes form the three-dimensional orthogonal coordinates of the right-hand system. The magnetization pinned layer 1111, the nonmagnetic layer 1112, the first region 1113, the second region 1115, the first magnetization supply layer 1116, and the second magnetization supply layer 1117 are formed in a thin rectangular parallelepiped shape stacked in the z-axis direction, and the plane having the largest area is parallel to the xy plane, and the first region 1113 and the second region 1115 are electrically and magnetically connected. The magnetization pinned layer 1111, the nonmagnetic layer 1112, the first region 1113, the second region 1115, the first magnetization supply layer 1116, and the second magnetization supply layer 1117 are stacked in this order, but the stacking direction may be the opposite direction. In this case, the positions of the read terminal 111X, the common terminal 111Y, and the write terminal 111Z are also reversed.

The magnetization direction of the magnetization fixed layer 1111 is fixed to the z direction. Here, the fixed magnetization means that the magnetization direction does not change at the time of initialization for introducing the magnetic wall 1114 and before and after writing using a write current. The magnetization pinned layer 1111 may be, for example, an in-plane magnetization film having in-plane magnetic anisotropy or a perpendicular magnetization film having perpendicular magnetic anisotropy.

One surface of the nonmagnetic layer 1112 is in contact with a surface opposite to a surface of the z-direction magnetization fixed layer 1111 in contact with the read terminal 111X. The other surface in the z direction is in contact with the first region 1113 and the second region 1115. The shape and area of the surface facing the z direction side of the magnetization pinned layer 1111 and the surface facing the z direction side of the nonmagnetic layer 1112 may be equal to each other, but the nonmagnetic layer 1112 may be wider in the xy plane so as to cover the first region 1113 and the second region 1115, and may be larger than the magnetization pinned layer 1111. The nonmagnetic layer 1112 is used to read a change in the magnetization state of the product operation unit 111 with respect to the magnetization free layer of the magnetization fixed layer 1111 as a change in the resistance value.

The first region 1113, the magnetic wall 1114, and the second region 1115 form a magnetization free layer. The magnetization free layer is made of a ferromagnetic material, and the magnetization directions of the first region 1113 and the second region 1115 are opposite to each other in the z direction. The magnetic wall 1114 faces in a direction substantially midway between the first region 1113 and the second region 1115. For example, in the case where the magnetization direction of the first region 1113 is fixed to the + z direction, the magnetization fixed layer 1111 and the nonmagnetic layer 1112 are in contact on the surface opposite to the surface in contact in the z direction. On the other hand, when the magnetization direction of the second region 1115 is fixed to the-z direction, the magnetization fixed layer 1111 and the nonmagnetic layer 1112 are in contact with each other on the surface opposite to the surface in contact with each other in the z direction. The magnetic wall 1114 is sandwiched by the first region 1113 and the second region 1115 in the y-direction.

The first magnetization supplying layer 1116 preferably does not overlap with the magnetization pinned layer 1111 in the z direction, and the surface facing the + z direction side is preferably in contact with the surface facing the-z direction side of the first region 1113. The first magnetization supply layer 1116 has a function of fixing the magnetization direction in a range overlapping with the first magnetization supply layer 1116 in the z direction in the first region 1113 to a desired direction. Further, a write terminal 111Z is connected to the surface of the first magnetization supply layer 1116 facing the negative Z direction side. The first magnetization supplying layer 1116 is formed of, for example, a synthetic antiferromagnetic structure (synthetic antiferromagnetic structure) composed of the same ferromagnetic material as that used for the magnetization pinned layer 1111, an antiferromagnetic material such as IrMn, or a ferromagnetic material/nonmagnetic material/ferromagnetic material sandwiching a nonmagnetic intermediate layer such as Ru or Ir.

The second magnetization supplying layer 1117 preferably does not overlap with the magnetization fixed layer 1111 in the z direction, and the surface facing the + z direction side is preferably in contact with the surface facing the-z direction side of the second region 1115. The second magnetization supplying layer 1117 has a function of fixing the magnetization direction of the second region 1115 in a range overlapping with the second magnetization supplying layer 1117 in the z direction to a desired direction. The common terminal 111Y is connected to the surface of the second magnetization supplying layer 1117 facing the negative z direction. The second magnetization supplying layer 1117 is formed of, for example, a synthetic antiferromagnetic structure (synthetic antiferromagnetic structure) composed of the same ferromagnetic material as that used for the magnetization fixed layer 1111, an antiferromagnetic material such as IrMn, or a ferromagnetic material/nonmagnetic material/ferromagnetic material sandwiching a nonmagnetic intermediate layer such as Ru or Ir.

The magnetization direction of the magnetization pinned layer 1111 and the magnetization directions of the first region 1113, the second region 1115, the first magnetization supply layer 1116, and the second magnetization supply layer 1117 in the variable resistor 111R may be not only the z direction but also the x direction and the y direction. In this case, the magnetization direction of the magnetization pinned layer 1111 is preferably the same as the magnetization directions of the first region 1113, the second region 1115, the first magnetization supply layer 1116, and the second magnetization supply layer 1117. For example, when the magnetization direction of the magnetization pinned layer 1111 is the + y direction, the magnetization direction of the first region is the + y direction, the magnetization direction of the second region is the-y direction, the magnetization direction of the first magnetization supplying layer 1116 is the + y direction, and the magnetization direction of the second magnetization supplying layer 1117 is the-y direction.

The product operation unit 111 changes the position of the magnetic wall 1114 in the Y direction by adjusting the magnitude and time of the write current flowing between the common terminal 111Y and the write terminal 111Z. Thus, the product calculation unit 111 can continuously change the ratio of the areas of the regions in which the magnetization directions are parallel to each other and the regions in which the magnetization directions are antiparallel to each other, and can change the resistance value of the variable resistor 111R substantially linearly. Here, the region in which the magnetization directions are parallel is an area of a portion overlapping with the magnetization fixed layer 1111 in the z direction in the first region 1113. In addition, a region where the magnetization directions are antiparallel is an area of a portion overlapping with the magnetization fixed layer 1111 in the z direction in the second region 1115. Further, a write current is input to the write terminal 111Z. The magnitude and time of the write current is adjusted by at least one of the number and width of the current pulses.

The product operation unit 111 may be a tunnel magnetoresistive element. The tunnel magnetoresistance effect element has a magnetization fixed layer, a magnetization free layer, and a tunnel barrier layer as a nonmagnetic layer. The magnetization fixed layer and the magnetization free layer are made of a ferromagnetic material and have magnetization. The tunnel barrier layer is sandwiched between the magnetization fixed layer and the magnetization free layer. The tunnel magnetoresistance effect element can change the resistance value by changing the relationship between the magnetization of the magnetization fixed layer and the magnetization of the magnetization free layer.

Returning to fig. 1, an input unit 101E is connected to the read terminals 111X and 121X via a resistor 101Q. Similarly, an input section 201E is connected to the read terminals 211X and 221X shown in fig. 1 via a resistor 201Q, and an input section k01E is connected to the read terminals k11X and k21X via a resistor k 01Q.

The input unit 101E inputs an input signal corresponding to the input value to the readout terminals 111X and 121X via the resistor 101Q. Similarly, the input unit 201E inputs an input signal corresponding to the input value to the readout terminals 211X and 221X via the resistor 201Q. Similarly, the input unit k01E inputs an input signal corresponding to an input value to the readout terminals k11X and k21X via the resistor k 01Q.

Each of these input signals is a voltage signal subjected to Pulse Width Modulation (PWM) corresponding to an input value, and includes a signal section, a rising section, and a falling section. The signal section is a portion to be used for product-sum operation in the input signal, and is preferably a fixed voltage, but may not necessarily be a fixed voltage. The rising section refers to a portion of the input signal that rises from zero voltage to the voltage level of the signal section. The falling portion refers to a portion of the input signal that falls from the voltage level of the signal portion to zero voltage.

The readout terminals 111X and 121X may be directly connected to the input portion 101E without passing through the resistor 101Q. Similarly, the readout terminals 211X and 221X shown in fig. 1 may be directly connected to the input section 201E without passing through the resistor 201Q. The readout terminals k11X and k21X may be directly connected to the input unit k01E without the resistor k 01Q.

In this case, the input unit 101E inputs an input signal for reducing the rate of change in the voltages of the rising and falling portions to the sense terminals 111X and 121X without passing through the resistor 101Q. Similarly, the input unit 201E inputs, to the sense terminals 211X and 221X, an input signal for reducing the rate of change in the voltages of the rising portion and the falling portion without passing through the resistor 201Q. Similarly, the input section k01E inputs, to the sense terminals k11X and k21X, input signals for reducing the speed of change in the voltages of the rising section and the falling section without passing through the resistor k 01Q.

The product operation unit 111 multiplies the input signal corresponding to the input value by a weight to generate an output signal, and outputs the output signal. That is, the product operation unit 111 reads the signal with the resistance value of the variable resistor 111R as a weight, performs a product operation on the input signal input to the read terminal 111X to generate an output signal, and outputs the output signal from the common terminal 111Y. Similarly, the product operation units 121, 211, 221, … …, k11, and k21 multiply input signals corresponding to input values by weights to generate output signals, respectively, and output the output signals.

The sum operation unit 10S calculates the sum of the output signals output from the product operation units 111, 211, … …, and k11, and outputs the calculation result to the correction unit 10H. Similarly, the sum operation unit 20S calculates the sum of the output signals output from the product operation units 121, 221, … …, and k21, and outputs the calculation result to the correction unit 20H. Details of the sum computation units 10S and 20S will be described later.

The correction section 10H performs correction processing for correcting the sum of the output signals based on a correction value including at least one of the first value and the second value, and outputs the analog signal generated by the correction processing to the data processing section 10D. Here, the first value is a value that is integrated into the sum of the currents flowing into at least one of the variable resistors 111R, 211R, … …, and k11R of the product operation units 111, 211, … …, and k11 due to the rising portion of the input signal. The second value is a value that is integrated into the sum of the currents flowing into at least one of the variable resistors 111R, 211R, … …, and k11R of the product operation units 111, 211, … …, and k11 due to the falling portion of the input signal. The same applies to the correction unit 20H. The correction unit 10H may multiply at least one of the first value and the second value by a weight to execute the correction process. The details of the correction units 10H and 20H will be described later.

The data processing unit 10D converts the analog signal output from the correction unit 10H into a digital signal, performs activation function processing on the digital signal, and converts the digital signal into an analog signal again. Similarly, the data processing unit 20D converts the analog signal output from the correction unit 20H into a digital signal, performs activation function processing on the digital signal, and converts the digital signal into an analog signal again. Details of the data processing units 10D and 20D will be described later.

Next, an example of a method of calculating the sum total by the product-sum calculator according to the first embodiment will be described with reference to fig. 3 to 6.

Fig. 3 is a diagram showing an example of an equivalent circuit of a partial configuration of the product-sum calculator according to the first embodiment. As shown in fig. 3, the product operation unit 111 has an equivalent circuit in which a parasitic capacitance 111C and a parasitic resistance 111P are variable resistors, and it is conceivable that the parasitic capacitance 111C is connected in parallel with the variable resistor 111R and the parasitic resistance 111P is connected in series with the variable resistor 111R. Similarly, the product operation units 121, 211, 221, … …, k11, and k21 each include: parasitic capacitances 121C, 211C, 221C, … …, k11C, k 21C; parasitic resistances 121P, 211P, 221P, … …, k11P, k 21P. It is also conceivable that the line resistances 111W, 121W, 211W, 221W, … …, k11W, and k21W are connected in series to the product operation units 111, 121, 211, 221, … …, k11, and k21, respectively.

Fig. 4 is a diagram showing an example of an inrush current when an input signal and an input signal pass through the product operation unit 111 according to the first embodiment. The input unit 101E outputs an input signal subjected to pulse width modulation, for example, an input signal VA shown in fig. 4 (a). The input signal VA has a signal section, a rising section, and a falling section. The rising portion of the input signal VA is a portion that rises substantially vertically from the zero voltage to the voltage level of the signal portion at time t 1. The signal section is a section from immediately after time t1 to immediately after time t4, and the length of the section corresponds to the input value. The drop-down section is a section that drops from zero voltage to substantially vertically the voltage level of the signal section at time t 4.

If the input signal VA shown in fig. 4 (a) is directly input to the sense terminal 111X of the product operation unit 111 without passing through the resistor 101Q, inrush currents IA1 and IA2 shown in fig. 4 (b) occur. The inrush current IA1 is generated by charging the parasitic capacitance 111C of the product operation unit 111 due to the rising portion of the input signal VA. The inrush current IA2 is generated by discharge from the parasitic capacitance 111C of the product operation unit 111 due to the falling portion of the input signal VA.

As shown in fig. 4 (a), the rise portion and the fall portion have a short time, and thus, the inrush currents IA1 and IA2 shown in fig. 4 (b) disappear in a short time. The inrush currents IA1 and IA2 flow into the parasitic capacitance 111C of the product operation unit 111 mostly and the variable resistance 111R of the product operation unit 111 in the remaining part. Therefore, when the input signal VA is directly input to the read terminal 111X of the product operation unit 111 without passing through the resistor 101Q, the variation in the sum of the output signals calculated by the sum operation unit 10S due to the inrush currents IA1 and IA2 is extremely small.

However, the generation of the inrush currents IA1 and IA2 may cause heat generation of the product-sum calculator 1, generation of an erroneous operation due to the heat generation, and an increase in load on the product-sum calculator 1. Further, when the inrush currents IA1 and IA2 become large, the capacitance of the capacitor for accumulating the electric charge due to the output signal may need to be increased. Therefore, in order to suppress the occurrence of inrush currents IA1 and IA2, an input signal VC shown in fig. 4 (c), for example, is input to the product operation unit 111.

The input signal VC shown in (c) in fig. 4 is generated in the case where the input signal VA shown in (a) in fig. 4 is passed through the resistor 101Q, for example. That is, the resistor 101Q lengthens the time of the rising portion and the falling portion of the input signal VA, and shortens the time of the signal portion of the input signal VA. The input signal VC has a signal section, a rising section, and a falling section. The rising portion of the input signal VC is a portion in which the voltage rises from zero voltage to the voltage level of the signal portion in the interval from time t1 to time t 2. The signal section is a section from time t2 to time t3, and the length of the section corresponds to the input value. The falling section is a section from time t3 to time t4, that is, a section where the voltage level of the signal section falls to zero voltage.

When the input signal VC shown in fig. 4 (c) is input to the read terminal 111X of the product operation unit 111, the inrush currents ID1 and ID2 shown in fig. 4 (d) occur. The inrush current ID1 is generated by charging the parasitic capacitance 111C of the product operation unit 111 due to the rising portion of the input signal VC. The inrush current ID2 is generated by the discharge from the parasitic capacitance 111C of the product operation unit 111 due to the falling portion of the input signal VA.

As shown in fig. 4 (c), the time for the rising portion and the falling portion of the input signal VC are longer than the time for the rising portion and the falling portion of the input signal VA shown in fig. 4 (a), and therefore, the inrush currents ID1 and ID2 shown in fig. 4 (d) are smaller than the inrush currents IA1 and IA2 shown in fig. 4 (b). Therefore, by inputting the input signal VC to the product operation unit 111, it is possible to reduce the capacitance of the capacitor for storing the electric charge caused by the output signal while reducing the inrush current by suppressing the generation of heat generation in the product-sum operation unit 1, the occurrence of malfunction associated with heat generation, and the increase in load on the product-sum operation unit 1.

However, as shown in fig. 4 (a) and 4 (c), the occurrence time of the inrush currents ID1 and ID2 is longer than that of the inrush currents IA1 and IA2, and therefore the ratio of the variable resistor 111R flowing into the product calculation unit 111 is larger than that of the inrush currents IA1 and IA 2. Therefore, when the input signal VC shown in (c) of fig. 4 is input to the read terminal 111X of the product operation unit 111, the sum of the output signals calculated by the sum operation unit 10S may be deviated by the inrush currents ID1 and ID 2.

The same applies to the product operation units 121, 211, 212, … …, k11, k21 and the sum operation unit 20S, which are described with reference to fig. 4.

Therefore, the product-sum operator 1 corrects the sum of output signals that are deviated by the rising part and the falling part of the input signal VC by a method described below.

Fig. 5 is a diagram showing an example of the correction input signal according to the first embodiment. Input unit 101E inputs a predetermined signal to resistor 101Q, and thereby inputs correction input signal VH shown in fig. 5 to read terminals 111X and 121X. Similarly, the input unit 201E inputs a predetermined signal to the resistor 201Q, and thereby inputs the correction input signal VH shown in fig. 5 to the readout terminals 211X and 221X. Similarly, the input unit k01E inputs a predetermined signal to the resistor k01Q, thereby inputting the correction input signal VH shown in fig. 5 to the readout terminals k11X and k 21X.

The correction input signal VH has a rising portion and a falling portion. Specifically, as shown in fig. 5, the correction input signal VH is included in the section from time t10 to time t20, and rises from zero voltage to the voltage level of the signal portion of the input signal VC shown in (c) in fig. 4. The inclination and time of the rising portion of the correction input signal VH are equal to those of the rising portion of the input signal VC shown in (c) of fig. 4. The correction input signal VH is included in a section from time t20 to time t30, and is a drop section for dropping the voltage level of the signal section of the input signal VC shown in (c) in fig. 4 to zero voltage. The inclination and time of the falling portion of the correction input signal VH are equal to those of the falling portion of the input signal VC shown in (c) of fig. 4.

Since the area of the rising portion of the correction input signal VH corresponds to the first value included in the correction value used by the correction unit 10H in the above-described correction processing, the area of the rising portion of the input signal VC is preferably closer to the area of the rising portion shown in fig. 4 (c). Similarly, since the area of the drop portion of the correction input signal VH corresponds to the second value included in the correction value used by the correction unit 10H in the above-described correction processing, the area of the drop portion of the input signal VC is preferably closer to the area of the drop portion shown in fig. 4 (c).

The product operation unit 111 multiplies the correction input signal VH by a weight to generate a correction output signal, and outputs the correction output signal. That is, the product operation unit 111 reads the correction input signal VH input to the read terminal 111X by using the resistance value of the variable resistor 111R as a weight, performs a product operation to generate a correction output signal, and outputs the correction output signal from the common terminal 111Y. Similarly, the product operation units 121, 211, 221, … …, k11, and k21 multiply the correction input signal VH by a weight to generate a correction output signal, and output the correction output signal.

The sum operation unit 10S calculates the sum of the correction output signals output from the product operation units 111, 211, … …, and k11, and outputs the calculation result to the correction unit 10H. The correction unit 10H sets the sum obtained by the calculation as a correction value, and executes a correction process of subtracting the correction value from the sum of the output signals output from the product calculation units 111, 211, … …, and k11, respectively. Similarly, the sum operation unit 20S calculates the sum of the correction output signals output from the product operation units 121, 221, … …, and k21, and outputs the calculation result to the correction unit 20H. The correction unit 20H sets the sum obtained by the operation as a correction value, and executes a correction process of subtracting the correction value from the sum of the output signals output from the product operation units 121, 221, … …, and k21, respectively.

Further, the correction values obtained by inputting the correction input signal VH shown in fig. 5 to the product operation units 111, 121, 211, 221, … …, k11, and k21 may be stored in the correction value storage unit. The correction value storage unit is a storage medium that stores a correction value.

Next, a specific example of the sum operation unit, the correction unit, and the data processing unit included in the product-sum calculator 1 will be described with reference to fig. 6. Fig. 6 is a diagram for explaining an example of the sum calculating unit, the correcting unit, and the data processing unit according to the first embodiment. In the following description, the sum operation unit 10S, the correction unit 10H, and the data processing unit 10D are described as an example, but the same applies to the sum operation unit 20S, the correction unit 20H, and the data processing unit 20D.

As shown in fig. 6, the sum operation unit 10S includes a capacitor 101S, a comparator 102S, and a reference voltage generation circuit 103S. One terminal of the capacitor 101S is connected to the common terminals 111Y, 211Y, … …, and k11Y of the product operation units 111, 211, … …, and k11, respectively, and the inverting input terminal of the comparator 102S, and the other terminal is connected to the output terminal of the comparator 102S. The capacitor 101S stores electric charges due to the output signals output from the product operation units 111, 211, … …, and k11, respectively. The comparator 102S reads the voltage of the capacitor 103 using the reference voltage supplied from the reference voltage generation circuit 103S connected to the non-inverting input terminal, and outputs the voltage to the correction unit 10H. The voltage read here is the sum of the output signals output from the product operation units 111, 211, … …, and k11, respectively.

As shown in fig. 6, the correction unit 10H includes a comparator 102H and a correction voltage generation circuit 103H. The non-inverting input terminal of the comparator 102H is connected to the output terminal of the comparator 102S, the inverting input terminal is connected to the correction voltage generation circuit 103H, and the output terminal is connected to the data processing unit 10D. The comparator 102H corrects the sum of the output signals corrected by the correcting unit 10H using the correction voltage supplied from the correction voltage generating circuit 103H. That is, the correction voltage is determined based on the correction value including the first value and the second value.

As shown in fig. 6, the data processing unit 10D includes: an analog-digital conversion circuit 101D, an activation function processing circuit 102D, and a digital-analog conversion circuit 103D. The analog-digital conversion circuit 101D converts an analog signal indicating the sum of the output signals corrected by the correction section 10H into a digital signal. The activation function processing circuit 102D performs activation function processing on the digital signal. The digital-analog converter circuit 103D converts the digital signal subjected to the activation function processing into an analog signal. The analog signal is output to, for example, another product-sum operator.

The product-sum calculator 1 separately generates a reference voltage for reading the voltage of the capacitor 101S and a correction voltage for correcting the sum of the output signals corrected by the correction unit 10H by using the sum calculation unit 10S, the correction unit 10H, and the data processing unit 10D shown in fig. 6. Therefore, the product-sum calculator 1 can generate an accurate correction voltage and accurately correct the sum of the output signals output from the product calculation units 111, 211, … …, and k 11.

Next, an example of the neural network operation performed by the product-sum calculator according to the first embodiment will be described with reference to fig. 7. Fig. 7 is a diagram for explaining an example of the neural network operation performed by the product-sum calculator according to the first embodiment.

Nodes 101, 201, … …, k01 form the input layer. The sensors 10, 20 form a hidden layer or an output layer. The node 101 corresponds to the input unit 101E shown in fig. 1 and 3, and outputs an input value corresponding to an input signal to the sensors 10 and 20. Similarly, the nodes 201, … …, and k01 correspond to the input units 201E, … …, and k01E, respectively, and output input values corresponding to input signals to the sensors 10 and 20.

Arrow 111A corresponds to product operation unit 111, and indicates that the input value output to node 101 is multiplied by a weight, and a value corresponding to the output signal is input to sensor 10. Similarly, arrow 121A corresponds to product operation unit 121, and indicates that the input value output to node 101 is multiplied by a weight, and a value corresponding to the output signal is input to sensor 20. The same applies to arrows 211A, 221A, … …, k11A, and k 21A.

The sensor 10 corresponds to the sum computation unit 10S, the correction unit 10H, and the data processing unit 10D shown in fig. 1 and 3, computes the sum of values input from the arrows 111A, 211A, … …, and k11A, executes the above-described correction processing, and applies activation function processing to the sum subjected to the correction processing and outputs the sum. Similarly, the sensor 20 corresponds to the sum computation unit 20S, the correction unit 20H, and the data processing unit 20D shown in fig. 1 and 3, computes the sum of the values input from the arrows 121A, 221A, … …, and k21A, performs the above-described correction processing, and performs activation function processing on the sum subjected to the correction processing and outputs the sum.

The product-sum calculator 1 according to the first embodiment is explained above. The product-sum operator 1 corrects the sum of the output signals based on a correction value including at least one of a first value and a second value, wherein the first value is a value incorporated in the sum by a current flowing into at least one variable resistor of the product operation section 111, 121, 211, 221, … …, k11, k21 caused by a rising section of the input signal VC, and the second value is a value incorporated in the sum by a current flowing into at least one variable resistor of the product operation section 111, 121, 211, 221, … …, k11, k21 caused by a falling section of the input signal VC. Thus, the product-sum calculator 1 can correct a deviation of the sum total of the output signals due to at least one of the rising portion and the falling portion of the input signal VC, and perform an accurate product-sum calculation.

At least one of the product operation units 111, 121, 211, 221, … …, k11, and k21 includes a magnetoresistance effect element exhibiting a magnetoresistance effect. Since the parasitic capacitance of the magnetoresistive element is larger than that of the other variable resistive elements, it is particularly necessary to reduce the speed of change in the voltage of the rising portion and the falling portion of the input signal and to alleviate the heat generation of the circuit and the load of the circuit due to the inrush current. Therefore, when at least one of the product operation units 111, 121, 211, 221, … …, k11, and k21 includes a magnetoresistance effect element, an effect achieved by using a correction value including at least one of the first value and the second value is particularly useful.

The product calculation unit 111 includes: read terminal 111X, common terminal 111Y, and write terminal 111Z. Thus, the product-sum calculator 1 is affected by the parasitic capacitance 111C only when product-sum calculation is performed, and can change the resistance value of the variable resistance 111R without being affected by the parasitic capacitance 111C when the write current flows between the common terminal 111Y and the write terminal 111Z. Similarly, the product arithmetic units 121, 211, 221, … …, k11, and k21 are also similar.

The product-sum calculator 1 inputs correction input signals VH having an up-converter and a down-converter to the product-sum calculator 111, 121, 211, 221, … …, k11, and k21, multiplies the correction input signals by weights to generate correction output signals, and performs correction processing using the sum of the correction output signals as a correction value. Thereby, the product-sum operator 1 can generate an accurate correction value, and therefore, an accurate product-sum operation can be performed.

The product-sum operator 1 inputs the input signals to the product operation units 111, 121, 211, 221, … …, k11, and k21 via the resistors 101Q, 201, … …, and k01Q, respectively. Thus, even if the rising portion and the falling portion of the input signal VA are steep, the product-sum calculator 1 can reduce the rate of change in the voltages of the rising portion and the falling portion, execute the correction processing using the correction value including at least one of the first value and the second value, and execute the accurate product-sum calculation.

Instead of the resistors 101Q, 201Q, … …, and k01Q, the product-sum calculator 1 may include resistors before the readout terminals 111X, 121X, 211X, 221X, … …, k11X, and k21X of the product calculation unit. The function of the resistor is similar to that of the resistors 101Q, 201Q, … …, k 01Q.

[ second embodiment ]

An example of the structure of the product-sum calculator according to the first embodiment will be described with reference to fig. 8. The product-sum calculator of the second embodiment differs from the product-sum calculator 1 of the first embodiment in the specific configurations of the sum calculator 10S, the corrector 10H, and the data processor 10D described with reference to fig. 6. Therefore, in the description of the second embodiment, only the differences from the first embodiment will be described, and redundant description will be omitted.

Fig. 8 is a diagram for explaining an example of the sum calculating unit, the correcting unit, and the data processing unit according to the second embodiment. As shown in fig. 8, the product-sum calculator of the second embodiment includes: a capacitor 1011S, a comparator 1021S, a voltage generation circuit 1031H, and a data processing unit 10D. The data processing unit 10D is the same as the first embodiment.

One terminal of the capacitor 1011S is connected to the common terminals 111Y, 211Y, … …, and k11Y of the product operation units 111, 211, … …, and k11, respectively, to the inverting input terminal of the comparator 1021S, and the other terminal is connected to the output terminal of the comparator 1021S. The capacitor 1011S stores electric charges caused by the output signals output from the product operation units 111, 211, … …, and k11, respectively. The comparator 1021S reads the voltage of the capacitor 1011S using the reference voltage and the correction voltage supplied from the voltage generation circuit 1031H connected to the non-inverting input terminal. Here, since the comparator 1021S supplies not only the reference voltage but also the correction voltage, the comparator 1021S reads the voltage subjected to the correction processing by the correction value.

Therefore, the product-sum calculator of the second embodiment can reduce the circuit scale by combining the comparator used for calculating the sum of the output signals and the comparator used for correcting the sum into one.

[ third embodiment ]

An example of the structure of the product-sum calculator according to the first embodiment will be described with reference to fig. 9. The product-sum operator of the third embodiment performs the correction process using a digital circuit, unlike the product-sum operator 1 of the first embodiment and the product-sum operator of the second embodiment that perform the correction process using an analog circuit. Therefore, in the description of the third embodiment, only the differences from the first and second embodiments will be described, and redundant description will be omitted.

Fig. 9 is a diagram for explaining an example of the sum calculating unit, the correcting unit, and the data processing unit in the third embodiment. As shown in fig. 9, the product-sum calculator of the third embodiment includes: and operation unit 10S, analog-to-digital conversion circuit 1011D, correction value storage unit 1032H, operation circuit 1033H, activation function processing circuit 1021D, and digital-to-analog conversion circuit 1031D. The sum arithmetic unit 10S is the same as the first embodiment.

The analog-digital conversion circuit 1011D converts an analog signal representing the sum of the output signals output from the sum operation unit 10S into a digital signal. The correction value storage unit 1032H is a storage medium that stores the correction value as digital data. The arithmetic circuit 1033H acquires the correction value from the correction value storage section 1032H, subtracts the correction value from the sum of the output signals converted into digital signals, and outputs the result. The activation function processing circuit 1021D performs activation function processing on the digital signal. The digital-analog conversion circuit 1031D converts the digital signal subjected to the activation function processing into an analog signal.

Therefore, the product-sum arithmetic unit according to the third embodiment can execute the above-described correction processing by adding the correction value storage unit 1032H and the arithmetic circuit 1033H only to the product-sum arithmetic unit that is an already used analog circuit. Further, since the product-sum calculator of the third embodiment stores the correction value in the correction value storage unit 1032H, it is not necessary to calculate the correction value when the above-described correction processing is executed. In addition, the product-sum calculator of the third embodiment includes the correction value storage unit 1032H outside the correction unit, and thus can execute the correction processing based on the correction value while suppressing an increase in the circuit scale of the correction unit. Since the number of correction units is smaller than the number of product operation units, the product-sum operation unit according to the third embodiment does not need to increase the storage capacity of the correction value storage unit 1032H.

The product-sum calculator 1 may be included in a logical operation device or a neuromorphic device. The logical operation device herein is a logical circuit formed by combining a plurality of product-sum operators 1, such as an AND circuit, an or circuit. The logical operation described here is a concept including deep learning. The neuromorphic device is a device to which the structure of the brain and the tissue of firing of nerve cells serving as neurons are applied, and is used for machine learning and the like.

Further, a program for realizing the functions of each device such as the product-sum calculator 1 according to the first embodiment may be recorded in a computer-readable recording medium, and the program recorded in the recording medium may be read and executed by a computer system to perform the processing.

The computer System described herein may include hardware such as an Operating System (OS) and peripheral devices. The computer-readable recording medium includes, for example, a medium that holds a program for a certain period of time, such as a flexible disk, a magneto-optical disk, a writable nonvolatile memory such as a rom (read Only memory) or a flash memory, a portable medium such as a dvd (digital Versatile disc), a storage device such as a hard disk incorporated in a computer system, or a volatile memory in a computer system serving as a client or a server when the program is transmitted via a network or a communication line.

The program may be transmitted from a computer system storing the program in a storage device or the like to another computer system via a transmission medium or by a transmission wave in the transmission medium. Here, the transmission medium for transmitting the program refers to a medium having a function of transmitting information, such as a network such as the internet or a communication line such as a telephone line.

The program may be a program for realizing a part of the above-described functions, or a program that can be realized by combining the above-described functions with a program that has been recorded in a computer system, so-called differential program. The program is read out and executed by a processor such as a cpu (central Processing unit) included in a computer.

While the first embodiment of the present invention has been described in detail with reference to the drawings, the specific configuration is not limited to the first embodiment, and various modifications and substitutions can be made without departing from the spirit of the present invention. The configurations described in the first embodiments may be combined.

Description of the symbols

1 … product arithmetic unit, 111, 121, 211, 221, k11, k21 … product arithmetic unit, 111R, 121R, 211R, 221R, k11, 11R, k21R … variable resistance, 10S, 20S … and arithmetic unit, 10H, 20H … correction unit.