阅读说明：本技术 四结太阳能电池及其制备方法 (Four-junction solar cell and preparation method thereof ) 是由 王俊 占荣 李华 王伟明 于 2019-09-26 设计创作，主要内容包括：一种四结太阳能电池及其制备方法,四结太阳能电池,包括依次层叠的各结子电池,各结子电池自下而上包括：Ge子电池；InGaAs子电池；InAlGaAs子电池；以及InAlGaP子电池；其中,所述InAlGaP子电池为入光侧,所述Ge子电池为背光侧。该四结太阳能电池仅需通过一次外延生长便可得到各结子电池,并且其能量转化效率接近理论极限,不需要现有技术中进行二次外延或者倒装剥离等复杂的制备工艺,有助于实现量产。(A four-junction solar cell and a preparation method thereof are provided, the four-junction solar cell comprises all junction sub-cells which are sequentially stacked, and each junction sub-cell comprises from bottom to top: a Ge sub-battery; an InGaAs sub-cell; an InAlGaAs sub-cell; and an InAlGaP subcell; the InAlGaP sub-cell is a light incident side, and the Ge sub-cell is a backlight side. The four-junction solar cell can obtain each junction sub-cell only through one-time epitaxial growth, the energy conversion efficiency of the four-junction solar cell is close to the theoretical limit, complex preparation processes such as secondary epitaxy or flip-chip stripping in the prior art are not needed, and the four-junction solar cell is beneficial to realizing mass production.)

1. The utility model provides a four knot solar cell which characterized in that, includes each knot sub-cell that stacks gradually, and each knot sub-cell includes from bottom to top:

a Ge sub-cell (100);

an InGaAs sub-cell (200);

an InAlGaAs sub-cell (300); and

an InAlGaP subcell (400);

the InAlGaP sub-cell (400) is a light incident side, and the Ge sub-cell (100) is a backlight side.

2. The four-junction solar cell of claim 1, wherein a tunnel junction is disposed between each two adjacent subcells;

optionally, an ohmic contact layer (500) is disposed on the InAlGaP subcell (400).

3. The quadruple junction solar cell according to claim 2, characterized in that there is a first lattice strain layer (11) between the Ge subcell (100) and the InGaAs subcell (200), and a second lattice strain layer (31) between the inalgaa subcell (300) and the InAlGaP subcell (400).

4. The quadruple junction solar cell according to claim 3, characterized in that the tunnel junctions between the Ge sub-cell (100) and the InGaAs sub-cell (200), between the InGaAs sub-cell (200) and the InAlGaAs sub-cell (300) and between the InAlGaAs sub-cell (300) and the InAlGaP sub-cell (400) are a first tunnel junction (12), a second tunnel junction (22) and a third tunnel junction (32), respectively, the first lattice strain layer (11) being interchangeable with the first tunnel junction (12) in the up-down order; the second lattice strain layer (31) is interchangeable with the third tunnel junction (32) in the vertical order.

5. The four-junction solar cell of claim 2,

the tunnel junction is made of one or more of the following materials: GaAs, InGaP, Al_0.3Ga_0.7As; and/or the presence of a gas in the gas,

the doping concentration of the current carrier in the tunnel junction reaches 1 multiplied by 10¹⁹cm^-3The above.

6. The four-junction solar cell of claim 3,

the materials of the first lattice strain layer (11) and the second lattice strain layer (31) are one or more of the following semiconductor materials: InGaAs, InAlGaAs, InAlGaP, or InGaP.

7. The four-junction solar cell of claim 1,

the band gap width of the InGaAs sub-cell (200) is 1.0eV-1.2 eV;

the band gap width of the InAlGaAs sub-cell (300) is 1.3eV-1.5 eV;

the InAlGaP subcell (400) has a band gap width of 1.8eV to 2.2 eV.

8. The four-junction solar cell of claim 1,

the Ge sub-cell (100) comprises:

a p-Ge single crystal substrate-cum-base region (111),

an n-Ge emitter region (112) and

an n-GaInP window layer (113);

optionally, the InGaAs subcell (200) includes:

an InAlGaAs or AlGaInP back electric field layer (211),

a p-InGaAs base region (212),

an n-InGaAs emitter region (213) and

an n-AlInP window layer (214);

optionally, the inalgas subcell (300) includes:

Al_0.7Ga_0.3an As or AIGaInP back electric field layer (311),

a p-InAlGaAs base region (312),

an n-InGaP emitter region (313) and

an n-AlInP window layer (314);

optionally, the InAlGaP subcell (400) comprises:

Al_0.7Ga_0.3an As or AlGaInP back electric field layer (411),

a p-InAlGaP base region (412),

an n-InAlGaP emitter region (413) and

an n-AlInP window layer (414).

9. The four-junction solar cell of claim 8,

in the Ge sub-battery (100), the thickness of the p-Ge single crystal substrate and base region (111) is 110-140 μm, and the doping concentration is 0.5 multiplied by 10¹⁷～1×10¹⁷m^-3To (c) to (d); the n-Ge emitter region (112) has a thickness of 0.05 μm to 0.1 μm and a doping concentration of 0.5 × 10¹⁸～1×10¹⁸m^-3To (c) to (d);

optionally, in the InGaAs sub-cell (200), the thickness of the p-InGaAs base region (212) is 1 μm to 1.5 μm, and the doping concentration is between 0.5 × 10¹⁷～1×10¹⁷m^-33To (c) to (d);

optionally, in the InAlGaAs sub-cell (300), Al_0.7Ga_0.3The thickness of the As or AlGaInP back electric field layer (311) is 0.1-0.2 μm; the thickness of the p-InAlGaAs base region (312) is 0.08-0.15 μm, and the doping concentration is 0.5 multiplied by 10¹⁸～1×10¹⁸m^-3To (c) to (d); the thickness of the n-InGaP emitting region (313) is 1.0-1.6 μm, and the doping concentration is 1 × 10¹⁷～3×10¹⁷m^-3To (c) to (d);

optionally, in the InAlGaP subcell (400), Al_0.7Ga_0.3The thickness of the As or AlGaInP back electric field layer (411) is 0.1-0.2 μm; the thickness of the p-InAlGaP base region (412) is 0.08-0.15 μm, and the doping concentration is between 0.5 x 10¹⁸～1×10¹⁸m^-3To (c) to (d); the thickness of the n-InAlGaP emitting region (413) is 1.0-1.6 μm, and the doping concentration is 1 × 10¹⁷～3×10¹⁷m^-3In the meantime.

10. A method for fabricating a four-junction solar cell, comprising:

sequentially epitaxially growing a Ge sub-battery (100), an InGaAs sub-battery (200) and an InAlGaAs sub-battery (300); and an InAlGaP subcell (400);

the InAlGaP sub-cell (400) is a light incident side, and the Ge sub-cell (100) is a backlight side;

optionally, after the epitaxial growth of the Ge subcell (100) and before the epitaxial growth of the InGaAs subcell (200), further comprising: a step of growing a first tunnel junction (12) and a first lattice-strained layer (11) using a lattice-grading technique;

optionally, after the epitaxially growing the InGaAs subcell (200) and before the epitaxially growing the inalgas subcell (300), further comprising: a step of growing a second tunnel junction (22);

optionally, after the epitaxially growing the inalgas subcell (300) and before the epitaxially growing the InAlGaP subcell (400), further comprising: growing a third tunnel junction (32) and growing a second lattice-strained layer (31) using a lattice-grading technique.

Technical Field

The disclosure belongs to the technical field of solar power generation, and relates to a four-junction solar cell and a preparation method thereof.

Background

In the current multi-junction solar cell, a Ge/GaInAs/GaInP three-junction solar cell is increasingly applied due to high photoelectric conversion efficiency, and particularly widely applied in the space efficient cell industry. However, researchers have been trying to further improve the photoelectric conversion efficiency of solar cells. The development from three junctions to four, five and even higher junctions is an important direction.

However, in the existing multi-junction solar cell, the problems of complex process and high difficulty in the preparation process often exist in the structure design capable of realizing high conversion efficiency, the problem of band gap design limitation exists in some structures, and the energy conversion efficiency is often difficult to approach the theoretical limit value.

In the prior art, the preparation process of a multi-junction solar cell is complex, some researches propose a flip-chip four-junction cascade solar cell, a first substrate is made of GaAs, a GaInP sub cell, a GaAs sub cell, an InGaAlAs sub cell and an InGaAs sub cell are sequentially flip-chip epitaxial, Eg is respectively 1.90eV, 1.42eV, 1.00eV and 0.73eV, and finally the flip-chip four-junction cell is peeled off and then is bonded to a second substrate Si substrate to be in electrode contact with the second substrate Si substrate.

Some researches propose a four-junction solar cell, wherein a GaInP sub-cell, a GaAs sub-cell and an InGaNAsBi sub-cell are arranged on the upper surface of a double-side polished GaAs substrate, and a quantum dot structure sub-cell is arranged on the lower surface of the GaAs substrate, and the band gap combinations of the four-junction solar cell are 1.90eV, 1.42eV, 1.00eV and 0.70 eV. Epitaxy is complicated and requires two epitaxy processes.

Disclosure of Invention

Technical problem to be solved

The present disclosure provides a four-junction solar cell and a method for manufacturing the same to at least partially solve the above-mentioned technical problems.

(II) technical scheme

According to an aspect of the present disclosure, there is provided a four-junction solar cell, including respective junction sub-cells stacked in sequence, each junction sub-cell including, from bottom to top: a Ge sub-cell 100; an InGaAs subcell 200; an InAlGaAs sub-cell 300; and an InAlGaP subcell 400; the InAlGaP subcell 400 is the light incident side, and the Ge subcell 100 is the backlight side.

In one embodiment, a tunnel junction is disposed between every two adjacent sub-cells.

In one embodiment, an ohmic contact layer 500 is disposed on the InAlGaP subcell 400.

In one embodiment, a first lattice strain layer 11 is disposed between the Ge subcell 100 and the InGaAs subcell 200, and a second lattice strain layer 31 is disposed between the InAlGaAs subcell 300 and the InAlGaP subcell 400.

In one embodiment, the tunnel junctions between the Ge sub-cell 100 and the InGaAs sub-cell 200, between the InGaAs sub-cell 200 and the inalgas sub-cell 300, and between the inalgas sub-cell 300 and the InAlGaP sub-cell 400 are a first tunnel junction 12, a second tunnel junction 22, and a third tunnel junction 32, respectively, and the first lattice strain layer 11 and the first tunnel junction 12 can be exchanged in the vertical sequence; the second lattice strain layer 31 is interchangeable with the third tunnel junction 32 in the top-bottom order.

In one embodiment, the material of the tunnel junction is one or more of the following materials: GaAs, InGaP, Al_0.3Ga_0.7As; and/or the ion doping concentration in the tunnel junction reaches 1 x 10¹⁹cm^-3The above.

In an embodiment, the material of the first lattice strain layer 11 and the second lattice strain layer 31 is one or more of the following semiconductor materials: InGaAs, InAlGaAs, InAlGaP, or InGaP.

In one embodiment, the band gap width of the InGaAs subcell 200 is 1.0eV to 1.2 eV; the band gap width of the InAlGaAs sub-battery 300 is 1.3eV-1.5 eV; the band gap width of the InAlGaP subcell 400 is 1.8eV-2.2 eV.

In one embodiment, the Ge sub-cell 100 includes: a p-Ge single crystal substrate and base region 111, an n-Ge emitter region 112, and an n-GaInP window layer 113;

optionally, the InGaAs subcell 200 includes: an InAlGaAs or AlGaInP back electric field layer 211, a p-InGaAs base region 212, an n-InGaAs emitter region 213 and an n-AlInP window layer 214;

optionally, the inalgas subcell 300 includes: al (Al)_0.7Ga_0.3An As or AlGaInP back electric field layer 311, a p-InAlGaAs base region 312, an n-InGaP emitter region 313 and an n-AlInP window layer 314;

optionally, the InAlGaP seedThe battery 400 includes: al (Al)_0.7Ga_0.3An As or AlGaInP back electric field layer 411, a p-InAlGaP base region 412, an n-InAlGaP emitter region 413, and an n-AlInP window layer 414.

In one embodiment, in the Ge sub-cell 100, the thickness of the p-Ge single-crystal substrate and base region 111 is 110 μm to 140 μm, and the doping concentration is between 0.5 × 10¹⁷～1×10¹⁷m^-3To (c) to (d); the n-Ge emitter region 112 has a thickness of 0.05-0.1 μm and a doping concentration of 0.5 × 10¹⁸～1×10¹⁸m^-3To (c) to (d);

optionally, in the InGaAs subcell 200, the thickness of the p-InGaAs base region 212 is 1 μm to 1.5 μm, and the doping concentration is between 0.5 × 10¹⁷～1×10¹⁷m^-33To (c) to (d);

optionally, in the inalgas sub-cell 300, Al_0.7Ga_0.3The thickness of the As or AlGaInP back electric field layer 311 is 0.1-0.2 μm; the thickness of the p-InAlGaAs base region 312 is 0.08-0.15 μm, and the doping concentration is 0.5 multiplied by 10¹⁸～1×10¹⁸m^-3To (c) to (d); the thickness of the n-InGaP emitting region 313 is 1.0 μm-1.6 μm, and the doping concentration is between 1 × 10¹⁷～3×10¹⁷m^-3To (c) to (d);

optionally, in the InAlGaP subcell 400, Al_0.7Ga_0.3The thickness of the As or A1GaInP back electric field layer 411 is 0.1-0.2 μm; the thickness of the p-InAlGaP base region 412 is 0.08-0.15 μm, and the doping concentration is between 0.5 x 10¹⁸～1×10¹⁸m^-3To (c) to (d); the thickness of the n-InAlGaP emitting region 413 is 1.0-1.6 μm, and the doping concentration is 1 × 10¹⁷～3×10¹⁷m^-3In the meantime.

According to another aspect of the present disclosure, there is provided a method of fabricating a four-junction solar cell, including: sequentially epitaxially growing a Ge sub-battery 100, an InGaAs sub-battery 200 and an InAlGaAs sub-battery 300; and an InAlGaP subcell 400; the InAlGaP subcell 400 is the light incident side, and the Ge subcell 100 is the backlight side.

Optionally, after the epitaxial growth of the Ge subcell 100 and before the epitaxial growth of the InGaAs subcell 200, further comprising: a step of growing a first tunnel junction 12 and a first lattice strain layer 11 using a lattice grading technique;

optionally, after epitaxially growing the InGaAs subcell 200 and before epitaxially growing the InAlGaAs subcell 300, further comprising: a step of growing the second tunnel junction 22;

optionally, after the epitaxial growth of the inalgas subcell 300 and before the epitaxial growth of the InAlGaP subcell 400, further comprising: a step of growing a third tunnel junction 32 and a second lattice-strained layer 31 using a lattice-grading technique.

(III) advantageous effects

According to the technical scheme, the four-junction solar cell and the preparation method thereof have the following beneficial effects:

(1) according to the standard AM0 spectrum, the band gaps of the four-junction cell can obtain the optimal conversion efficiency respectively at 0.7eV, 1.0eV, 1.4eV and 1.9eV, but in the actual material growth process, four materials matched with lattices can not be found to have the band gap structure, and the ideal four-junction band gap is realized by adopting a secondary lattice buffer layer technology;

(2) the first lattice strain layer is arranged between the Ge sub-battery and the InGaAs sub-battery, the second lattice strain layer is arranged between the InAlGaAs sub-battery and the InAlGaAs sub-battery, and the lattice strain layer is beneficial to realizing theoretical design requirements of band gaps of the Ge sub-battery, the InGaAs sub-battery and the InAlGaAs sub-battery under the adjustment of the first lattice strain layer, but if the InAlGaAs sub-battery is matched with InAlGaAs lattices, the band gap can not realize 1.9eV, so that the second lattice strain layer technology is adopted, the optimal band gap design is realized, and the actual conversion efficiency of battery conversion exceeds 34%;

(3) the four-junction solar cell can obtain each junction sub-cell only through one-time epitaxial growth, the energy conversion efficiency of the four-junction solar cell is close to the theoretical limit, complex preparation processes such as secondary epitaxy or flip-chip contact in the prior art are not needed, and the four-junction solar cell is beneficial to realizing mass production.

Drawings

Fig. 1 is a schematic view of an overall structure of a four-junction solar cell according to an embodiment of the present disclosure.

Fig. 2 is a schematic structural diagram of a four-junction solar cell according to an embodiment of the present disclosure.

Fig. 3 is a flowchart illustrating a method for fabricating a four-junction solar cell according to an embodiment of the present disclosure.

[ notation ] to show

A 100-Ge sub-cell;

111: a p-Ge single crystal substrate and base region; 112: an n-Ge emission region;

113: an n-GaInP window layer;

11-a first lattice strained layer;

12-a first tunnel junction;

121：n++GaAs； 122：p++GaAs；

200-InGaAs sub-cells;

211: a p-InAlGaAs back electric field layer (InAlGaAs or AlGaInP back electric field layer);

212: a p-InGaAs base region;

213: an n-InGaAs emitter region; 214: an n-AlInP window layer;

22-a second tunnel junction;

221：n++InGaAs； 222：p++InGaAs；

300-InAlGaAs sub-cell;

311: p-InAlGaAs back electric field layer (Al)_0.7Ga_0.3As or AlGaInP back electric field layer);

312: a p-InAlGaAs base region;

313: an n-InGaP emitter region; 314: an n-AlInP window layer;

32-a third tunnel junction;

321：n++InAlGaAs； 322：p++InAlGaAs；

31-a second lattice strained layer;

400-InAlGaP subcells;

411: p-InAlGaP back electric field layer (Al)_0.7Ga_0.3As or AlGaInP back electric field layer);

412: a p-InAlGaP base region;

413: an n-InAlGaP emitter region; 414: an n-AlInP window layer;

500-ohmic contact layer.

Detailed Description

A multijunction solar cell comprises a stack of multijunction subcells, wherein each junction subcell comprises a stack of different semiconductor layers forming a PN junction. The PN junction of each subcell is formed such that each junction subcell has a different bandgap energy. Each junction subcell absorbs a reduced portion of the solar spectrum but has high efficiency.

The subcells are connected in series by tunnel diodes or tunnel junctions placed between two adjacent subcells. Since the subcells are connected in series, the subcell that absorbs the minimum energy of the incident spectrum and thus provides the minimum current limits the other cells to that current value. The maximum power provided by the integral multijunction solar cell is equal to the minimum of the currents delivered by the different subcells multiplied by the voltage at the terminals of the multijunction cell (equal to the sum of the voltages at the terminals of the subcells) and is not equal to the sum of the maximum power outputs provided by each subcell.

Compared with a three-junction battery, the four-junction battery can reduce heat loss, improve the utilization rate of the solar battery to solar spectrum, and simultaneously improve the open-circuit voltage and the filling factor to obtain higher conversion efficiency. However, in the structural design of the four-junction solar cell, from the standard AM0 spectrum angle, band gap matching of 0.7eV, 1.0eV, 1.4eV and 1.9eV can obtain the optimal conversion efficiency, but actually in the material growth process, the lattice matched material has difficulty in realizing the band gap, or other problems which cannot be overcome exist. For example, the material of 1.0eV also comprises InGaNAs, the lattice constant is basically matched with that of the Ge substrate, but the growth quality of the material has a bottleneck, and the internal quantum efficiency does not meet the practical requirement. The design of the band gap is realized by gradually adjusting the lattice constant through the lattice strain layer technology.

For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings. In the present disclosure, "a and/or B" means a, or B or both a and B. Throughout, the term "p-material" means "p-type material", "n-material" means "n-type material", "n + + material (e.g., GaAs)" means "n-type highly doped material", and "p + + material (e.g., GaAs)" means p-type highly doped material.

First embodiment

In a first exemplary embodiment of the present disclosure, a four junction solar cell is provided.

Fig. 1 is a schematic view of an overall structure of a four-junction solar cell according to an embodiment of the present disclosure. Fig. 2 is a schematic structural diagram of a four-junction solar cell according to an embodiment of the present disclosure.

Referring to fig. 1, the four-junction solar cell of the present disclosure includes junction sub-cells stacked in sequence, and each junction sub-cell includes, from bottom to top: a Ge sub-cell 100; an InGaAs subcell 200; an InAlGaAs sub-cell 300; and an InAlGaP subcell 400; the InAlGaP subcell 400 is the light incident side, and the Ge subcell 100 is the backlight side.

The details of the four-junction solar cell of the present embodiment are described below with reference to fig. 2.

In an embodiment of the present disclosure, the Ge sub-battery 110 sequentially includes, from bottom to top: a base region, an emitter region, and an aperture layer.

The InGaAs sub-battery 200 comprises, from bottom to top: a back electric field layer, a base region, an emitter region and a window layer.

The inalgas sub-battery 300 comprises from bottom to top: a back electric field layer, a base region, an emitter region and a window layer.

The InAlGaP sub-battery 400 comprises from bottom to top: a back electric field layer, a base region, an emitter region and a window layer.

In one embodiment, as shown in fig. 2, the Ge sub-cell 100 includes: a p-Ge single crystal substrate and base region 111, an n-Ge emitter region 112, and an n-GaInP window layer 113.

For example, in the Ge sub-cell 100, the thickness of the p-Ge single-crystal substrate/base region 111 is 110 μm to 140 μm, and the doping concentration is 0.5 × 10¹⁷～1×10¹⁷m^-3To (c) to (d); the n-Ge emitter region 112 has a thickness of 0.05-0.1 μm and a doping concentration of between0.5×10¹⁸～1×10¹⁸m^-3To (c) to (d);

in one embodiment, as shown in fig. 2, the InGaAs subcell 200 includes: InAlGaAs or AlGaInP back electric field layer 211, p-InGaAs base region 212, n-InGaAs emitter region 213 and n-AlInP window layer 214.

For example, in the InGaAs sub-cell 200, the p-InGaAs base region 212 has a thickness of 1 μm to 1.5 μm and a doping concentration of 0.5 × 10¹⁷～1×10¹⁷m^-33In the meantime.

In one embodiment, as shown in fig. 2, the inalgas subcell 300 includes: al (Al)_0.7Ga_0.3An As or AlGaInP back electric field layer 311, a p-InAlGaAs base region 312, an n-InGaP emitter region 313, and an n-AlInP window layer 314.

For example, in the InAlGaAs sub-cell 300, Al_0.7Ga_0.3The thickness of the As or AlGaInP back electric field layer 311 is 0.1-0.2 μm; the thickness of the p-InAlGaAs base region 312 is 0.08-0.15 μm, and the doping concentration is 0.5 multiplied by 10¹⁸～1×10¹⁸m^-3To (c) to (d); the thickness of the n-InGaP emitting region 313 is 1.0 μm-1.6 μm, and the doping concentration is between 1 × 10¹⁷～3×10¹⁷m^-3In the meantime.

In one embodiment, as shown in fig. 2, the InAlGaP subcell 400 includes: al (Al)_0.7Ga_0.3An As or AlGaInP back electric field layer 411, a p-InAlGaP base region 412, an n-InAlGaP emitter region 413, and an n-AlInP window layer 414.

For example, in the InAlGaP subcell 400, Al_0.7Ga_0.3The thickness of the As or AlGaInP back electric field layer 411 is 0.1-0.2 μm; the thickness of the p-InAlGaP base region 412 is 0.08-0.15 μm, and the doping concentration is between 0.5 x 10¹⁸～1×10¹⁸m^-3To (c) to (d); the thickness of the n-InAlGaP emitting region 413 is 1.0-1.6 μm, and the doping concentration is 1 × 10¹⁷～3×10¹⁷m^-3In the meantime.

In an embodiment of the present disclosure, a tunnel junction is disposed between every two adjacent sub-cells.

Referring to fig. 2, in the present embodiment, the tunnel junctions between the Ge sub-cell 100 and the InGaAs sub-cell 200, between the InGaAs sub-cell 200 and the inalgas sub-cell 300, and between the inalgas sub-cell 300 and the InAlGaP sub-cell 400 are the first tunnel junction 12, the second tunnel junction 22, and the third tunnel junction 32, respectively.

In one embodiment, the materials of the tunnel junctions (including the first tunnel junction 12, the second tunnel junction 22, and the third tunnel junction 32) include, but are not limited to, one or more of the following materials: GaAs, InGaP, Al_0.3Ga_0.7As; and/or the ion doping concentration in the tunnel junction reaches 1 x 10¹⁹cm^-3The above.

In one embodiment, the band gap width of the InGaAs subcell 200 is 1.0eV to 1.2 eV; the band gap width of the InAlGaAs sub-battery 300 is 1.3eV-1.5 eV; the band gap width of the InAlGaP subcell 400 is 1.8eV-2.2 eV.

Referring to fig. 2, in the present embodiment, a first lattice strain layer 11 is disposed between the Ge sub-cell 100 and the InGaAs sub-cell 200, and a second lattice strain layer 31 is disposed between the InAlGaAs sub-cell 300 and the InAlGaP sub-cell 400.

The lattice constant of the 1.0eV InGaAs sub-cell 200 is not matched with that of a Ge substrate, crystal growth cannot be directly realized on the Ge substrate, the common MOCVD growth requires that the lattice constant difference between two materials is within 1%, and if the lattice constant difference exceeds 1%, the defect density of the materials is sharply increased and even becomes polycrystal. The lattice strain layer has the function of gradually adjusting the lattice constant to a design value through layering, so that the epitaxial growth of two materials with large lattice constant difference is realized, and a larger design space is provided for adjusting the band gap of a device structure.

Referring to fig. 2, here the first lattice strained layer 11 is illustrated below the first tunnel junction 12 and the second lattice strained layer 31 is illustrated above the third tunnel junction 32. The structure of the four-junction solar cell of the present disclosure is not limited thereto, and the first lattice strain layer 11 and the first tunnel junction 12 can be exchanged in the up-down sequence; the second lattice strain layer 31 is interchangeable with the third tunnel junction 32 in the top-bottom order.

In an embodiment, the material of the first lattice strain layer 11 and the second lattice strain layer 31 is one or more of the following semiconductor materials: InGaAs, InAlGaAs, InAlGaP, or InGaP.

In this embodiment, as shown in fig. 2, an ohmic contact layer 500 is provided on the InAlGaP subcell 400.

In addition, the four-junction solar cell can also comprise necessary structures of cells such as upper and lower electrodes, an antireflection film and the like.

Second embodiment

In a second exemplary embodiment of the present disclosure, a method for fabricating a four-junction solar cell is provided for fabricating the four-junction solar cell shown in the first exemplary embodiment.

Fig. 3 is a flowchart illustrating a method for fabricating a four-junction solar cell according to an embodiment of the present disclosure.

The preparation method of the four-junction solar cell comprises the following steps: sequentially epitaxially growing a Ge sub-battery 100, an InGaAs sub-battery 200 and an InAlGaAs sub-battery 300; and an InAlGaP subcell 400; the InAlGaP subcell 400 is the light incident side, and the Ge subcell 100 is the backlight side.

Referring to fig. 3, in this embodiment, the method for manufacturing a four-junction solar cell includes:

step S201: epitaxially growing a Ge sub-cell 100;

in this embodiment, the step of epitaxially growing the Ge sub-cell 100 includes: metal-organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), or other epitaxial growth equipment is adopted, and a P-type Ge single crystal substrate 111 is selected as the substrate, and the substrate is also used as the base region, so that the name of the substrate is as follows: a p-Ge single crystal substrate and base region 111, and an n-Ge emitting region 112 and an n-type GaInP window layer 113 are formed by adopting a diffusion process;

wherein the thickness of the p-Ge single crystal substrate and base region 111 is 110 μm-140 μm, and the doping concentration is 0.5 × 10¹⁷～1×10¹⁷m^-3To (c) to (d); the n-Ge emitter region 112 has a thickness of 0.05-0.1 μm and a doping concentration of 0.5 × 10¹⁸～1×10¹⁸m^-3In the meantime.

Step S202: growing a first tunnel junction 12 and a first lattice strain layer 11 using a lattice grading technique;

in this embodiment, a lattice-graded technique is first used to grow a first lattice strain layer 11; then, growing a first tunnel junction 12 connecting the Ge subcell 100 and the InGaAs subcell 200, including growing two layers of the first tunnel junction with different doping types, for example, first growing n + + GaAs 121 and then growing p + + GaAs 122 in one example, to obtain a first tunnel junction 12;

the material of the first lattice strain layer 11 includes one or more of InGaAs, InAlGaAs, or InGaP, and in this embodiment, an As-containing compound is preferably used.

In other embodiments of the present disclosure, the first tunnel junction 12 may also be grown prior to growing the first lattice strained layer 11.

Step S203: epitaxially growing an InGaAs subcell 200;

in this embodiment, the step of growing the InGaAs subcell 200 includes: firstly growing p-InAlGaAs with high doping concentration as a back electric field layer, which is called as a p-InAlGaAs back electric field layer 211; growing p-InGaAs as base region, called p-InGaAs base region 212; then growing n-InGaAs as an emitter region, which is called as an n-InGaAs emitter region 213; finally, growing n-AlInP with high doping concentration as a window layer, which is called as an n-AlInP window layer 214; the p-InAlGaAs is made of InAlGaAs or A1GaInP and respectively corresponds to: an InAlGaAs or A1GaInP back electric field layer 211; the thickness of the p-InGaAs back electric field layer 211 is 1-1.5 μm, and the doping concentration is 0.5-1 × 10¹⁷m^-33；

Step S204: growing a second tunnel junction 22;

in this embodiment, the second tunnel junction 22 connecting the InGaAs sub-cell 200 and the InAlGaAs sub-cell 300 is grown, for example, n + + InGaAs 221 is grown first; and p + + InGaAs 222 is grown again.

Step S205: epitaxially growing an InAlGaAs sub-cell 300;

in this embodiment, the step of growing the inalgas subcell 300 includes: firstly growing p-InAlGaAs with high doping concentration as a back electric field layer, which is called as a p-InAlGaAs back electric field layer 311; regrowing p-InAlGaAs as base region, calledA p-InAlGaAs base region 312; then growing n-InGaP as an emitting region, which is called as an n-InGaP emitting region 313; then, growing n-AlInP with high doping concentration as a window layer, which is called as an n-AlInP window layer 314; the p-InAlGaAs material is Al_0.7Ga_0.3As or AlGaInP, respectively, corresponding to Al_0.7Ga_0.3An As or AlGaInP back electric field layer 311 with a thickness of 0.1-0.2 μm; the thickness of the p-InAlGaAs base region 312 is 0.08-0.15 μm, and the doping concentration is 0.5 multiplied by 10¹⁸～1×10¹⁸m^-3To (c) to (d); the thickness of the n-InGaP emitting region 313 is 1.0 μm-1.6 μm, and the doping concentration is between 1 × 10¹⁷～3×10¹⁷m^-3In the meantime.

Step S206: growing a third tunnel junction 32 and a second lattice strained layer 31 using a lattice grading technique;

in this embodiment, the third tunnel junction 32 connecting the InAlGaP sub-cell 300 and the inalgas sub-cell 400 is grown: firstly growing n + + InAlGaAs 321; growing p + + InAlGaAs 322;

after the third tunnel junction 32 has been grown, a lattice grading technique is also used to grow a second lattice-strained layer 31.

The material of the second lattice strain layer includes one or more of InAlGaP, inalgas, or InGaP, and a P-containing compound is preferably used in this embodiment.

In other embodiments of the present disclosure, the second lattice strain layer 32 may also be grown prior to growing the third tunnel junction 32.

Step S207: growing an InAlGaP subcell 400;

firstly, growing p-InAlGaP with high doping concentration as a back electric field layer, which is called as a p-InAlGaP back electric field layer 411; regrowing p-InAlGaP as a base region, which is called as a p-InAlGaP base region 412; then growing n-InAlGaP as an emitter region, which is called as an n-InAlGaP emitter region 413; finally, growing n-AlInP with high doping concentration as a window layer, which is called as an n-AlInP window layer 414; the material of the p-InAlGaP is Al_0.7Ga_0.3As or AlGaInP, corresponding to: al (Al)_0.7Ga_0.3An As or AlGaInP back electric field layer 411 with a thickness of 0.1-0.2 μm; the p-InAlGaP baseThe thickness of the region 412 is 0.08 μm-0.15 μm, and the doping concentration is 0.5 × 10¹⁸～1×10¹⁸m^-3To (c) to (d); the thickness of the n-InAlGaP emitting region 413 is 1.0-1.6 μm, and the doping concentration is 1 × 10¹⁷～3×10¹⁷m^-3In the meantime.

Step S208: growing an ohmic contact layer 500;

a high doping concentration N-type GaAs cap layer is grown over InAlGaP subcell 400 as ohmic contact layer 500.

Of course, in this embodiment, other steps of preparing the battery are also included:

step S209: manufacturing an upper electrode;

manufacturing a patterned upper electrode above the ohmic contact layer 500, which substantially comprises the steps of designing and manufacturing a photoetching layout, gluing and developing, upper electrode metal deposition, developing and exposing, removing glue, annealing and the like;

step S210: manufacturing a lower electrode;

and depositing and annealing the lower electrode metal.

Step S211: manufacturing an anti-reflection film;

entering an evaporation machine to deposit an optical antireflection film on the surface of the electrode on the chip;

step S212: and (6) scribing and testing.

The four-junction solar cell of the embodiment can obtain each junction sub-cell only by one-time epitaxial growth, the energy conversion efficiency of the four-junction solar cell is close to the theoretical limit, complex preparation processes such as secondary epitaxy or flip-chip contact in the prior art are not needed, and the four-junction solar cell is beneficial to realizing mass production.

In summary, the present disclosure provides a four-junction solar cell and a method for manufacturing the same, which implement an ideal four-junction band gap by using a secondary lattice buffer layer technology, and the four-junction solar cell can obtain each junction sub-cell only by one epitaxial growth, and has an energy conversion efficiency close to a theoretical limit, and does not require complex manufacturing processes such as secondary epitaxy or flip-chip contact in the prior art, thereby facilitating mass production and providing a direction and a basis for developing a higher conversion efficiency cell.

In the drawings used to describe embodiments of the present disclosure, the thickness of a layer or region is exaggerated for clarity; also, in the drawings of some embodiments of the present disclosure, only the structures related to the concept of the present disclosure are shown, and other structures may refer to general designs. In addition, some drawings only illustrate the basic structure of the embodiments of the present disclosure, and the detailed parts are omitted.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, is intended in an open-ended sense, and does not exclude the presence of other elements, components, portions or items than those listed. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

The above-mentioned embodiments are intended to illustrate the objects, aspects and advantages of the present disclosure in further detail, and it should be understood that the above-mentioned embodiments are only illustrative of the present disclosure and are not intended to limit the present disclosure, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.