阅读说明：本技术 Tcp数据的传输方法、装置、计算机设备及存储介质 (Transmission method and device of TCP data, computer equipment and storage medium ) 是由 袁靖茹 于 2020-11-27 设计创作，主要内容包括：本申请适用于数据处理技术领域,提供了TCP数据的传输方法、装置、计算机设备及存储介质,基于FPGA,方法包括：将接收到的传输控制协议TCP数据包的序列号,与应接收数据包的目标序列号进行对比；若TCP数据包的序列号大于目标序列号,则将TCP数据包存储至预设的FPGA缓存空间,并确定当前是否接收到新的TCP数据包；若当前未接收到新的TCP数据包,则将FPGA缓存空间中序列号等于目标序列号的TCP数据包传递至下一节点。本方法能够同时进行数据包的接收和对乱序数据包的重组,使得数据包的接收、解析和重组过程并行执行,进一步提高数据传输过程中数据处理的效率。(The application is applicable to the technical field of data processing, and provides a transmission method and a device of TCP data, computer equipment and a storage medium, wherein based on an FPGA, the method comprises the following steps: comparing the sequence number of the received transmission control protocol TCP data packet with the target sequence number of the data packet to be received; if the serial number of the TCP data packet is larger than the target serial number, storing the TCP data packet to a preset FPGA cache space, and determining whether a new TCP data packet is received currently; and if a new TCP data packet is not received currently, transmitting the TCP data packet with the sequence number equal to the target sequence number in the FPGA cache space to the next node. The method can simultaneously receive the data packet and recombine the disordered data packet, so that the receiving, analyzing and recombining processes of the data packet are executed in parallel, and the data processing efficiency in the data transmission process is further improved.)

1. A transmission method of TCP data is characterized in that based on a field programmable gate array FPGA, the transmission method comprises the following steps:

comparing the sequence number of the received transmission control protocol TCP data packet with the target sequence number of the data packet to be received;

if the serial number of the TCP data packet is larger than the target serial number, storing the TCP data packet to a preset FPGA cache space, and determining whether a new TCP data packet is received currently;

and if a new TCP data packet is not received currently, transmitting the TCP data packet with the sequence number equal to the target sequence number in the FPGA cache space to the next node.

2. The TCP data transmission method according to claim 1, wherein after comparing the sequence number of the received TCP packet with the target sequence number of the data packet to be received, the method further comprises:

and if the sequence number of the TCP data packet is equal to the target sequence number, transmitting the TCP data packet to a next node.

3. The TCP data transmission method according to claim 1, wherein after comparing the sequence number of the received TCP packet with the target sequence number of the data packet to be received, the method further comprises:

and if the sequence number of the TCP data is smaller than the target sequence number, discarding the TCP data packet.

4. The TCP data transmission method according to claim 1, wherein if a new TCP data packet is not currently received, transmitting the TCP data packet with the sequence number equal to the target sequence number in the FPGA cache space to a next node, comprises:

if a new TCP data packet is not received currently, detecting the TCP data packet in a non-empty cache space in the FPGA cache space;

and if the sequence number of the TCP data packet in the non-empty cache space is equal to the target sequence number, transmitting the TCP data packet in the non-empty cache space to a next node.

5. The TCP data transmission method according to claim 4, wherein after detecting a TCP data packet in a non-empty buffer space in the FPGA buffer space if a new TCP data packet is not currently received, the method further comprises:

and if the sequence number of the TCP data packet in the non-empty cache space is greater than the target sequence number, returning to the step of determining whether a new TCP data packet is currently received.

6. The TCP data transmission method according to claim 4, wherein after detecting a TCP data packet in a non-empty buffer space in the FPGA buffer space if a new TCP data packet is not currently received, the method further comprises:

if the sequence number of the TCP data packet in the non-empty cache space is smaller than the target sequence number, the TCP data packet in the non-empty cache space is discarded.

7. The method according to any one of claims 1 to 6, wherein if a new TCP packet is not currently received, after the TCP packet with the sequence number equal to the target sequence number in the FPGA cache space is transferred to a next node, the method further comprises:

reading the TCP data packet to obtain the data length of the TCP data packet;

and summing the data length and the target sequence number to obtain the latest target sequence number.

8. A data transmission device, based on an FPGA, the device comprising:

the comparison module is used for comparing the sequence number of the received transmission control protocol TCP data packet with the target sequence number of the data packet to be received;

the buffer module is used for storing the TCP data packet to a preset FPGA buffer space and determining whether a new TCP data packet is received currently if the serial number of the TCP data packet is greater than the target serial number;

and the transmission module is used for transmitting the TCP data packet with the sequence number equal to the target sequence number in the FPGA cache space to the next node if a new TCP data packet is not received currently.

9. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the method according to any of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1 to 7.

Technical Field

The present application belongs to the technical field of data processing, and in particular, to a method and an apparatus for transmitting TCP data, a computer device, and a storage medium.

Background

The Transmission Control Protocol (TCP) is a connection-oriented, reliable transport layer communication Protocol based on a byte stream. In the transmission process of TCP data, the data packet sequence is out of order due to the non-fixed property of the data exchange path and the routing path, and the TCP protocol can recombine the data packets by utilizing the reliability characteristics of the TCP protocol so as to ensure that the data packet sequence received by a receiving end is correct. Therefore, the TCP protocol is widely applied to trading scenarios with high requirements on data transmission security, such as securities trading, futures trading, gold trading, and the like.

In the related art, the TCP protocol is implemented based on the conventional CPU architecture, and consumes CPU resources. With the development of big data, the data volume of a transaction scene is larger and larger, so that the data transmission requirement of mass financial transactions is difficult to meet by a TCP data recombination mode realized based on a CPU architecture. It can be seen that the current data transmission process based on the TCP protocol has a problem of small application range.

Disclosure of Invention

The embodiment of the application provides a transmission method and device of TCP data, computer equipment and a storage medium, and can solve the problem that the application range is small in the current data transmission process based on a TCP protocol.

In a first aspect, an embodiment of the present application provides a transmission method of TCP data, which is based on a field programmable gate array FPGA, and the transmission method includes:

comparing the sequence number of the received transmission control protocol TCP data packet with the target sequence number of the data packet to be received;

if the serial number of the TCP data packet is larger than the target serial number, storing the TCP data packet to a preset FPGA cache space, and determining whether a new TCP data packet is received currently;

and if a new TCP data packet is not received currently, transmitting the TCP data packet with the sequence number equal to the target sequence number in the FPGA cache space to the next node.

According to the transmission method of the TCP data, because a plurality of instruction cycles need to be consumed in the identification process of the serial number based on the CPU architecture, and each instruction cycle needs to consume a plurality of clock cycles, the CPU is difficult to deal with the complex out-of-order recombination process, and the requirement of low delay cannot be met. In the embodiment, out-of-order recombination in the data transmission process is realized based on a Field Programmable Gate Array (FPGA), and the FPGA can complete identification of a serial number in one clock cycle, so that the data analysis and data recombination efficiency is improved, and thus the TCP data transmission method can be applied to more data transmission scenes. Specifically, the TCP data packet is received based on the FPGA, when the serial number of the data packet is greater than the target serial number corresponding to the data packet to be received, the TCP data packet is stored in a preset FPGA cache space so as to achieve the purpose of analyzing the TCP data packet, whether a new TCP data packet is received currently or not is determined, and if the new TCP data packet is not received currently, the TCP data packet with the serial number equal to the target serial number in the FPGA cache space is transmitted to the next node so as to achieve the purpose of recombining the out-of-order data packet. The method can simultaneously receive the data packet and recombine the disordered data packet, so that the receiving, analyzing and recombining processes of the data packet are executed in parallel, and the data processing efficiency in the data transmission process is further improved.

In a second aspect, an embodiment of the present application provides a TCP data transmission apparatus, where based on an FPGA, the apparatus includes:

the comparison module is used for comparing the sequence number of the received transmission control protocol TCP data packet with the target sequence number of the data packet to be received;

the buffer module is used for storing the TCP data packet to a preset FPGA buffer space and determining whether a new TCP data packet is received currently if the serial number of the TCP data packet is greater than the target serial number;

and the transmission module is used for transmitting the TCP data packet with the sequence number equal to the target sequence number in the FPGA cache space to the next node if a new TCP data packet is not received currently.

In a third aspect, an embodiment of the present application provides a computer device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor, when executing the computer program, implements the transmission method of TCP data according to any one of the above first aspects.

In a fourth aspect, the present application provides a computer-readable storage medium, where a computer program is stored, and when executed by a processor, the computer program implements the TCP data transmission method according to any one of the first aspect.

In a fifth aspect, an embodiment of the present application provides a computer program product, which, when running on a terminal device, causes the terminal device to execute the TCP data transmission method according to any one of the above first aspects.

It is understood that the beneficial effects of the second aspect to the fifth aspect can be referred to the related description of the first aspect, and are not described herein again.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

Fig. 1 is a schematic flowchart of a TCP data transmission method according to an embodiment of the present application;

fig. 2 is a schematic flow chart of a TCP data transmission method according to another embodiment of the present application;

fig. 3 is a schematic structural diagram of a TCP data transmission apparatus according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a computer device provided in an embodiment of the present application.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to" determining "or" in response to detecting ". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".

Furthermore, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between descriptions and not necessarily for describing or implying relative importance.

Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise.

As described in the related art, the TCP protocol is implemented based on the conventional CPU architecture, and consumes much CPU resources. With the development of big data, the data volume of a transaction scene is larger and larger, so that the data transmission requirement of mass financial transactions is difficult to meet by a TCP data recombination mode realized based on a CPU architecture. It can be seen that the data transmission process based on the TCP protocol at present has a problem of low data reassembly efficiency.

In view of this, embodiments of the present application provide a method for transmitting TCP data, which solves the problem that a CPU is difficult to handle a complex out-of-order reassembly process and cannot meet a low latency requirement because a CPU architecture needs to consume multiple instruction cycles and each instruction cycle needs to consume multiple clock cycles in a serial number identification process. According to the method, the disorder recombination of the data transmission process is realized based on the FPGA, the FPGA can finish the identification of the serial number in one clock period, and the data analysis and data recombination efficiency is improved, so that the TCP data transmission method can be suitable for more data transmission scenes. Specifically, the TCP data packet is received based on the FPGA, when the serial number of the data packet is greater than the target serial number corresponding to the data packet to be received, the TCP data packet is stored in a preset FPGA cache space so as to achieve the purpose of analyzing the TCP data packet, whether a new TCP data packet is received currently or not is determined, and if the new TCP data packet is not received currently, the TCP data packet with the serial number equal to the target serial number in the FPGA cache space is transmitted to the next node so as to achieve the purpose of recombining the out-of-order data packet. The method can simultaneously receive the data packet and recombine the disordered data packet, so that the receiving, analyzing and recombining processes of the data packet are executed in parallel, and the data processing efficiency in the data transmission process is further improved.

Fig. 1 shows a schematic flow chart of a transmission method of TCP data provided in the present application. The execution main body of the transmission method of the TCP data provided by the embodiment of the application is computer equipment, and the computer equipment comprises but is not limited to computing equipment such as a smart phone, a tablet computer, a desktop computer, a supercomputer, a personal digital assistant and a server which are provided with an FPGA chip. The FPGA is a programmable chip, FPGA development engineers can describe a circuit structure by adopting a hardware description language, and then a software tool maps the functions of the circuit structure onto the FPGA chip after a series of fixed software processes (synthesis, layout and wiring), so that the circuits on the FPGA chip are consistent with the circuits described by the FPGA development engineers, and the circuit functions expected by the development engineers are realized. The transmission method of TCP data shown in fig. 1 includes steps S101 to S103, which are described in detail as follows.

S101, comparing the sequence number of the received transmission control protocol TCP data packet with the target sequence number of the data packet to be received.

In the present embodiment, data is transmitted based on the TCP protocol, and a plurality of consecutive TCP data are packetized into TCP packets and transmitted in the form of TCP packets. A TCP packet (also referred to as a packet for short in this embodiment) is a packet transmitted based on a TCP protocol, and the packet includes a plurality of bytes of data, and a TCP protocol header field of each TCP packet has a sequence number, which indicates a number of a starting byte of data in a current packet in the whole transmission data and also indicates a number of the whole packet in the whole transmission data. The target sequence number is the sequence number of the TCP data packet which should be received by the computer equipment, and the data packet which should be received is the target data packet of which the target sequence number carries the sequence number of the latest data packet received by the computer equipment. Alternatively, since the target serial number is updated in real time, a register for recording the latest target serial number may be set in advance.

Illustratively, the protocol header of a TCP packet has a sequence number seq _ num and pkg _ len indicating the number of bytes of data in the packet. Assuming that the seq _ num of the first packet is 1 and pkg _ len is 10, the seq _ num of the second packet is 11 and pkg _ len is 200, the seq _ num of the third packet is 211. Under normal conditions, the computer device should receive the packet with seq _ num equal to 1, the packet with seq _ num equal to 11, and the packet with seq _ num equal to 211 in sequence, but due to the non-fixed nature of the data exchange path and the routing path, multiple data transmission channels occur so that the sequence of the packets received by the computer is wrong, that is, the computer device may receive the packet with seq _ num equal to 1, the packet with seq _ num equal to 211, and the packet with seq _ num equal to 11 in sequence, and may also receive the packet with seq _ num equal to 211, the packet with seq _ num equal to 1, and the packet with seq _ num equal to 11 in sequence, and may also be in other sequences, and the sequence is not exhaustive. Therefore, in order to ensure that the sequence of the data packet transmitted to the next node by the computer device is correct, the sequence number of the TCP data packet is compared with the target sequence number corresponding to the data packet that should be received. That is, if the first packet received by the computer device is seq _ num equal to 1, the second packet to be received is seq _ num equal to 11, that is, seq _ num equal to 11 is the current target sequence number, so the sequence number of the second packet actually received by the computer device is compared with the target sequence number to determine whether the two are equal, and if the two are equal, the packet sequence is correct, otherwise, the packet sequence is out of order.

And S102, if the serial number of the TCP data packet is larger than the target serial number, storing the TCP data packet to a preset FPGA cache space, and determining whether a new TCP data packet is received currently.

In this embodiment, the computer device is preset with a plurality of FPGA cache spaces. The FPGA buffer space is a buffer unit on the FPGA chip and used for buffering out-of-order TCP packets, and the buffer space may be set based on a FIFO or a RAM, and the specific type of the buffer space is not limited in this embodiment. Optionally, N buffer spaces are opened based on an FPGA software tool, and each buffer space is marked with a serial number, so as to record TCP data packets stored in the buffer space, where a value of N may be set according to an actual requirement, for example, N is 32, 32 buffers may finish parsing data packets in one clock cycle at the fastest speed, and one clock cycle is the smallest operation time unit of the FPGA.

In one case, when the TCP data packet is greater than the total number N of the FPGA buffer space, the TCP data packet with the sequence number smaller than the latest target sequence number in the buffer space may be removed, and the TCP data packet with the sequence number equal to the latest target sequence number may be transmitted to the next node, thereby achieving the purpose of releasing the buffer space. Further, if the buffer space does not have a TCP packet that needs to be cleared and a TCP packet that is passed to the next node, the TCP packet in buffer space number 0 may be discarded. Since the TCP protocol has a retransmission mechanism, i.e. when a data packet is lost, the data source retransmits the data packet, the TCP data packet dropped in the buffer space No. 0 is subsequently re-received by the computer device.

It should be noted that, because the retransmission mechanism of the TCP protocol has timing determination, the value of N, for example, N is T/T, can be calculated according to the time T and retransmission timing T of processing one TCP data packet by the FPGA, so as to ensure that the buffer space is sufficient for storing out-of-order TCP data packets.

And when the computer equipment judges that the sequence number of the TCP data packet is greater than the target sequence number, the TCP data packet is stored in a preset FPGA cache space. If the sequence number of the TCP data packet is greater than the target sequence number, the TCP data is out of order, so that the TCP data is cached until the latest target sequence number is equal to the sequence number of the TCP data, and the latest target sequence number is transmitted to the next node. It can be understood that, generally, the data packet with the front sequence number is received first, so that the TCP data packets can be buffered in sequence according to the number of the buffer space of the FPGA, so that when the buffer space is checked subsequently, the TCP data packets can also be checked in sequence, so as to check the TCP data packet buffered first preferentially and avoid the condition of missing check.

In order to ensure that the packet input end of the computer device is not blocked, it is determined whether a new TCP packet is received each time one buffer space is cleared, and if not, the process proceeds to step S103.

S103, if a new TCP data packet is not received at present, the TCP data packet with the sequence number equal to the target sequence number in the FPGA cache space is transmitted to the next node.

In this embodiment, if a new TCP packet is not currently received, it indicates that there is no new TCP packet at the packet input end of the computer device to be processed, so the TCP packet in the FPGA cache space is checked to transmit the TCP packet with the sequence number equal to the target sequence number to the next node, thereby achieving the purpose of reassembling the out-of-order packet. It will be appreciated that the next node may be any unit or module on the computer device, for example, a statistical module for performing data statistics on the transaction data, and then the received data packets of the transaction data may be passed to the statistical module for performing data statistics.

In an embodiment, if a new TCP packet is not currently received, the step of transferring the TCP packet with the sequence number equal to the target sequence number in the FPGA cache space to the next node includes: if a new TCP data packet is not received currently, detecting the TCP data packet in a non-empty cache space in the FPGA cache space; and if the sequence number of the TCP data packet in the non-empty cache space is equal to the target sequence number, transmitting the TCP data packet in the non-empty cache space to the next node.

In this embodiment, the non-empty buffer space is a buffer space in which the TCP data packet is buffered. The computer equipment checks whether a new data packet is received, if not, the computer equipment starts checking from the No. 0 cache space, determines whether the sequence number of the data packet in the non-empty cache space is equal to the latest target sequence number, if so, the data packet in the non-empty cache space is transmitted to the next node, and if not, the computer equipment checks the next data packet. Optionally, after checking one non-empty buffer space, checking whether a new data packet is received, if so, checking whether the sequence number of the new data packet is equal to the latest target sequence number, so as to avoid the condition that the input end of the data packet is jammed. Specifically, a logic judgment condition is added in the FPGA, and the priority for checking whether the sequence number of the new data packet is equal to the latest target sequence number is set to be higher than the sequence number of the data packet in the checking cache space.

In an embodiment, if a new TCP packet is not currently received, after the TCP packet with a sequence number equal to the target sequence number in the FPGA cache space is transferred to the next node, the method further includes: reading the TCP data packet to obtain the data length of the TCP data packet; and summing the data length and the target sequence number to obtain the latest target sequence number.

In this embodiment, the data length is the number of bytes of TCP data in the data packet. Recording a target sequence number next _ seq of a data packet to be received currently through a preset register, reading a sequence number cur _ seq and a data length pkg _ len of the data packet when a new data packet is received, transmitting the data packet to a next node when cur _ seq is equal to next _ seq, obtaining a new next _ seq according to cur _ seq + pkg _ len, and writing the value into the new next _ seq.

Referring to fig. 2, fig. 2 is a flowchart illustrating an implementation of a TCP data transmission method according to another embodiment of the present application. With respect to the embodiment shown in fig. 1, the transmission method of TCP data provided in the embodiment shown in fig. 2 further includes steps S201 and S202 after step S101. The details are as follows:

s201, if the sequence number of the TCP data packet is equal to the target sequence number, transmitting the TCP data packet to a next node.

In this embodiment, after receiving a TCP data packet, the sequence number of the received TCP data packet is compared with a target sequence number of a data packet to be received, and if the sequence number of the TCP data packet is equal to the target sequence number, it indicates that the TCP data packet is a data packet to be received, and the TCP data packet is transmitted to a next node.

S202, if the sequence number of the TCP data is smaller than the target sequence number, the TCP data packet is discarded.

In this embodiment, since the TCP protocol has a retransmission mechanism, there is a case where the same data packet is repeatedly transmitted, and in order to ensure that the transmission sequence of the data packet is accurate, after receiving the TCP data packet, this embodiment compares the sequence number of the received TCP data packet of the transmission control protocol with the target sequence number of the data packet to be received, and if the sequence number of the TCP data is smaller than the target sequence number, it indicates that the computer device has transmitted the TCP data packet to the next node, that is, the data packet is history data, so that the received data packet is useless at this time, and the TCP data packet is discarded. It is understood that discarding means that the FPGA judges that the data packet needs not to be processed through some specific logic control (e.g. processing an active high level bit of the data packet), and if the sequence number of the TCP data is detected to be less than the target sequence number, the flag bit of processing is pulled low, that is, the data packet is not processed until the next packet arrives to make a judgment.

With respect to the embodiment shown in fig. 1, the transmission method of TCP data provided in the embodiment shown in fig. 2 further includes steps S203 and S204 after step S103. The details are as follows:

s203, if the sequence number of the TCP data packet in the non-empty cache space is larger than the target sequence number, returning to the step of determining whether a new TCP data packet is received currently.

In this embodiment, if the sequence number of the TCP data packet in the non-empty cache space is greater than the target sequence number, it indicates that the TCP data packet is not a data packet to be received, and therefore, the step of determining whether a new TCP data packet is currently received is returned.

S204, if the sequence number of the TCP data packet in the non-empty cache space is smaller than the target sequence number, discarding the TCP data packet in the non-empty cache space.

In this embodiment, because the FPGA receives a new packet during the process of checking the buffer space, according to the foregoing logic control, the FPGA may first check the sequence number a1 of the new packet, and then update the target sequence number B1, if the sequence number a1 of the new packet is equal to the target sequence number B1 before updating, the target sequence number B1 is updated to obtain a new target sequence number B2, at this time, the value of the target sequence number B2 is larger than that of the previous B1, and when checking the non-empty buffer space again, the sequence number a2 of the packet in the buffer space is also equal to the previous target sequence number B1, but since the check is not made, the sequence number a2 of the packet in the buffer space is smaller than B2 at this time, and the packet in the buffer space is discarded. Thereby enabling the buffer space to be released in the event that the computer device receives a data packet equal to the latest target sequence number.

It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

Fig. 3 shows a block diagram of a TCP data transmission apparatus provided in the embodiment of the present application, and for convenience of description, only the relevant parts of the embodiment of the present application are shown.

Referring to fig. 3, the apparatus includes:

a comparing module 301, configured to compare a sequence number of a received TCP packet with a target sequence number of a packet to be received;

the cache module 302 is configured to store the TCP data packet in a preset FPGA cache space and determine whether a new TCP data packet is currently received if the sequence number of the TCP data packet is greater than the target sequence number;

a transferring module 303, configured to transfer, if a new TCP packet is not currently received, the TCP packet with the sequence number equal to the target sequence number in the FPGA cache space to a next node.

The embodiment of the application provides a transmission device of TCP data, and aims to solve the problems that a plurality of instruction cycles need to be consumed in the identification process of a serial number based on a CPU framework, and each instruction cycle needs to consume a plurality of clock cycles, so that a CPU is difficult to deal with a complex out-of-order recombination process, and the low-delay requirement cannot be met. The device of the embodiment realizes out-of-order recombination of the data transmission process based on the FPGA, the FPGA can complete the identification of the serial number in one clock cycle, and the efficiency of data analysis and data recombination is improved, so that the TCP data transmission method can be suitable for more data transmission scenes. Specifically, the receiving module 301 based on the FPGA receives the TCP data packet, and when the sequence number of the data packet is greater than the target sequence number corresponding to the data packet to be received, the buffer module 302 stores the TCP data packet in a preset FPGA buffer space to achieve the purpose of analyzing the TCP data packet, and determines whether a new TCP data packet is currently received, and if a new TCP data packet is not currently received, the transmitting module 303 transmits the TCP data packet whose sequence number is equal to the target sequence number in the FPGA buffer space to the next node to achieve the purpose of reassembling the out-of-order data packet. The device can simultaneously receive the data packets and recombine the out-of-order data packets, so that the receiving, analyzing and recombining processes of the data packets are executed in parallel, and the efficiency of data recombination in the data transmission process is further improved.

In an embodiment, the apparatus further includes:

and the second transmission module is used for transmitting the TCP data packet to the next node if the sequence number of the TCP data packet is equal to the target sequence number.

In an embodiment, the apparatus further includes:

a first discarding module, configured to discard the TCP packet if the sequence number of the TCP data is less than the target sequence number.

In an embodiment, the transmission module 303 is specifically configured to:

if a new TCP data packet is not received currently, detecting the TCP data packet in a non-empty cache space in the FPGA cache space;

and if the sequence number of the TCP data packet in the non-empty cache space is equal to the target sequence number, transmitting the TCP data packet in the non-empty cache space to a next node.

In an embodiment, the transmission module 303 is further specifically configured to:

and if the sequence number of the TCP data packet in the non-empty cache space is greater than the target sequence number, returning to the step of determining whether a new TCP data packet is currently received.

In an embodiment, the transmission module 303 is further specifically configured to:

if the sequence number of the TCP data packet in the non-empty cache space is smaller than the target sequence number, the TCP data packet in the non-empty cache space is discarded.

In an embodiment, the apparatus further includes:

the reading module is used for reading the TCP data packet to obtain the data length of the TCP data packet;

and the summing module is used for summing the data length and the target sequence number to obtain the latest target sequence number.

It should be noted that, for the information interaction, execution process, and other contents between the above-mentioned devices/units, the specific functions and technical effects thereof are based on the same concept as those of the embodiment of the method of the present application, and specific reference may be made to the part of the embodiment of the method, which is not described herein again.

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

Fig. 4 is a schematic structural diagram of a computer device according to an embodiment of the present application. As shown in fig. 4, the computer device 4 of this embodiment includes: at least one processor 40 (only one shown in fig. 4), a memory 41, and a computer program 42 stored in the memory 41 and executable on the at least one processor 40, the processor 40 implementing the steps of any of the method embodiments described above when executing the computer program 42.

The computer device 4 may be a mobile phone, a desktop computer, a notebook, a palm computer, a cloud server, or other computing devices. The computer device may include, but is not limited to, a processor 40, a memory 41. Those skilled in the art will appreciate that fig. 4 is merely an example of the computer device 4 and does not constitute a limitation of the computer device 4, and may include more or less components than those shown, or combine certain components, or different components, such as input output devices, network access devices, etc.

The Processor 40 may be a Central Processing Unit (CPU), and the Processor 40 may be other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The memory 41 may in some embodiments be an internal storage unit of the computer device 4, such as a hard disk or a memory of the computer device 4. The memory 41 may also be an external storage device of the computer device 4 in other embodiments, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like, which are provided on the computer device 4. Further, the memory 41 may also include both an internal storage unit and an external storage device of the computer device 4. The memory 41 is used for storing an operating system, an application program, a BootLoader (BootLoader), data, and other programs, such as program codes of the computer program. The memory 41 may also be used to temporarily store data that has been output or is to be output.

The embodiments of the present application further provide a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the computer program implements the steps in the above-mentioned method embodiments.

The embodiments of the present application provide a computer program product, which when running on a mobile computer, enables the mobile computer to implement the steps in the above method embodiments when executed.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, all or part of the processes in the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium and can implement the steps of the embodiments of the methods described above when the computer program is executed by a processor. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer readable medium may include at least: any entity or device capable of carrying computer program code to a photographing apparatus/computer device, a recording medium, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), an electrical carrier signal, a telecommunications signal, and a software distribution medium. Such as a usb-disk, a removable hard disk, a magnetic or optical disk, etc. In certain jurisdictions, computer-readable media may not be an electrical carrier signal or a telecommunications signal in accordance with legislative and patent practice.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus/network device and method may be implemented in other ways. For example, the above-described apparatus/network device embodiments are merely illustrative, and for example, the division of the modules or units is only one logical division, and there may be other divisions when actually implementing, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.