阅读说明：本技术 用于低功率的相关双采样放大器 (Correlated double sampling amplifier for low power ) 是由 M·C·W·科林 M·米克 于 2019-08-02 设计创作，主要内容包括：信号采集或调节放大器可以配置和控制为使用差分输入信号的相关双倍采样(CDS)和电容性或其他反馈网络中的存储电容器,低功率运算跨导放大器(OTA)能够在CDS采样之间断电,并且可以以提供良好性能特征的方式运行,同时仍提供低功率或高效功率。放大器和其他信号处理电路可以在需要较少信号测量吞吐量的情况下按比例缩小功率,在需要更多信号测量吞吐量的情况下按比例放大功率。这种灵活性可以帮助使本方法对于广泛的信号采集和测量应用有用。通过缓冲放大器进行预充电可以提供改进的信号采集电路有效输入阻抗。(The signal acquisition or conditioning amplifier may be configured and controlled to use Correlated Double Sampling (CDS) of the differential input signal and a storage capacitor in a capacitive or other feedback network, and the low power Operational Transconductance Amplifier (OTA) can be powered down between CDS samples and can operate in a manner that provides good performance characteristics while still providing low or high efficiency power. Amplifiers and other signal processing circuitry may scale power down where less signal measurement throughput is needed and scale power up where more signal measurement throughput is needed. This flexibility may help make the present method useful for a wide range of signal acquisition and measurement applications. Precharging through the buffer amplifier may provide improved effective input impedance of the signal acquisition circuit.)

1. A signal acquisition circuit for performing Correlated Double Sampling (CDS) on a differential input signal having components Vx and Vy for low power signal processing, the circuit comprising:

an amplifier comprising or coupled to a feedback network comprising or coupled to a storage capacitor, the amplifier configured to provide gain between first and second amplifier inputs and an amplifier output;

an initialization switch arranged to initialize the storage capacitor prior to CDS of the input signal; and

a control circuit configured to control operation of the multiplexer to sequentially couple Vx and Vy to the first amplifier input for each of the first and second samples of CDS before reinitializing the storage capacitor or before reinitializing the storage capacitor.

2. The circuit of claim 1, comprising:

a first precharge switch configured to be controlled by the control circuit to couple Vx through a first buffer amplifier to the first amplifier input to precharge the first amplifier input;

a first set-up switch controlled by said control circuit to subsequently couple Vx to said first amplifier input without said first buffer amplifier to further set up said first amplifier input after precharging;

a second precharge switch configured to be controlled by the control circuit to couple Vy to the first amplifier input through a second buffer amplifier to precharge the first amplifier input; and

a second set-up switch configured to be controlled by the control circuit to subsequently couple Vy to the first amplifier input without a second buffer amplifier to further set up the first amplifier input after precharging.

3. The circuit of claim 1 or 2, wherein the initialization switch is arranged to initialize the storage capacitor prior to CDS, including precharging, establishing and sampling each of Vx and Vy prior to reinitializing the storage capacitor.

4. The circuit of any of claims 1-3, wherein the initialization switch is located between the amplifier output and the second amplifier input.

5. The circuit of any of claims 1 to 4, wherein the amplifier comprises an Operational Transconductance Amplifier (OTA).

6. The circuit of any of claims 1-5, further comprising an analog-to-digital converter (ADC) coupled to the amplifier output, and wherein the control circuit is configured to control the ADC to perform analog-to-digital conversion of amplifier output samples of Vx and Vy.

7. The circuit of claim 6, wherein the ADC comprises a Successive Approximation Routine (SAR) ADC, and wherein the control circuit is configured to allow the ADC to be powered down between intermittent CDS analog-to-digital conversions.

8. The circuit of claim 5 wherein the OTA is configured to power down between intermittent CDS samples.

9. The circuit of any of claims 1 to 8, wherein the amplifier comprises an Operational Transconductance Amplifier (OTA), and wherein the feedback network comprises:

a feedback capacitor between the amplifier output and the second amplifier input; and

a storage capacitor between the second amplifier input and ground or other reference node.

10. The circuit of claim 2, wherein the first and second buffer amplifiers are configured to be powered down by the control circuit between intermittent CDS sampling.

11. The circuit of any of claims 1-10, wherein the control circuit is configured to alternate a time series of multiplexes Vx and Vy to the first input amplifier input between successive CDS samples.

12. A method of acquisition of an input signal of Correlated Double Sampling (CDS) of a differential input signal having components Vx and Vy for low power signal processing, the method comprising:

initializing a storage capacitor included in or coupled to a feedback network around an amplifier prior to CDS sampling of an input signal;

coupling Vx to a first amplifier input of the amplifier for first sampling of CDS;

coupling Vy to a first amplifier input of the amplifier for a second sampling of CDS before or without re-initializing the storage capacitor; and

sampling a difference in amplifier output signals of the amplifier in response to each of Vx and Vy to provide CDS sampling of a differential input signal without or prior to reinitializing the storage capacitor.

13. The method of claim 12, comprising:

precharging the first amplifier input through a Vx-applying buffer amplifier;

establishing said first amplifier input further without said buffer amplifier by applying Vx to said first amplifier input prior to sampling Vx via an output signal of said amplifier;

precharging the first amplifier input through a buffer amplifier to which Vy is applied; and

the first amplifier input is further established without the buffer amplifier by applying Vy to the first amplifier input prior to sampling Vy via the output signal of the amplifier.

14. The method of claim 12 or 13, comprising:

sampling an output signal of the amplifier in response to applied Vx after further setup to provide a first output sample of CDS;

sampling an output signal of the amplifier in response to an applied Vy after further setup to provide a second output sample of CDS; and

CDS samples are provided based on a difference between a first output sample and a second output sample before reinitializing a storage capacitor between the first output sample and the second output sample or without reinitializing.

15. The method of claim 14, comprising reinitializing the storage capacitor between successive CDS samples.

16. The method of any of claims 13 to 15, comprising powering down the amplifier between at least some CDS samples.

17. The method of claim 14, wherein sampling the output signal of the amplifier further comprises: analog-to-digital conversion of the amplifier output, and powering down the analog-to-digital converter between analog-to-digital conversions of at least some of the CDS samples.

18. The method of claim 12, wherein the amplifier comprises an Operational Transconductance Amplifier (OTA) configured to be capable of being powered down between at least some of the CDS samples.

19. An intermittent acquisition device for a differential input signal having components Vx and Vy for low-power signal processing, the device comprising:

means for providing a transconductance gain between the first and second inputs and the output;

means for initializing a storage capacitor comprising or coupled to a feedback network prior to Correlated Double Sampling (CDS) of an input signal; and

means for coupling Vx to the first input for a first sampling of CDS and then Vy to the first input without or prior to reinitializing the storage capacitor.

20. The apparatus of claim 19, comprising:

means for precharging the first input based on Vx;

means for further establishing the first input based on Vx;

means for precharging the first input based on Vy; and

means for further establishing the first input based on Vy.

Technical Field

This document relates generally, but not by way of limitation, to signal processing circuits and methods, and more particularly, but not by way of limitation, to correlated double sampling amplifiers suitable for low power instrumentation applications.

Background

There is a need for high quality, low power signal processing of sensors and other analog input signals, particularly in battery powered or implantable applications. Many signal acquisition and analog-to-digital signal conversion circuits do not provide accuracy and low noise signal processing performance while also providing low power consumption.

Disclosure of Invention

Illustrative, non-limiting examples of analog signal processing channels may include: an input amplifier circuit for sampling an analog input signal; an analog-to-digital converter (ADC) circuit for converting the amplifier buffered analog input signal to a digital value; a reference voltage circuit for providing a reference voltage for the ADC to perform analog-to-digital (A2D) conversion; digital post-processing circuitry for further performing signal processing (e.g., decimation or other filtering, etc.); and a control circuit for timing operation of the ADC and the switching circuit used in the signal processing path.

For battery powered or other low power applications, it is important to average the integrated power (e.g., the energy consumed per signal measurement). Some low power applications require only minimal signal acquisition and corresponding signal processing to make measurements. Powering down the signal processing components between signal acquisition and corresponding measurements may help to conserve power. Such powering down may include placing one or more circuits in a low power consumption state or may include shutting down one or more circuits, such as placing the circuits in a non-power consumption state.

Not all signal processing circuit components are equally suitable for powering down into a standby or inactive state. Some components may still have relatively high inactive static power consumption. The inventors of the present invention have realized that, among other things, it may be desirable to reduce or reduce the reactive power to a level equal to or below the self-discharge rate of a battery used to power the signal processing circuitry, for example.

Some components may additionally or alternatively have high active state power consumption or long on or off time requirements, which may result in poor power consumption characteristics. In low power signal acquisition and processing systems, both active and reactive power consumption are important figures of merit. It may also be helpful to provide flexibility for a user to configure a system that can span different throughput requirements, while extending power consumption to accommodate such different throughput requirements. In summary, if a user can be provided with a larger "power and throughput" scaling range, the same circuit can better meet the wider application requirements, leading to a more useful product.

The inventors of the present invention have also recognized that, among other things, to power down signal acquisition, processing and conversion circuitry, a Successive Approximation Routine (SAR) ADC may be configured to use a relatively fixed amount of energy per A2D conversion, and may be carefully configured to turn off the power supply to an inactive state with low inactive state leakage current, and voltage reference circuitry may also be carefully configured to support power cycling or power down to a low power state despite reducing the noise bandwidth of such reference voltage circuitry.

However, most signal conditioning amplifiers used to buffer, amplify or condition an input signal for further signal processing, signal conversion or both may face serious limitations, including incomplete power-down performance, design for resistive loads that consume power, and even choppers. Amplifiers are typically limited by slow power-up setup times and the chopping provided is not always well synchronized with the signal measurement to optimize power consumption.

For signal acquisition or signal conditioning amplifiers, the present inventors have recognized a need for: low reactive power consumption; starting from a power-down state quickly; low offset voltage; low reference input (RTI) noise (including low 1/f noise); good signal gain (e.g., reducing RTI noise of the ADC coupled to the amplifier output); good common mode rejection performance, particularly when used to obtain differential input signals from sensors or other sources.

This document describes subject matter that may include a signal acquisition or conditioning amplifier that may be configured and controlled to use Correlated Double Sampling (CDS) of a differential input signal and a storage capacitor in a capacitive or other feedback network, a low power Operational Transconductance Amplifier (OTA) that is capable of powering down between CDS samplings and may operate in a manner that provides low or efficient power consumption while still providing good performance characteristics. Amplifiers and other signal processing circuitry may scale power down where less signal measurement throughput is needed and scale power up where more signal measurement throughput is needed. This flexibility may help make the present method useful for a wide range of signal acquisition and measurement applications.

The following is a numbered list of non-limiting examples or aspects.

Aspect 1 may include or use subject matter (e.g., an apparatus, system, device, method, apparatus, or device-readable medium that performs an action, including instructions that when executed by a device cause the device to perform the action, or an article of manufacture), such as may include or use signal acquisition circuitry to perform Correlated Double Sampling (CDS) on a differential input signal having components Vx and Vy for low power signal processing. The signal acquisition circuit may include an amplifier that includes or is coupled to a feedback network. The feedback network may include or be coupled to a storage capacitor. The amplifier may be configured to provide a gain between the first and second amplifier inputs and the amplifier output. The initialisation switch may be arranged to initialise the storage capacitor prior to CDS of the input signal. The control circuit may be configured to control operation of the multiplexer to sequentially couple Vx and Vy to the first amplifier input for respective first and second samples of CDS without reinitializing the storage capacitor or prior to reinitializing the storage capacitor.

Aspect 2 may include or use, or may be combined with the subject matter of aspect 1, to optionally include or use a first precharge switch, which may be configured to be controlled by the control circuit to couple Vx to the first amplifier input through a first buffer amplifier to precharge the first amplifier input. A first set-up switch may be controlled by the control circuit to subsequently couple Vx to the first amplifier input without the first buffer amplifier to further set up the first amplifier input after precharging. A second precharge switch may be configured to be controlled by the control circuit to couple Vy to the first amplifier input through a second buffer amplifier to precharge the first amplifier input. A second set-up switch may be configured to be controlled by the control circuit to subsequently couple Vy to the first amplifier input without a second buffer amplifier to further set up the first amplifier input after precharging.

Aspect 3 may include, use, or may be combined with the subject matter of any one or any combination of aspects 1 or 2 to optionally include or use an initialization switch arranged to initialize the storage capacitor prior to CDS, including precharging, establishing, and sampling each of Vx and Vy prior to reinitializing the storage capacitor.

Aspect 4 may include, use, or may be combined with the subject matter of any one or any combination of aspects 1 to 3 to optionally include or use: an initialization switch is located between the amplifier output and the second amplifier input.

Aspect 5 may include, use, or may be combined with the subject matter of any one or any combination of aspects 1 to 4 to optionally include or use: the amplifier comprises an Operational Transconductance Amplifier (OTA).

Aspect 6 may include, use, or may be combined with the subject matter of any one or any combination of aspects 1 to 5 to optionally include or use: an analog-to-digital converter (ADC), for example, is coupled to the output of the amplifier. The control circuit may be configured to control the ADC to perform analog-to-digital conversion of the amplifier output samples of Vx and Vy.

Aspect 7 may include, use, or may be combined with the subject matter of any one or any combination of aspects 1 to 6 to optionally include or use: the ADC comprises a Successive Approximation Routine (SAR) ADC. The control circuitry may be configured to allow the ADC between intermittent CDS analogue to digital conversions to be powered down, for example may be performed cyclically or intermittently.

Aspect 8 may include, use, or may be combined with the subject matter of any one or any combination of aspects 1 through 7 to optionally include or use: the OTA is configured to power down between intermittent CDS samples.

Aspect 9 may include, use, or may be combined with the subject matter of any one or any combination of aspects 1 to 8 to optionally include or use: the amplifier comprises an Operational Transconductance Amplifier (OTA), for example, the feedback network comprises: a feedback capacitor between the amplifier output and the second amplifier input; and a storage capacitor between the second amplifier input and ground or other reference node.

Aspect 10 may include, use, or may be combined with the subject matter of any one or any combination of aspects 1 to 9 to optionally include or use: the first and second buffer amplifiers may be configured to be powered down by the control circuit, for example, between intermittent CDS sampling.

Aspect 11 may include, use, or may be combined with the subject matter of any one or any combination of aspects 1 to 10 to optionally include or use: a control circuit is configured to alternate a time series of multiplexes Vx and Vy between successive CDS samples to the first input amplifier input.

Aspect 12 may include, use, or may be combined with the subject matter of any one or any combination of aspects 1 through 11 to optionally include or use: a method of acquisition of an input signal of Correlated Double Sampling (CDS) of a differential input signal having components Vx and Vy for low power signal processing. The method may comprise initializing a storage capacitor which may be included in or coupled to a feedback network around the amplifier prior to CDS sampling of the input signal. Vx can be coupled to a first amplifier input of the amplifier for first sampling of CDS. Vy may be coupled to the first amplifier input of the amplifier for second sampling of CDS without or prior to reinitializing the storage capacitor. The difference in the amplifier output signal of the amplifier may be sampled, e.g., to provide CDS sampling of the differential input signal, in response to each of Vx and Vy without or prior to reinitializing the storage capacitor.

Aspect 13 may include, use, or may be combined with the subject matter of any one or any combination of aspects 1 to 12 to optionally include or use: the first amplifier input is precharged through a buffer amplifier to which Vx is applied. The first amplifier input may be further established without the buffer amplifier by applying Vx to the first amplifier input before Vx is sampled via the output signal of the amplifier. The first amplifier input may be precharged by a buffer amplifier to which Vy is applied. The first amplifier input may be further established without the buffer amplifier by applying Vy to the first amplifier input prior to sampling Vy via the output signal of the amplifier.

Aspect 14 may include, use, or may be combined with the subject matter of any one or any combination of aspects 1 to 13 to optionally include or use: after further setup to provide the first output sample of CDS, the output signal of the amplifier is sampled in response to applied Vx. After further setup to provide a second output sample of CDS, the output signal of the amplifier may be sampled in response to the applied Vy. Then, providing CDS samples based on a difference between the first output samples and the second output samples may be provided before or without reinitializing storage capacitors between the first output samples and the second output samples. The difference may be obtained by digitally subtracting the digitized value of the sampled amplifier output in response to Vy and Vx.

Aspect 15 may include, use, or may be combined with the subject matter of any one or any combination of aspects 1 to 14 to optionally include or use: the storage capacitor is reinitialized between successive CDS samples.

Aspect 16 may include, use, or may be combined with the subject matter of any one or any combination of aspects 1 through 15 to optionally include or use: the amplifier is powered down between at least some CDS samples.

Aspect 17 may include, use, or may be combined with the subject matter of any one or any combination of aspects 1 to 16 to optionally include or use: the sampling of the output signal of the amplifier may further comprise, for example: analog-to-digital conversion of the amplifier output, and powering down the analog-to-digital converter between analog-to-digital conversions of at least some of the CDS samples.

Aspect 18 may include, use, or may be combined with the subject matter of any one or any combination of aspects 1 to 17 to optionally include or use: the amplifier comprises, for example, an Operational Transconductance Amplifier (OTA) that may be configured to be capable of powering down between at least some CDS samples.

Aspect 19 may include, use, or may be combined with the subject matter of any one or any combination of aspects 1 to 18 to optionally include or use: an intermittent acquisition device for a differential input signal having components Vx and Vy for low power signal processing. The apparatus may include: means for providing a transconductance gain (e.g., OTA) between first and second inputs and an output; means for initializing a storage capacitor (e.g., comprising switches, control circuitry, etc.) comprising or coupled to a feedback network prior to Correlated Double Sampling (CDS) of an input signal; means for coupling Vx to the first input for a first sampling of CDS and then Vy to the first input (e.g., multiplexer, switch, control circuit, etc.) without or prior to reinitializing the storage capacitor.

Aspect 20 may include, use, or may be combined with the subject matter of any one or any combination of aspects 1-19 to optionally include or use: means for precharging the first input based on Vx (which may include, for example, a buffer amplifier and a multiplexer or switch and control circuitry); means for further establishing the first input based on Vx (which may include, for example, a multiplexer or a switch and a control circuit); means for precharging the first input based on Vy (which may include, for example, a buffer amplifier and a multiplexer or switch and control circuitry); and means for further establishing the first input based on Vy.

Each of these non-limiting examples may exist independently, or may be combined or combined in various permutations with one or more other examples.

This summary is intended to provide an overview of the subject matter of the present patent application. And are not intended to provide an exclusive or exhaustive explanation of the invention. Including the detailed description to provide more information about the present patent application.

Drawings

In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, and not by way of limitation, various embodiments discussed in this document.

Fig. 1A is a schematic diagram illustrating an example of a signal acquisition circuit.

Fig. 1B is a timing diagram illustrating an example of the operation of the signal acquisition circuit illustrated in fig. 1A.

Detailed Description

This document describes subject matter that may include a signal acquisition or conditioning amplifier that may be configured and controlled to use Correlated Double Sampling (CDS) of a differential input signal, and a storage capacitor in a capacitive or other feedback network, a low power Operational Transconductance Amplifier (OTA) capable of powering down between CDS samplings, and may operate in a manner that provides good performance characteristics while still providing low or high efficiency power consumption. Amplifiers and other signal processing circuitry may scale power down where less signal measurement throughput is needed and scale power up where more signal measurement throughput is needed. This flexibility may help make the present method useful for a wide range of signal acquisition and measurement applications.

Fig. 1A shows an example of a signal acquisition circuit 100, e.g. for performing Correlated Double Sampling (CDS) on a differential input signal having components Vx and Vy, e.g. for low power signal processing. FIG. 1B shows a timing diagram illustrating the operation of various components of signal acquisition circuit 100 shown in FIG. 1A. In fig. 1A, signal acquisition circuit 100 may include an amplifier 102 circuit, such as for signal acquisition or conditioning of an analog differential input signal having components Vx and Vy at differential signal input nodes 104A-B, respectively. In the example of fig. 1A, the amplifier 102 may include an Operational Transconductance Amplifier (OTA) that may amplify a voltage that is converted between a first (e.g., non-inverting) amplifier input 106A and a second (e.g., inverting) amplifier input 106B to a current that may be provided at an amplifier output 108 using a transconductance gain (Gm) of the OTA. The current provided on the amplifier output 108 may be used to charge or discharge a capacitive load to provide a final voltage signal on the amplifier output 108 that may be converted to a sampled digital output value at an ADC output 112 by a Successive Approximation Routine (SAR) or other analog-to-digital converter (ADC) 110. The various components Vx and Vy of the differential input signal may be successively converted to CDS versus sampled digital output values at the ADC output 112. The CDS sampling instance can be used to provide a differential digital output signal (corresponding to the difference between the Vx and Vy components of the differential analog input signal) by taking the difference between the two sampled digital output values on the ADC output 112 that forms the CDS pair sampling instance. The ADC110 may be powered down, for example between successive CDS sampling instances. ADC 100 may include or be coupled to a VOLTAGE REFERENCE circuit to provide a VOLTAGE for use in comparison during A2D conversion, where the VOLTAGE REFERENCE circuit may be configured to also be powered down, such as between successive CDS sampling instances, e.g., U.S. patent application No.15/969,175 entitled POWER-cycle VOLTAGE REFERENCE filed on 2018, 5/2 by Coln et al, which is incorporated herein by REFERENCE in its entirety, including a description of its REFERENCE VOLTAGE suitable for powering down.

If the acquired signal is sufficiently slow with respect to a fast succession of a pair of samples of CDS samples as shown and described in relation to fig. 1A, 1B, there will be almost identical differential signal components Vx and Vy during both samples of the CDS samples, and therefore the signal acquisition can still be considered "differential", and even if such alternative terms can be used, terms such as "quasi-differential" or "pseudo-differential" are not introduced herein to complicate this.

The capacitive load driven by the OTA amplifier 102 can include a storage capacitor Ci, such as can be driven and charged or discharged by the OTA amplifier 102 via a feedback network surrounding the OTA amplifier 102. In the example shown in fig. 1A, the feedback network is a capacitive feedback network, and may include a feedback capacitor Cf located between the amplifier output 108 and the second amplifier input 106B, for example. The storage capacitor Ci may be coupled to a feedback network, for example by being coupled between the second amplifier input 106B and a ground or reference node 113. A feedback network may be used to establish a closed loop gain around the OTA amplifier 102. In the example shown in FIG. 1A, the closed loop voltage gain can be shown as (Ci/Cf +1), as shown in equation 1.

(Vy–Vx)＝(V_ADC2–V_ADC1) /(Ci/Cf +1) equation 1

The use of a capacitive feedback network in conjunction with the OTA amplifier 102 may be helpful because the OTA amplifier 102 drives a capacitive load that, after charging to a stable voltage value at the OTA amplifier output 108, does not generate a quiescent current after charging to a stable voltage value at the OTA amplifier output 108, unlike a resistive load that continues to draw a quiescent current even after the amplifier output 108 reaches the stable voltage value. Another advantage of using the OTA amplifier 102 in conjunction with this configuration of the capacitive feedback network is that the OTA amplifier 102 can be "output compensated" so that its stability is achieved by the "dominant pole" provided by the load capacitance on the amplifier output 108 ("seeing" the capacitance of the capacitive feedback network and the capacitance of the SAR or other ADC circuit 110). It can be compared to an operational amplifier ("op amp") that provides a voltage gain rather than a transconductance gain, which typically requires an "internal" compensation capacitor (e.g., it can be conceptualized as "internal" to the op amp even though it may include an external capacitor coupled to an internal node of the op amp (e.g., between the first and second stages of a two-stage op amp). The internal compensation capacitor of the op-amp requires longer on and off times to stabilize, and therefore it is more difficult to power down the op-amp (and repeat the sampling of CDS, for example) than to similarly power down (and power up) the output compensated op-amp.

For the capacitive feedback network shown in fig. 1A, an initialization switch 114 may be included to initialize the voltage of the storage capacitor Ci at the second amplifier input 106B, which would otherwise be in a "floating" state when using a high input impedance OTA amplifier 102, e.g., each of the first and second inputs 106A-B of the OTA amplifier 102 is connected to a capacitive gate terminal of a Field Effect Transistor (FET) internal to the OTA amplifier. The initialization switch 114 may be located between the amplifier output 108 and the second amplifier input 106B to auto-zero the OTA amplifier 108 when the initialization switch 114 is closed, such that the amplifier output 108 and the first and second amplifier inputs 106A-B are effectively ideally biased to the same voltage when ignoring offset voltages between the first and second amplifier inputs 106A-B. In practice, a small non-ideal offset voltage will appear between the first and second amplifier inputs 106A-B, however, its effect may be reduced or limited by the CDS sampling techniques described herein.

The CDS sampling instance may be performed in the following manner. First, the initialization switch E may be closed to auto-zero the amplifier 102 and initialize the voltage on the storage capacitor Ci. The initialization switch E may then be opened, and the differential signal components Vx and Vy may be successively coupled to the first (e.g., non-inverting) input 106A of the amplifier 102, e.g., through respective switches B and D, respectively, before the initialization switch E is next closed or before the storage capacitor Ci is not initialized again, as shown in the timing diagram of fig. 1B, where a "high" signal indicates a closed switch. In response to each differential signal component Vx and Vy applied in turn to first input 106A of amplifier 102, the ADC may perform a sampled analog-to-digital (A2D) conversion of the voltage present on amplifier output 108, thereby generating a pair of sampled digital values of the CDS sample at times ADC1 and ADC2 as shown in fig. 1B. The difference between each of the pair of sampled digital values of the CDS sample represents the differential signal present between the differential input signal nodes 104A-B. Offset voltages and 1/f noise, as well as other noise (e.g., RTI noise of ADC 110), may be reduced or eliminated by CDS sampling techniques and settings. The OTA amplifier 102 can then be powered down if necessary, or even completely shut down until the next CDS sampling instance is needed. Similarly, the ADC110 may be powered down during this inactive period until the next CDS sampling instance is needed. At that time, the OTA amplifier 102, the ADC110, or both, may be powered back up and the storage capacitor Ci may be reinitialized, e.g., in the case described above, for another CDS sampling without reinitializing the storage capacitor Ci between each of the pair of samples in the CDS sampling instance.

Because the charging or discharging of the input capacitance at the first input 106A of the OTA amplifier 102 can be considered as an effective input current into the first input 106A of the OTA amplifier 102, a signal at the load input node 104A-B of a sensor or other signal source providing the input may be present to some degree. Some sensors may be affected by such a payload current, which may affect the measurement accuracy of the sensor. However, this may be improved by including buffer amplifiers 116A-B, each having a respective buffer amplifier input coupled to one of the differential signal inputs 104A-B, and each having a respective buffer amplifier output coupled to the first input 106A of the amplifier 102 via a respective one of the switches A and C. The buffer amplifiers 116A-B may each be used to precharge the first input 106A (powered by charge drawn from the power supply powering the buffer amplifiers, rather than by the sensor or other signal source, as the accuracy of the charge may be affected by such effective load current).

For example, as shown in the timing diagram of fig. 1A, by closing switch a, the differential signal component Vx may first be connected to the first input 104 of the amplifier 102 to precharge the first input 104 of the amplifier 102 through the buffer amplifier 116A. Switch a may then be opened and switch B may be closed to connect the actual signal component Vx to the first input 104 of the amplifier 102 to further establish stabilization, bypassing the buffer amplifier 116A, thereby yielding noise immunity or the ability of the buffer amplifier 116A to offset non-idealities.

Then, for example, as shown in the timing diagram of fig. 1A, by closing switch C, the differential signal component Vy may first be connected to the first input 104 of the amplifier 102 to precharge the first input 104 of the amplifier 102 through the buffer amplifier 116B. Then, switch C may be opened and switch D may be closed to connect the actual signal component Vy to the first input 104 of the amplifier 102 for further stabilization, bypassing the buffer amplifier 116B, thereby yielding noise immunity or the ability of the buffer amplifier 116B to offset non-idealities. The buffer amplifiers 116A-B may be matched to each other to improve performance. Control circuitry 118 may be included in signal acquisition circuitry 100 or coupled to signal acquisition circuitry 100 to provide control signals for operating the illustrated switches, ADCs 110, or both, to control the operations as illustrated in the timing diagram of fig. 1B. The control circuitry 118 may comprise dedicated digital hardware circuitry, programmable microcontroller circuitry, or may be implemented using one or more of a variety of other general purpose or special purpose circuits. Control circuitry 118 may control multiplexer circuitry, which may include, for example, some or all of switches A, B, C or D shown in FIG. 1A.

The control circuit 118 may be configured and operated to change the order of acquisition of the differential signal components Vx and Vy, such as alternating between successive CDS samples. For example, a first CDS instance sampling pair may be taken as Vx then Vy, a second CDS instance sampling pair as Vy then Vx, a third CDS instance sampling pair as Vx then Vy, and so on, similarly alternately providing signal inversion for the operation of the ADC to maintain consistency of the differential digital signals output at the ADC outputs 112.

The feedback network around the OTA amplifier 102 need not be a capacitive feedback network. Resistive feedback or a combination of resistive and reactive feedback may be provided, but the capacitive feedback as shown advantageously does not require a continuous quiescent current after the amplifier output 108 reaches a desired value.

Circuits, apparatus, systems, and methods such as those shown and described herein may help provide several advantages. For example, initializing the storage capacitor Ci to a bias voltage given by one component of the differential input signal (e.g., Vx) may help allow amplification of the differential signal (the difference between Vx and Vy) without overloading the amplifier 102. In one example, the use of CDS techniques described herein may help suppress offset and low frequency noise, particularly 1/f noise, in the signal acquisition circuit 100. CDS sampling may also help suppress a common mode signal that may be approximated by the differential signal component Vx. In an example, ADC110 may convert two sample values (based on Vx and Vy, respectively) into the digital domain, so that a simple digital subtraction of the two values may be used to obtain a difference or correlation. In one example, pre-charge buffers 116A-B can provide the charge needed to move the amplifier input capacitance between Vx and Vy so that the input current load is not seen by the sensor or other input signal source at its output, which the sensor may be sensitive to. All amplifiers and ADCs can be effectively powered-up cyclically, for example, by turning off power to one or all such components between CDS sampling instances, which can be done frequently or infrequently as required by the particular application.

The above description includes reference to the accompanying drawings, which form a part hereof. The drawings show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as "examples. Such examples may include elements in addition to those shown or described. However, the inventors also contemplate examples providing only those elements shown or described. Moreover, the inventors also contemplate examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), with respect to particular examples (or one or more aspects thereof), or other examples (or one or more aspects thereof) shown or described herein.

If usage between this document and any document incorporated by reference is inconsistent, then usage in this document controls.

In this document, the terms "a" or "an" are used in patent documents to include one or more, independent of "at least one" or "one or more" of any other circumstance or usage. In this document, unless otherwise specified, the term "or" is used to indicate a non-exclusive, e.g., "a or B" includes "a but not B", "B but not a" and "a and B". In this document, the terms "including" and "in which" are used as equivalents of the respective terms "comprising" and "wherein". Also, in the following claims, the terms "comprises" and "comprising" are open-ended, that is, a system, apparatus, article, composition, formulation, or process that includes elements in addition to those listed after the term in a claim are considered to be within the scope of that claim. Furthermore, in the following claims, the terms "first," "second," and "third," etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.

Unless the context indicates otherwise, geometric terms such as "parallel," "perpendicular," "circular," or "square" are not intended to require absolute mathematical precision. Rather, such geometric terms are susceptible to variations due to manufacturing or equivalent function. For example, if an element is described as "circular" or "generally circular," that description still includes components that are not exactly circular (e.g., components that are slightly oblong or polygonal).

The method examples described herein may be machine or computer implemented at least in part. Some examples may include a computer-readable or machine-readable medium encoded with instructions operable to configure an electronic device to perform a method as described in the above examples. Implementations of such methods may include code, e.g., microcode, assembly language code, a high-level language code, and the like. Such code may include computer readable instructions for performing various methods. The code may form part of a computer program product. Further, in an example, the code can be tangibly stored on one or more volatile, non-transitory, or non-volatile tangible computer-readable media, e.g., during execution or at other times. Examples of such tangible computer-readable media may include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, Random Access Memories (RAMs), Read Only Memories (ROMs), and the like.

The above description is intended to be illustrative and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used, for example, by one of ordinary skill in the art upon reviewing the above description. The abstract is provided to comply with 37c.f.r. § 1.72(b), to allow the reader to quickly ascertain the nature of the technical disclosure. This document is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing detailed description, various features may be grouped together to simplify the present disclosure. This should not be construed to mean that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the detailed description as examples or embodiments, with each claim standing on its own as a separate embodiment, and it is contemplated that such embodiments may be combined with each other in various combinations or permutations. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.