阅读说明：本技术 光电转换元件和光电转换元件的制造方法 (Photoelectric conversion element and method for manufacturing photoelectric conversion element ) 是由 吉河训太 河崎勇人 小泉玄介 于 2019-06-04 设计创作，主要内容包括：提供能够实现输出提高的光电转换元件。光电转换元件(1)包含：在半导体基板(11)的背面侧的一部分依次层叠有本征半导体层(23)和第一导电型半导体层(25)的第一区域(7)；以及在半导体基板(11)的背面侧的另一部分依次层叠有本征半导体层(33)和第二导电型半导体层(35)的第二区域(8),在该背面接合型的光电转换元件中,第一区域(7)中的本征半导体层(23)的折射率比第二区域(8)中的本征半导体层(33)的折射率小。(Provided is a photoelectric conversion element capable of realizing an improvement in output. A photoelectric conversion element (1) comprises: a first region (7) in which an intrinsic semiconductor layer (23) and a first conductivity type semiconductor layer (25) are sequentially stacked on a portion of the back surface side of a semiconductor substrate (11); and a second region (8) in which an intrinsic semiconductor layer (33) and a second conductivity type semiconductor layer (35) are sequentially laminated on another portion of the back surface side of the semiconductor substrate (11), wherein the refractive index of the intrinsic semiconductor layer (23) in the first region (7) is smaller than the refractive index of the intrinsic semiconductor layer (33) in the second region (8).)

1. A back-junction photoelectric conversion element includes: a first region in which an intrinsic semiconductor layer and a first conductivity type semiconductor layer are sequentially stacked on a portion of one main surface side of a semiconductor substrate; and a second region in which an intrinsic semiconductor layer and a second conductivity type semiconductor layer are sequentially stacked on the other portion of the semiconductor substrate on the one main surface side,

the intrinsic semiconductor layer in the first region has a refractive index smaller than that of the intrinsic semiconductor layer in the second region.

2. The photoelectric conversion element according to claim 1,

the photoelectric conversion element further includes an overlap region which is a region between the first region and the second region, and a first intrinsic semiconductor layer and a first conductive semiconductor layer extending from the intrinsic semiconductor layer and the first conductive semiconductor layer in the first region are overlapped on a second intrinsic semiconductor layer and a second conductive semiconductor layer extending from the intrinsic semiconductor layer and the second conductive semiconductor layer in the second region.

3. The photoelectric conversion element according to claim 2,

when the film thickness of the first conductivity type semiconductor layer in the overlap region is T1, the film thickness of the first intrinsic semiconductor layer sandwiched between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer in the overlap region is T2, the film thickness of the first conductivity type semiconductor layer in the first region is T3, and the film thickness of the intrinsic semiconductor layer in the first region is T4, the film thicknesses T1, T2, T3, and T4 satisfy the following expression (1).

T2/(T1+T2)＜T4/(T3+T4)···(1)

4. The photoelectric conversion element according to claim 2 or 3,

regarding a total film thickness of the second intrinsic semiconductor layer, the second conductive type semiconductor layer, the first intrinsic semiconductor layer, and the first conductive type semiconductor layer in the overlap region, it is smaller than a sum of a total film thickness of the intrinsic semiconductor layer and the first conductive type semiconductor layer in the first region and a total film thickness of the intrinsic semiconductor layer and the second conductive type semiconductor layer in the second region.

5. The photoelectric conversion element according to any one of claims 2 to 4, comprising:

a first electrode layer corresponding to the first conductive type semiconductor layer in the first region; and

a second electrode layer corresponding to the second conductive type semiconductor layer in the second region,

the first conductivity type is an n-type,

the second conductivity type is a p-type,

the first electrode layer extends to cover a part or all of the first conductive type semiconductor layer in the overlap region.

6. The photoelectric conversion element according to claim 5,

the first electrode layer extends to cover the entirety of the first conductive type semiconductor layer in the overlap region and a portion of the second conductive type semiconductor layer in the second region.

7. A method for manufacturing a back-junction photoelectric conversion element, the photoelectric conversion element comprising: a first region in which an intrinsic semiconductor layer and a first conductivity type semiconductor layer are sequentially stacked on a portion of one main surface side of a semiconductor substrate; a second region in which an intrinsic semiconductor layer and a second conductivity type semiconductor layer are sequentially stacked on the other portion of the semiconductor substrate on the one main surface side; and an overlap region which is a region between the first region and the second region, and on which a first intrinsic semiconductor layer and a first conductive type semiconductor layer extending from the intrinsic semiconductor layer and the first conductive type semiconductor layer in the first region are overlapped, the second intrinsic semiconductor layer and the second conductive type semiconductor layer extending from the intrinsic semiconductor layer and the second conductive type semiconductor layer in the second region, wherein the method of manufacturing a photoelectric conversion element includes:

a second-conductivity-type semiconductor layer stacking step of sequentially stacking a precursor of an intrinsic semiconductor layer and a precursor of a second-conductivity-type semiconductor layer in the first region, the second region, and the overlapping region on the one principal surface side of the semiconductor substrate;

a second conductivity type semiconductor layer forming step of forming a part of the intrinsic semiconductor layer in the first region, forming the intrinsic semiconductor layer and the second conductivity type semiconductor layer in the second region, and forming the second intrinsic semiconductor layer and the second conductivity type semiconductor layer in the overlap region by removing a part of the precursor of the second conductivity type semiconductor layer and a part of the precursor of the intrinsic semiconductor layer in the first region by using a hydrogen plasma etching method; and

and a first conductive type semiconductor layer forming step of forming a remaining part of the intrinsic semiconductor layer and the first conductive type semiconductor layer on a part of the intrinsic semiconductor layer in the first region, and forming the first intrinsic semiconductor layer and the first conductive type semiconductor layer on the second conductive type semiconductor layer in the overlap region.

Technical Field

The present invention relates to a back-junction-type (also referred to as back-contact-type or back-electrode-type) photoelectric conversion element and a method for manufacturing the photoelectric conversion element.

Background

As photoelectric conversion elements such as solar cells using semiconductor substrates, there are, for example, hetero-junction-type (hereinafter, also referred to as a double-junction-type with respect to a back-junction-type, and also referred to as a double-electrode-type) photoelectric conversion elements in which semiconductor layers are formed on both surfaces of a light receiving surface side and a back surface side, and back-junction-type photoelectric conversion elements in which electrodes are formed only on the back surface side. In the double-sided junction type photoelectric conversion element, an electrode is formed on the light receiving surface side, and therefore sunlight is blocked by the electrode. On the other hand, in the back-junction photoelectric conversion element, since no electrode is formed on the light-receiving surface side, the light receiving rate of sunlight is higher than that of the double-junction photoelectric conversion element. Patent document 1 discloses a back-contact type solar cell as a back-contact type photoelectric conversion element.

The solar cell (photoelectric conversion element) described in patent document 1 includes: an intrinsic semiconductor layer, a first conductivity type (e.g., n-type) semiconductor layer, and a first electrode layer which are stacked in this order on a part of the back surface side of the semiconductor substrate; and an intrinsic semiconductor layer, a second conductivity type (e.g., p-type) semiconductor layer, and a second electrode layer sequentially stacked on another portion of the back surface side of the semiconductor substrate.

Patent document 1: japanese patent laid-open publication No. 2013-131586.

As described above, the output of the back-junction photoelectric conversion element is higher than that of the double-junction photoelectric conversion element, but further improvement in output is desired.

Disclosure of Invention

The present invention aims to provide a photoelectric conversion element capable of improving output and a method for manufacturing the photoelectric conversion element.

The photoelectric conversion element of the present invention includes: a first region in which an intrinsic semiconductor layer and a first conductivity type semiconductor layer are sequentially stacked on a portion of one main surface side of a semiconductor substrate; and a second region in which an intrinsic semiconductor layer and a second conductivity type semiconductor layer are sequentially stacked on the other portion of the semiconductor substrate on the one principal surface side, wherein in the back-junction photoelectric conversion element, the refractive index of the intrinsic semiconductor layer in the first region is smaller than the refractive index of the intrinsic semiconductor layer in the second region.

In the method for manufacturing a photoelectric conversion element of the present invention, the photoelectric conversion element includes: a first region in which an intrinsic semiconductor layer and a first conductivity type semiconductor layer are sequentially stacked on a portion of one main surface side of a semiconductor substrate; a second region in which an intrinsic semiconductor layer and a second conductivity type semiconductor layer are sequentially stacked on the other portion of the semiconductor substrate on the one main surface side; and an overlap region which is a region between the first region and the second region, and on which a first intrinsic semiconductor layer and a first conductive semiconductor layer extending from the intrinsic semiconductor layer and the first conductive semiconductor layer in the first region are overlapped, the second intrinsic semiconductor layer and the second conductive semiconductor layer extending from the intrinsic semiconductor layer and the second conductive semiconductor layer in the second region, wherein the method of manufacturing the photoelectric conversion element includes: a second conductivity type semiconductor layer stacking step of sequentially stacking a precursor of the intrinsic semiconductor layer and a precursor of the second conductivity type semiconductor layer in the first region, the second region, and the overlapping region on the one principal surface side of the semiconductor substrate; a second conductivity type semiconductor layer forming step of forming a part of the intrinsic semiconductor layer in the first region, forming the intrinsic semiconductor layer and the second conductivity type semiconductor layer in the second region, and forming the second intrinsic semiconductor layer and the second conductivity type semiconductor layer in the overlap region by removing a part of the precursor of the second conductivity type semiconductor layer and the precursor of the intrinsic semiconductor layer in the first region by using a hydrogen plasma etching method; and a first conductive type semiconductor layer forming step of forming a remaining part of the intrinsic semiconductor layer and the first conductive type semiconductor layer on a part of the intrinsic semiconductor layer in the first region, and forming the first intrinsic semiconductor layer and the first conductive type semiconductor layer on the second conductive type semiconductor layer in the overlapping region.

According to the present invention, the output of the photoelectric conversion element is improved.

Drawings

Fig. 1 is a side view showing an example of a photoelectric conversion module according to the present embodiment.

Fig. 2 is a view of the photoelectric conversion element of the present embodiment as viewed from the back side.

Fig. 3 is a sectional view of the photoelectric conversion element of fig. 2 taken along line III-III.

Fig. 4A is a view showing a second conductivity type semiconductor layer forming step in the method for manufacturing a photoelectric conversion element according to the present embodiment.

Fig. 4B is a view showing a second conductive type semiconductor layer removal step in the method for manufacturing a photoelectric conversion element according to the present embodiment.

Fig. 4C is a view showing a first conductive type semiconductor layer forming step in the method for manufacturing a photoelectric conversion element according to the present embodiment.

Fig. 4D is a diagram illustrating an electrode layer formation step in the method for manufacturing a photoelectric conversion element according to the present embodiment.

Fig. 5 is a view of a photoelectric conversion element according to a modification of the present embodiment, as viewed from the back side.

Detailed Description

Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding portions are denoted by the same reference numerals. Note that, for convenience, hatching, component reference numerals, and the like may be omitted, but in this case, reference is made to other drawings.

(photoelectric conversion Module)

Fig. 1 is a side view showing an example of a photoelectric conversion module according to the present embodiment. The photoelectric conversion module 100 includes a plurality of photoelectric conversion elements 1 arranged in a two-dimensional shape.

The photoelectric conversion elements 1 are connected in series and/or in parallel by the wiring member 2. Specifically, the wiring member 2 is connected to a bus portion (described later) in the electrode layer of the photoelectric conversion element 1. The wiring member 2 is a known internal connector such as a tab wire.

The photoelectric conversion element 1 and the wiring member 2 are sandwiched between the light-receiving-surface protection member 3 and the back-surface protection member 4. The photoelectric conversion element 1 and the wiring member 2 are sealed by filling a liquid or solid sealing material 5 between the light-receiving-surface protection member 3 and the back-surface protection member 4. The light-receiving-surface protection member 3 is, for example, a glass substrate, and the back-surface protection member 4 is a glass substrate or a metal plate. The sealing material 5 is, for example, a transparent resin.

The photoelectric conversion element 1 will be described in detail below.

(photoelectric conversion element)

Fig. 2 is a view of the photoelectric conversion element of the present embodiment as viewed from the back side. The photoelectric conversion element 1 shown in fig. 2 is a back-junction type photoelectric conversion element. The photoelectric conversion element 1 includes an n-type (first conductivity type) semiconductor substrate 11 having 2 main surfaces, and has an n-type region (first region) 7 and a p-type (second conductivity type) region (second region) 8 on the main surface of the semiconductor substrate 11.

The n-type region 7 is formed in a so-called comb-like shape, and includes a plurality of finger portions 7f corresponding to comb teeth and a bus portion 7b corresponding to a support portion of the comb teeth. The bus portion 7b extends in a first direction (X direction) along one side portion of the semiconductor substrate 11, and the finger portions 7f extend from the bus portion 7b in a second direction (Y direction) intersecting the first direction.

Similarly, the p-type region 8 has a so-called comb-like shape, and includes a plurality of finger portions 8f corresponding to comb teeth and a bus portion 8b corresponding to a support portion of the comb teeth. The bus portion 8b extends in the first direction (X direction) along the other side portion of the semiconductor substrate 11 facing the one side portion, and the finger portions 8f extend in the second direction (Y direction) from the bus portion 8 b.

The fingers 7f and the fingers 8f are alternately arranged in the first direction (X direction).

N-type region 7 and p-type region 8 may be formed in a stripe shape.

There is an overlap region R between n-type region 7 and p-type region 8. The overlap region R is a region where the p-type semiconductor layer and the n-type semiconductor layer overlap each other, as will be described later.

Fig. 3 is a sectional view of the photoelectric conversion element of fig. 2 taken along line III-III. As shown in fig. 3, the photoelectric conversion element 1 includes an intrinsic semiconductor layer 13 laminated on a light receiving surface side, which is a light receiving side, of the main surfaces of the semiconductor substrate 11. The photoelectric conversion element 1 includes an intrinsic semiconductor layer 23, an n-type (first conductivity type) semiconductor layer 25, and a first electrode layer 27, which are sequentially stacked on a portion (mainly the n-type region 7) of the back surface side, which is a main surface (one main surface) of the main surface of the semiconductor substrate 11 on the opposite side of the light receiving surface. The photoelectric conversion element 1 further includes an intrinsic semiconductor layer 33, a p-type (second conductivity type) semiconductor layer 35, and a second electrode layer 37, which are sequentially stacked on the other portion (mainly, the p-type region 8) on the back surface side of the semiconductor substrate 11.

The semiconductor substrate 11 is made of a crystalline silicon material such as single crystal silicon or polycrystalline silicon. The semiconductor substrate 11 is, for example, an n-type semiconductor substrate in which a crystalline silicon material is doped with an n-type dopant. The n-type dopant is, for example, phosphorus (P).

The semiconductor substrate 11 functions as a photoelectric conversion substrate that absorbs incident light from the light receiving surface side to generate photo carriers (electrons and positive holes).

By using crystalline silicon as a material of the semiconductor substrate 11, a relatively high output (stable output regardless of illuminance) can be obtained even when the dark current is relatively small and the intensity of incident light is low.

The intrinsic semiconductor layer 13 is formed on the light-receiving surface side of the semiconductor substrate 11. The intrinsic semiconductor layer 33 is formed on the p-type region 8 and the overlap region R on the back surface side of the semiconductor substrate 11.

The intrinsic semiconductor layer 23 is formed on the n-type region 7 and the overlap region R on the back surface side of the semiconductor substrate 11. In this embodiment, the intrinsic semiconductor layer 23 includes 2 layers 23a and 23 b. Two layers 23a, 23b of the intrinsic semiconductor layer 23 are formed in the n-type region 7 on the back surface side of the semiconductor substrate 11, and only one layer 23b of the intrinsic semiconductor layer 23 is formed in the overlap region R on the back surface side of the semiconductor substrate 11. In addition, the 2 layers 23a, 23b of the intrinsic semiconductor layer 23 in the n-type region 7 are integrally formed to such an extent that the boundaries of these layers cannot be visually confirmed.

The intrinsic semiconductor layers 13, 23, 33 are formed of, for example, an intrinsic (i-type) amorphous silicon material.

The intrinsic semiconductor layers 13, 23, and 33 function as passivation layers, and suppress recombination of carriers generated on the semiconductor substrate 11, thereby improving carrier recovery efficiency.

An antireflection layer made of a material such as SiO, SiN, or SiON may be provided on the intrinsic semiconductor layer 13 on the light-receiving surface side of the semiconductor substrate 11.

The n-type semiconductor layer 25 is formed on the intrinsic semiconductor layer 23, that is, on the n-type region 7 and the overlap region R on the back surface side of the semiconductor substrate 11. The n-type semiconductor layer 25 is formed of, for example, an amorphous silicon material. The n-type semiconductor layer 25 is, for example, an n-type semiconductor layer obtained by doping an amorphous silicon material with an n-type dopant (for example, the above-mentioned phosphorus (P)).

The p-type semiconductor layer 35 is formed on the intrinsic semiconductor layer 33, i.e., the p-type region 8 and the overlap region R on the back surface side of the semiconductor substrate 11. The p-type semiconductor layer 35 is formed of, for example, an amorphous silicon material. The p-type semiconductor layer 35 is, for example, a p-type semiconductor layer obtained by doping an amorphous silicon material with a p-type dopant. The p-type dopant includes, for example, boron (B).

In the overlap region R, a portion 23b of the intrinsic semiconductor layer 23 and the n-type semiconductor layer 25 overlap on the adjacent intrinsic semiconductor layer 33 and the p-type semiconductor layer 35. Specifically, in the overlap region R, the intrinsic semiconductor layer (first intrinsic semiconductor layer) 23b extending from the portion 23b of the intrinsic semiconductor layer 23 in the n-type region 7, and the n-type semiconductor layer 25 extending from the n-type semiconductor layer 25 in the n-type region 7 are overlapped on the intrinsic semiconductor layer (second intrinsic semiconductor layer) 33 extending from the intrinsic semiconductor layer 33 in the p-type region 8, and the p-type semiconductor layer 35 extending from the p-type semiconductor layer 35 in the p-type region 8.

When the film thickness of the n-type semiconductor layer 25 in the overlap region R is T1, the film thickness of the intrinsic semiconductor layer 23b sandwiched between the n-type semiconductor layer 25 and the p-type semiconductor layer 35 in the overlap region R is T2, the film thickness of the n-type semiconductor layer 25 in the n-type region 7 is T3, and the film thickness of the intrinsic semiconductor layer 23 in the n-type region 7 is T4, these film thicknesses T1, T2, T3, and T4 satisfy the relationship of the following expression (1).

T2/(T1+T2)＜T4/(T3+T4)···(1)

For example, the film thicknesses T1 and T2 are film thicknesses at the portions of the n-type semiconductor layer 25 in the overlap region R that are farthest from the back surface of the semiconductor substrate 11. The film thicknesses T3 and T4 are average film thicknesses in the n-type region 7.

In other words, with respect to the total film thickness (e.g., maximum film thickness) T11 of the intrinsic semiconductor layer 33, the second conductivity type semiconductor layer 35, the intrinsic semiconductor layer 23b, and the first conductivity type semiconductor layer 25 in the overlap region R, it is smaller than the sum of the total film thickness (e.g., average film thickness) T12 of the intrinsic semiconductor layer 23 and the n type semiconductor layer 25 in the n type region 7 and the total film thickness (e.g., average film thickness) T13 of the intrinsic semiconductor layer 33 and the second conductivity type semiconductor layer 35 in the p type region 8.

T11＜T12+T13

The refractive index of intrinsic semiconductor layer 23 in n-type region 7 is smaller than the refractive index of intrinsic semiconductor layer 33 in p-type region 8 (details will be described later).

The first electrode layer 27 is formed on the n-type semiconductor layer 25 in the n-type region 7 on the back surface side of the semiconductor substrate 11, corresponding to the n-type semiconductor layer 25. Further, the first electrode layer 27 extends to cover a part of the n-type semiconductor layer 25 in the overlap region R. The first electrode layer 27 may extend to cover the entire n-type semiconductor layer 25 in the overlap region R.

The second electrode layer 37 is formed on the p-type semiconductor layer 35 in the p-type region 8 on the back surface side of the semiconductor substrate 11, corresponding to the p-type semiconductor layer 35. The second electrode layer 37 is separated from the first electrode layer 27.

The first electrode layer 27 and the second electrode layer 37 may be formed of a transparent electrode layer and a metal electrode layer, or may be formed of only a metal electrode layer. The transparent electrode layer is formed of a transparent conductive material. Examples of the transparent conductive material include ITO (Indium Tin Oxide: a composite Oxide of Indium Oxide and Tin Oxide). The metal electrode layer is formed of a conductive paste material containing metal powder such as silver.

Next, a method for manufacturing the photoelectric conversion element 1 of the present embodiment, in particular, a method for forming each layer on the back side will be described with reference to fig. 4A to 4D. Fig. 4A to 4D are views showing a second conductivity type semiconductor layer stacking step, a second conductivity type semiconductor layer forming step, a first conductivity type semiconductor layer forming step, and an electrode layer forming step in the method for manufacturing a photoelectric conversion element according to the present embodiment, respectively.

First, as shown in fig. 4A, a precursor 33Z of an intrinsic semiconductor layer and a precursor 35Z of a p-type semiconductor layer are sequentially stacked on the entire back surface side of the semiconductor substrate 11, specifically, on the n-type region 7, the p-type region 8, and the overlap region R (second conductivity type semiconductor layer stacking step).

For example, the precursor 33Z of the intrinsic semiconductor layer and the precursor 35Z of the p-type semiconductor layer are stacked in this order on the entire back surface side of the semiconductor substrate 11 by CVD.

Next, as shown in fig. 4B, a part of the back surface side of the semiconductor substrate 11, specifically, a part of the precursor 35Z of the p-type semiconductor layer and the precursor 33Z of the intrinsic semiconductor layer in the n-type region 7 is removed by hydrogen plasma etching. Thereby, the part 23a of the intrinsic semiconductor layer 23, the intrinsic semiconductor layer 33, and the p-type semiconductor layer 35 are formed on the other part of the back surface side of the semiconductor substrate 11. Specifically, a part 23a of the intrinsic semiconductor layer 23 is formed in the n-type region 7, the intrinsic semiconductor layer 33 and the p-type semiconductor layer 35 are formed in the p-type region 8, and the intrinsic semiconductor layer (second intrinsic semiconductor layer) 33 and the p-type semiconductor layer 35 are formed in the overlap region R (second conductive semiconductor layer forming step).

For example, the precursor 35Z of the p-type semiconductor layer and a part of the precursor 33Z of the intrinsic semiconductor layer in the n-type region 7 are removed by a hydrogen plasma etching method using the mask M. At this time, in the overlap region R under the mask M, a part of the precursor 35Z of the p-type semiconductor layer is also etched.

The hydrogen plasma etching is adjusted so that a part 23a of the intrinsic semiconductor layer remains in a part of the back surface side of the semiconductor substrate 11, specifically, in the n-type region 7.

Next, as shown in fig. 4C, a remaining part 23b of the intrinsic semiconductor layer 23 and the n-type semiconductor layer 25 are formed on a part of the back surface side of the semiconductor substrate 11. Specifically, the remaining part 23b of the intrinsic semiconductor layer 23 and the n-type semiconductor layer 25 are formed on the part 23a of the intrinsic semiconductor layer 23 in the n-type region 7, and the intrinsic semiconductor layer (first intrinsic semiconductor layer) 23b and the n-type semiconductor layer 25 are formed on the second conductivity type semiconductor layer 35 in the overlap region R (first conductivity type semiconductor layer forming step).

For example, the remaining part 23b of the intrinsic semiconductor layer 23 and the n-type semiconductor layer 25 are stacked on the n-type region 7 on the back surface side of the semiconductor substrate 11 by a CVD method using the mask M as it is. At this time, in the overlap region R under the mask M, the stacking of the n-type semiconductor layer 25 and the part 23b of the intrinsic semiconductor layer 23 is also performed.

In this way, in the overlap region R, the intrinsic semiconductor layer 23b overlapping on the p-type semiconductor layer 35 corresponds to the part 23b of the intrinsic semiconductor layer 23 in the n-type region 7.

Thus, as described above, the film thickness T1 of the n-type semiconductor layer 25 in the overlap region R, the film thickness T2 of the intrinsic semiconductor layer 23b sandwiched between the n-type semiconductor layer 25 and the p-type semiconductor layer 35 in the overlap region R, the film thickness T3 of the n-type semiconductor layer 25 in the n-type region 7, and the film thickness T4 of the intrinsic semiconductor layer 23 in the n-type region 7 satisfy the relationship of the above expression (1).

In other words, as described above, the total film thickness T11 of the intrinsic semiconductor layer 33, the second conductivity type semiconductor layer 35, the intrinsic semiconductor layer 23b, and the first conductivity type semiconductor layer 25 in the overlap region R is smaller than the sum of the total film thickness T12 of the intrinsic semiconductor layer 23 and the n type semiconductor layer 25 in the n type region 7 and the total film thickness T13 of the intrinsic semiconductor layer 33 and the second conductivity type semiconductor layer 35 in the p type region 8.

In addition, a portion 23a of the intrinsic semiconductor layer 23 is formed by hydrogen plasma etching, and a remaining portion 23b of the intrinsic semiconductor layer 23 is formed thereon, whereby the refractive index of the intrinsic semiconductor layer 23 in the n-type region 7 is smaller than the refractive index of the intrinsic semiconductor layer 33 in the p-type region 8. This is considered to be an effect of hydrogen plasma etching, for example, to make the surface of the part 23a of the intrinsic semiconductor layer 23 porous, or to form voids on the surface of the part 23a of the intrinsic semiconductor layer 23, thereby containing hydrogen in the intrinsic semiconductor layer 23.

When the n-type semiconductor layer 25 is formed in the low refractive region of the intrinsic semiconductor layer 23, phosphorus, which is a doping impurity of the n-type semiconductor layer 25, is slightly diffused (in other words, doped) into the intrinsic semiconductor layer 23, and the resistivity of the intrinsic semiconductor layer 23 is reduced.

Thereby, in the n-type region 7, the lifetime of carriers is maintained, and the resistance of the intrinsic semiconductor layer 23 becomes small. Therefore, the photoelectric conversion element 1 has a reduced series resistance and an improved output.

Further, the formation method of the n-type semiconductor layer 25 and the part 23b of the intrinsic semiconductor layer in the n-type region 7 and the overlap region R is not limited thereto.

For example, after the precursor of the part 23b of the intrinsic semiconductor layer and the precursor of the n-type semiconductor layer 25 are stacked on the entire back surface side of the semiconductor substrate 11 by the CVD method, the part 23b of the intrinsic semiconductor layer and the n-type semiconductor layer 25 may be formed by the etching method. As an etching solution for the precursor of the n-type semiconductor layer 25, for example, an alkaline solution such as potassium hydroxide is cited.

Next, as shown in fig. 4D, a first electrode layer 27 is formed on the n-type semiconductor layer 25, and a second electrode layer 37 is formed on the p-type semiconductor layer 35 (electrode layer forming step). At this time, the first electrode layer 27 is extended so as to cover a part or the whole of the n-type semiconductor layer 25 in the overlap region R, and the first electrode layer 27 is formed. In addition, the second electrode layer 37 is formed so as to be separated from the first electrode layer 27.

For example, after an electrode layer is laminated on the entire back surface side of the semiconductor substrate 11, the first electrode layer 27 and the second electrode layer 37 may be formed by etching. Alternatively, when an electrode layer is laminated on the back surface side of the semiconductor substrate 11, the first electrode layer 27 and the second electrode layer 37 may be formed using a mask.

The transparent electrode layer of the first electrode layer 27 and the second electrode layer 37 may be stacked by a sputtering method. Further, the first electrode layer 27 and the second electrode layer 37 may be stacked by a printing method or a vapor deposition method.

Through the above steps, the photoelectric conversion element 1 shown in fig. 3 is obtained.

As described above, according to the method of manufacturing a photoelectric conversion element of the present embodiment, the part 23a of the intrinsic semiconductor layer 23 in the n-type region (first region) 7 is formed by hydrogen plasma etching, and the remaining part 23b of the intrinsic semiconductor layer 23 is formed thereon.

According to the photoelectric conversion element 1 manufactured as such, the refractive index of the intrinsic semiconductor layer 23 in the n-type region (first region) 7 is smaller than the refractive index of the intrinsic semiconductor layer 33 in the p-type region (second region) 8. Thereby, in the n-type region (first region) 7, the lifetime of carriers is maintained, and the resistance of the intrinsic semiconductor layer 23 becomes small. Therefore, the photoelectric conversion element 1 has a reduced series resistance and an improved output.

In the above-described embodiment, the first conductivity type semiconductor layer 25 is an n-type semiconductor layer, the second conductivity type semiconductor layer 35 is a p-type semiconductor layer, the first region 7 is an n-type region, and the second region 8 is a p-type region, but the first conductivity type semiconductor layer 25 may be replaced with a p-type semiconductor layer, the second conductivity type semiconductor layer 35 may be replaced with an n-type semiconductor layer, the first region 7 may be replaced with a p-type region, and the second region 8 may be replaced with an n-type region.

In this case, by hydrogen plasma etching, a part 23a of the intrinsic semiconductor layer 23 in the p-type region (first region) 7 is formed, and a remaining part 23b of the intrinsic semiconductor layer 23 is formed thereon.

According to the photoelectric conversion element 1 manufactured as such, the refractive index of the intrinsic semiconductor layer 23 in the p-type region (first region) 7 is smaller than the refractive index of the intrinsic semiconductor layer 33 in the n-type region (second region) 8. Thereby, in the p-type region (first region) 7, the lifetime of carriers is maintained, and the resistance of the intrinsic semiconductor layer 23 becomes small. Therefore, the photoelectric conversion element 1 has a reduced series resistance and an improved output.

In this way, if the refractive index of the intrinsic semiconductor layer of either one of the n-type region and the p-type region is smaller than that of the intrinsic semiconductor layer of the other region, the series resistance is reduced and the output is improved in the photoelectric conversion element 1.

In addition, when the resistance of the intrinsic semiconductor layer of the p-type region is low, it is considered that the diffusion of a p-type dopant (for example, boron (B)) in the p-type semiconductor layer is increased, and the n-type semiconductor substrate (for example, the lifetime of carriers in the semiconductor substrate) may be affected. In contrast, when the resistance of the intrinsic semiconductor layer in the n-type region is low, it is considered that the n-type semiconductor substrate is not affected even if the diffusion of the n-type dopant (for example, phosphorus (P)) in the n-type semiconductor layer is increased. That is, the influence of the diffusion of the n-type dopant (e.g., phosphorus (P)) on the n-type semiconductor substrate (e.g., the influence on the lifetime of carriers) is considered to be smaller than the influence of the diffusion of the P-type dopant (e.g., boron (B)) on the n-type semiconductor substrate. Accordingly, it is considered preferable that the refractive index of the intrinsic semiconductor layer 23 in the n-type region 7 is smaller than the refractive index of the intrinsic semiconductor layer 33 in the p-type region 8 as in the above-described embodiment.

In addition, in general, in a photoelectric conversion element of a hetero junction type and a back junction type, although high conversion efficiency is obtained, it is difficult to draw an amorphous layer without impairing electric characteristics, and cost is also incurred. In contrast, according to the photoelectric conversion element 1 of the present embodiment, the process can be simplified, and therefore, the cost can be reduced.

In addition, the intrinsic semiconductor layer sandwiched by the n-type semiconductor layer and the p-type semiconductor layer in the overlap region receives doping from the n-type semiconductor layer and doping from the p-type semiconductor layer.

According to the photoelectric conversion element 1 of the present embodiment, the intrinsic semiconductor layer 23b sandwiched between the n-type semiconductor layer 25 and the p-type semiconductor layer 35 is thin and has a low refractive index in the overlap region R, and therefore, both the p-type and n-type dopants are easily doped, and the depletion layer increases the resistance. Therefore, the leakage between PN in the overlap region R is reduced, and the output of the photoelectric conversion element 1 is improved.

Here, the n-type semiconductor layer generally has lower alkali resistance than the electrode layer and the p-type semiconductor layer. Therefore, when the alkali component penetrates into the module after the module is formed, the performance of the photoelectric conversion element is degraded.

According to the photoelectric conversion element 1 of the present embodiment, the first electrode layer 27 corresponding to the n-type semiconductor layer 25 in the n-type region 7 extends so as to cover a part or the whole of the n-type semiconductor layer 25 in the overlap region R. Thereby, the n-type semiconductor layer 25 in the overlap region R is protected from the alkali component.

Further, as shown in fig. 5, the first electrode layer 27 may extend so as to cover the entire n-type semiconductor layer 25 in the overlap region R and a part of the p-type semiconductor layer 35 in the p-type region 8. Thus, even if there is a manufacturing error of the n-type semiconductor layer 25 in the overlap region R (for example, a detour error under the mask M as described above), the entire n-type semiconductor layer 25 in the overlap region R is covered with the first electrode layer 27. Thereby, the n-type semiconductor layer 25 in the overlap region R is further protected from the alkali component.

The embodiments of the present invention have been described above, but the present invention is not limited to the above embodiments and various changes and modifications can be made. For example, in the above-described embodiment, the photoelectric conversion element 1 is obtained by forming the part 23a of the intrinsic semiconductor layer 23 in the n-type region (first region) 7 by hydrogen plasma etching (second conductive semiconductor layer forming step) and forming the remaining part 23b of the intrinsic semiconductor layer 23 thereon (first conductive semiconductor layer forming step) (for example, the part 23a and the remaining part 23b of the intrinsic semiconductor layer 23 are made of the same material). However, the method for manufacturing the photoelectric conversion element of the present invention is not limited thereto.

For example, in the second conductivity type semiconductor layer forming step, the precursor of the second conductivity type semiconductor layer and the intrinsic semiconductor layer may be all etched in the first region, and in the first conductivity type semiconductor layer forming step, the intrinsic semiconductor layer and the first conductivity type semiconductor layer may be formed on the main surface of the semiconductor substrate in the first region. In this case, as the material of the intrinsic semiconductor layer in the first region, a material having a smaller refractive index than that of the material of the intrinsic semiconductor layer in the second region may be used. In addition, as an etching solution for the precursor of the second conductivity type semiconductor layer, an acidic solution such as hydrofluoric acid is exemplified.

Alternatively, in the second conductive type semiconductor layer laminating step and the second conductive type semiconductor layer forming step, when the intrinsic semiconductor layer and the p-type semiconductor layer are laminated in the second region on the back surface side of the semiconductor substrate 11 by the CVD method, the intrinsic semiconductor layer and the p-type semiconductor layer may be formed using a mask, and in the first conductive type semiconductor layer forming step, the intrinsic semiconductor layer and the first conductive type semiconductor layer may be formed on the main surface of the semiconductor substrate in the first region. In this case, as the material of the intrinsic semiconductor layer in the first region, a material having a smaller refractive index than that of the material of the intrinsic semiconductor layer in the second region may be used.

The respective layers are not limited to the dry method, and may be formed by a wet method. In this case, as the material of the intrinsic semiconductor layer in the first region, a material having a smaller refractive index than that of the material of the intrinsic semiconductor layer in the second region may be used.

In the above-described embodiment, the hetero-junction type photoelectric conversion element 1 is exemplified as shown in fig. 3 and 5, but the present invention is not limited to the hetero-junction type photoelectric conversion element, and can be applied to various photoelectric conversion elements such as a homo-junction type photoelectric conversion element.

In the above-described embodiment, an n-type semiconductor substrate is exemplified as the semiconductor substrate 11, but the semiconductor substrate 11 may be a p-type semiconductor substrate in which a p-type dopant (for example, boron (B) described above) is doped into a crystalline silicon material.

In the above-described embodiments, the photoelectric conversion element having the crystalline silicon substrate is exemplified, but not limited thereto. For example, the photoelectric conversion element may have a gallium arsenide (GaAs) substrate.

Description of reference numerals

1 … photoelectric conversion element; 2 … wiring parts; 3 … light receiving surface protection member; 4 … back protection components; 5 … sealing material; 7 … n-type region (first region); 8 … p-type region (second region); 7b, 8b … bus; 7f, 8f … fingers; 11 … a semiconductor substrate; 13. 23, 33 … intrinsic semiconductor layer; 23a … a portion of the intrinsic semiconductor layer; 23b … a remaining portion of the intrinsic semiconductor layer; a precursor of 33Z … intrinsic semiconductor layer; 25 … n-type semiconductor layer (first conductivity type semiconductor layer); 27 … a first electrode layer; 35 … p-type semiconductor layer (second conductive type semiconductor layer); a precursor of 35Z … p-type semiconductor layer (second conductivity type semiconductor layer); 37 … second electrode layer; 100 … photoelectric conversion module; r … overlap region.