阅读说明：本技术 可变增益放大器 (Variable gain amplifier ) 是由 山本航 堤恒次 下泽充弘 于 2018-08-10 设计创作，主要内容包括：应用了本发明的可变增益放大器具备：第一晶体管群,与输入端子及输出端子连接,将来自输入端子的信号进行放大后输出到输出端子；第二晶体管群,与输入端子连接；第三晶体管群,与输出端子连接；以及控制部,使在第一晶体管群和第二晶体管群中接通的晶体管的总数恒定,且使在第一晶体管群和第三晶体管群的各个晶体管群中接通的晶体管的总数相同,控制第一晶体管群、第二晶体管群以及第三晶体管群。(The variable gain amplifier to which the present invention is applied includes: a first transistor group connected to the input terminal and the output terminal, for amplifying a signal from the input terminal and outputting the amplified signal to the output terminal; a second transistor group connected to the input terminal; a third transistor group connected to the output terminal; and a control unit that controls the first transistor group, the second transistor group, and the third transistor group such that the total number of transistors turned on in the first transistor group and the second transistor group is constant, and the total number of transistors turned on in each of the first transistor group and the third transistor group is the same.)

1. A variable gain amplifier is provided with:

a first transistor group connected to an input terminal and an output terminal, amplifying a signal from the input terminal, and outputting the amplified signal to the output terminal;

a second transistor group connected to the input terminal;

a third transistor group connected to the output terminal; and

and a control unit configured to control the first transistor group, the second transistor group, and the third transistor group such that the total number of transistors turned on in the first transistor group and the second transistor group is constant, and the total number of transistors turned on in each of the first transistor group and the third transistor group is the same.

2. The variable gain amplifier according to claim 1, further comprising:

a first load element having one terminal connected to ground and the other terminal connected to the input terminal;

a second load element having one terminal connected to a power supply line and the other terminal connected to the output terminal; and

a third load element having one terminal connected to the ground,

the first transistor group is connected in parallel between the other terminal of the second load element and the other terminal of the first load element,

the second transistor group is connected in parallel between the other terminal of the first load element and the power supply line,

the third transistor group is connected in parallel between the other terminal of the second load element and the other terminal of the third load element.

3. The variable gain amplifier according to claim 2, further comprising:

a variable current source connected between the one terminal of the third load element and the ground; and

and a current control unit that controls the variable current source according to a current flowing through the second transistor group.

4. The variable gain amplifier according to claim 2, further comprising:

an amplifier circuit that is arranged in place of the first load element and includes a transistor having a gate connected to the input terminal; and

and a voltage applying unit for applying a voltage to the gate.

5. The variable gain amplifier according to any one of claims 1 to 4,

1 or more of the first transistor group, the second transistor group, and the third transistor group operate in units of differential pairs including 2 transistors.

6. The variable gain amplifier according to claim 1, further comprising:

a first load element having one terminal connected to ground and the other terminal connected to the input terminal; and

a second load element having one terminal connected to a power supply line and the other terminal connected to the output terminal,

the first transistor group has a plurality of differential pairs including 2 transistors, the differential pairs being connected in parallel between the other terminal of the first load element and the other terminal of the second load element,

the second transistor group and the third transistor group have a plurality of differential pairs each including 2 transistors, and the differential pairs of the second transistor group and the third transistor group are cascade-connected between the other terminal of the first load element and the other terminal of the second load element,

the control unit turns on/off the cascade-connected one differential pair of the second transistor group and one differential pair of the third transistor group in units of one differential pair.

7. The variable gain amplifier according to claim 6, further comprising:

a constant current source connected between the one terminal of the first load element and the ground.

8. The variable gain amplifier according to claim 6, further comprising:

an amplifier circuit that is arranged in place of the first load element and includes a transistor having a gate connected to the input terminal; and

and a voltage applying unit for applying a voltage to the gate.

Technical Field

The present invention relates to a variable gain amplifier capable of changing a gain.

Background

A phased array antenna used in a radar apparatus, a wireless communication device, or the like controls the amplitude and phase of a high-frequency signal using a variable gain amplifier and a phase shifter, and changes the radiation direction of a beam. As the variable gain amplifier, there is a variable gain amplifier including: a cascode amplifier including an amplifier stage transistor that amplifies an input signal and a plurality of cascode stage transistors connected in a cascode manner at an output terminal of the amplifier stage transistor; and a gate potential control circuit that controls on and off of the plurality of cascode stage transistors (see, for example, patent document 1).

The plurality of cascode stage transistors are classified into a signal transfer transistor connected to an output terminal of the variable gain amplifier and a signal short transistor connected to a power supply terminal. The output terminal is connected to the output terminal of the signal transmission transistor.

In the conventional variable gain amplifier described in patent document 1, the number of transistors is controlled so that the total of the number of transistors for signal transmission to be turned on and the number of transistors for signal short to be turned on is always constant. By this control, the amount of current flowing through the output terminal, that is, the gain of the variable gain amplifier can be changed.

Patent document 1: japanese patent laid-open publication No. 2007-259297

Disclosure of Invention

Problems to be solved by the invention

When the sum of the number of signal transfer transistors to be turned on and the number of signal short-circuit transistors to be turned on is always constant, the impedance of the entire plurality of cascode stage transistors is constant or substantially constant from the viewpoint of the amplifier stage transistor. However, from the viewpoint of the output terminal, the overall impedance changes with a change in the number of signal transmission transistors that are turned on, in other words, a change in gain. Due to this change in impedance, an error occurs in the amount of current flowing through the output terminal, and the passing phase (past phase) fluctuates.

The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a variable gain amplifier capable of further suppressing variation in a passing phase caused by gain change.

Means for solving the problems

The variable gain amplifier according to the present invention includes: a first transistor group connected to the input terminal and the output terminal, for amplifying a signal from the input terminal and outputting the amplified signal to the output terminal; a second transistor group connected to the input terminal; a third transistor group connected to the output terminal; and a control unit that controls the first transistor group, the second transistor group, and the third transistor group such that the total number of transistors turned on in the first transistor group and the second transistor group is constant, and the total number of transistors turned on in each of the second transistor group and the third transistor group is the same.

ADVANTAGEOUS EFFECTS OF INVENTION

According to the present invention, it is possible to further suppress variation in the passing phase caused by gain change.

Drawings

Fig. 1 is a block diagram showing a variable gain amplifier according to embodiment 1 of the present invention.

Fig. 2 is a block diagram showing a variable gain amplifier according to embodiment 2 of the present invention.

Fig. 3 is a block diagram showing a variable gain amplifier according to embodiment 3 of the present invention.

Fig. 4 is a block diagram showing a variable gain amplifier according to embodiment 4 of the present invention.

Fig. 5 is a block diagram showing a variable gain amplifier according to embodiment 5 of the present invention.

Fig. 6 is a diagram showing the amount of variation in the passing phase due to the gain of the variable gain amplifier according to embodiment 5 of the present invention.

Fig. 7 is a block diagram showing a variable gain amplifier according to embodiment 6 of the present invention.

Fig. 8 is a block diagram showing a variable gain amplifier according to embodiment 7 of the present invention.

(description of reference numerals)

1: a variable gain amplifier; 2: a first load element pair; 2 a: a first load element; 2P, 2N, 3P, 3N, 4P, 4N: a load element; 3 a: a second load element; 4 a: a third load element; 5D: a dummy structure group (a second transistor group and a third transistor group); 5D 1-5D 3: dummy structures (dummy); 5I: inputting a dummy structure group (a second transistor group); 5I 1-5I 3: inputting a dummy structure; 5DL1P, 5DL1N, 5DU1P, 5DU1N, 5I1P, 5I1N, 5G1P, 5G1N, 5O1P, 5O1N, 31P, 31N: a transistor; 5G: an amplifying circuit group (first transistor group); 5G 1-5G 3, 31: an amplifying circuit; 5O: outputting a dummy structure group (third transistor group); 5O 1-5O 3: outputting the dummy structure; 6: a gate potential control circuit (control unit); 21: a constant current source; 22: a variable current source; 23: a current control circuit (current control unit); 32: a gate potential applying circuit.

Detailed Description

Hereinafter, embodiments of the variable gain amplifier according to the present invention will be described with reference to the drawings. Here, the same or corresponding components are denoted by the same reference numerals.

Embodiment 1.

Fig. 1 is a block diagram showing a variable gain amplifier according to embodiment 1 of the present invention. As shown in fig. 1, the variable gain amplifier 1 according to embodiment 1 is a differential input/differential output amplifier, and includes input terminals INP and INN and output terminals OUTP and OUTN. The first load element pair 2 includes 2 load elements 2P and 2N, and one terminal of each of the load elements 2P and 2N is connected to ground. The input terminals INP and INN are connected to the other terminals of the load elements 2P and 2N, respectively.

An input dummy structure group 5I corresponding to the second transistor group is connected between the first load element pair 2 and the power supply line VDD. The input dummy structure group 5I is used for short-circuiting signals, and fig. 1 shows a state in which 3 input dummy structures 5I1 to 5I3 are connected in parallel. Here, "5 IN" is used as a symbol IN the case where a specific input dummy structure is not referred to.

As shown in fig. 1, the input dummy structure 5I1 is a differential pair in which the gates of the 2 transistors 5I1P and 5I1N are grounded. As the 2 transistors 5I1P and 5I1N constituting the differential pair, N-channel MOSFETs (Metal-Oxide-Semiconductor Field Effect transistors) are used. The 2 transistors 5I1P and 5I1N have gates connected to each other, drains connected to the power supply line VDD, and sources connected to the 2 load elements 2P and 2N, respectively. Although not shown, the input dummy structures 5I2 and 5I3 also have the same internal structure as the input dummy structure 5I 1.

The second load element pair 3 includes 2 load elements 3P and 3N, and each of the load elements 3P and 3N has one terminal connected to the power supply line VDD and the other terminal connected to the output terminals OUTP and OUTN, respectively. An amplifier circuit group 5G corresponding to the first transistor group is connected between the second load element pair 3 and the first load element pair 2. The amplifier circuit group 5G is used for signal amplification, and fig. 1 shows a state in which 3 amplifier circuits 5G1 to 5G3 are connected in parallel. Here, "5 GN" is used as a symbol unless a specific amplifier circuit is referred to.

As shown in fig. 1, the amplifier circuit 5G1 is a differential pair in which the gates of the 2 transistors 5G1P and 5G1N are grounded, similarly to the input dummy structure 5I 1. As the 2 transistors 5G1P and 5G1N constituting the differential pair, N-channel MOSFETs are used. The 2 transistors 5G1P and 5G1N have their gates connected to each other, their drains connected to the 2 load elements 3P and 3N, respectively, and their sources connected to the 2 load elements 2P and 2N, respectively. Although not shown, the amplifier circuits 5G2 and 5G3 have the same internal configuration as that of the amplifier circuit 5G 1.

The third load element pair 4 includes 2 load elements 4P and 4N, and one terminal of each of the load elements 4P and 4N is connected to ground. An output dummy structure group 5O corresponding to the third transistor group is connected between the third load element pair 4 and the second load element pair 3. The output dummy structure group 5O is a component provided to suppress a variation in impedance when viewed from the output terminals OUTP and OUTN, and fig. 1 shows a state in which 3 output dummy structures 5O1 to 5O3 are connected in parallel. Hereinafter, the impedance seen from the viewpoint of the output terminals OUTP, OUTN will be expressed as "output impedance". In the case where a specific output dummy structure is not specified, "5 ON" is used as a symbol.

As shown in fig. 1, the output dummy structure 5O1 is a differential pair in which the gates of the 2 transistors 5O1P and 5O1N are grounded, similarly to the input dummy structure 5I1 and the amplifier circuit 5G 1. N-channel MOSFETs are used as the 2 transistors 5O1P and 5O1N constituting the differential pair. The gates of the 2 transistors 5O1P and 5O1N are connected to each other, the drains are connected to the 2 load elements 3P and 3N, respectively, and the sources are connected to the 2 load elements 4P and 4N, respectively. Although not shown, the output dummy structures 5O2 and 5O3 are also internal structures similar to the output dummy structure 5O 1.

All the gates of the transistors constituting the input dummy structure group 5I, the amplification circuit group 5G, and the output dummy structure group 5O are connected to the gate potential control circuit 6. The gate potential control circuit 6 outputs a control signal to the gate of each transistor to control the operations of the input dummy structure group 5I, the amplification circuit group 5G, and the output dummy structure group 5O. That is, the gate potential control circuit 6 corresponds to the control unit in embodiment 1.

In each of the input dummy structure group 5I, the amplification circuit group 5G, and the output dummy structure group 5O, the gates of 2 transistors constituting a differential pair are connected to each other. Therefore, in the input dummy structure group 5I, the amplifier circuit group 5G, and the output dummy structure group 5O, the on/off operations of the 2 transistors are controlled in units of differential pairs.

The input dummy structure group 5I and the gate potential control circuit 6 are connected to each other through different signal lines for each input dummy structure 5 IN. The amplifier circuit group 5G and the gate potential control circuit 6 are also connected by different signal lines for each amplifier circuit 5 GN.

Each signal line connecting the input dummy structure group 5I and the gate potential control circuit 6 is connected to a signal line corresponding to the output dummy structure group 5O. For example, the signal line connected to the input dummy structure 5I1 of the input dummy structure group 5I is connected to the signal line of the output dummy structure 5O1 of the output dummy structure group 5O. The signal line connected to the input dummy structure 5I2 of the input dummy structure group 5I is connected to the signal line of the output dummy structure 5O2 of the output dummy structure group 5O, and the signal line connected to the input dummy structure 5I3 of the input dummy structure group 5I is connected to the signal line of the output dummy structure 5O3 of the output dummy structure group 5O. As a result of such a connection structure, the number of input dummy structures 5IN that operate IN the input dummy structure group 5I matches the number of output dummy structures 5ON that operate IN the output dummy structure group 5O.

The gate potential control circuit 6 maintains the sum of the number of input dummy structures 5IN operating IN the input dummy structure group 5I and the number of amplification circuits 5GN operating IN the amplification circuit group 5G constant, and changes the combination of these numbers IN accordance with the gain to be set. Thus, for example, when the total value is assumed to be 3, IN a situation where one input dummy structure 5IN is operated IN the input dummy structure group 5I, 2 amplifier circuits 5GN are operated IN 3 amplifier circuits 5G1 to 5G3 of the amplifier circuit group 5G. In the output dummy structure group 5O, one output dummy structure 5ON operates. IN a case where 2 input dummy structures 5IN are operated IN the input dummy structure group 5I, one amplification circuit 5GN operates IN the amplification circuit group 5G. In the output dummy structure group 5O, 2 output dummy structures 5ON operate.

By such an operation, the sum of the number of amplification circuits 5GN operating in the amplification circuit group 5G and the number of output dummy structures 5ON operating in the output dummy structure group 5O is also maintained constant regardless of the contents of the gain setting. The amplifier circuit group 5G and the output dummy structure group 5O are both connected to the output terminals OUTP and OUTN. Therefore, by appropriately selecting the impedances of the amplifier circuits 5G1 to 5G3 and the output dummy structures 5O1 to 5O3, the output impedance can be maintained constant or the variation of the output impedance can be suppressed within an extremely narrow range regardless of the content of the gain setting. Thus, the variation of the passing phase caused by the gain change is avoided or suppressed within an extremely narrow range, and more preferable characteristics are realized as the variable gain amplifier 1. The simplest impedance is selected such that the impedances of all the amplification circuits 5GN and all the output dummy structures 5ON are the same.

IN embodiment 1, the number of input dummy structures 5IN, the number of amplifier circuits 5GN, and the number of output dummy structures 5ON are all set to 3, but the number is not limited to 3. The resolution in the gain setting can be increased as the number is increased, and therefore the number may be determined according to the required resolution or the like. However, the number of input dummy structures 5IN needs to be made equal to the number of output dummy structures 5 ON.

IN embodiment 1, the signal line of the output dummy structure 5ON is connected to the signal line of the input dummy structure 5IN order to simplify control and the like, but each output dummy structure 5ON may be connected to the gate potential control circuit 6 through a signal line. The input dummy structure group 5I and the amplifier circuit group 5G may be connected to different pairs of load elements. The gate potential control circuit 6 may be an analog circuit, but may be a control device including a microcomputer or the like.

Embodiment 2.

Fig. 2 is a block diagram showing a variable gain amplifier according to embodiment 2 of the present invention. Differences from embodiment 1 described above will be described in detail with reference to fig. 2.

In embodiment 2, as shown in fig. 2, one terminal of each of the 2 load elements 2P and 2N constituting the first load element pair 2 is connected to ground via a constant current source 21. One terminal of each of the 2 load elements 4P and 4N constituting the third load element pair 4 is connected to ground via a variable current source 22. The current control circuit 23 is connected to the variable current source 22 in order to control the current value of the variable current source 22.

As described above, the total sum of the number of input dummy structures 5IN operating IN the input dummy structure group 5I and the number of amplification circuits 5GN operating IN the amplification circuit group 5G, IN other words, the total impedance is maintained constant. Therefore, the constant current source 21 is used to supply a current corresponding to the sum. However, the current flowing through the output dummy structure group 5O varies depending ON the number or the output dummy structures 5ON that operate. The number of output dummy structures 5ON or the number thereof to be operated varies depending ON the control content for the input dummy structure group 5I.

Therefore, the current control circuit 23 controls the variable current source 22 so that the value of the supplied current matches the value of the current flowing through the input dummy structure group 5I. IN order to perform this control, the current control circuit 23 receives an analog signal or a digital signal representing a combination of analog signals or digital signals, which change IN accordance with the combination of the input dummy structures 5IN to be operated, from the gate potential control circuit 6. The current control circuit 23 uses the input signal to cause the variable current source 22 to supply the current to be supplied.

Thus, in embodiment 2, appropriate amounts of current are supplied to the input dummy structure group 5I, the amplification circuit group 5G, and the output dummy structure group 5O using the constant current source 21 and the variable current source 22, respectively. Therefore, the gain control can be performed with higher accuracy than in embodiment 1. Also in embodiment 2, the same effect as that of embodiment 1 can be obtained, and variation in the passing phase caused by gain change can be avoided or suppressed within an extremely narrow range.

Embodiment 3.

Fig. 3 is a block diagram showing a variable gain amplifier according to embodiment 3 of the present invention. The difference from embodiment 2 described above will be described in detail with reference to fig. 3.

In embodiment 3, the first load element pair 2 is replaced with an amplifier circuit 31 as shown in fig. 3. The amplifier circuit 31 is a differential pair having 2 transistors 31P and 31N with their sources grounded, respectively. The 2 transistors 31P, 31N are both N-channel MOSFETs. The sources of one of the 2 transistors constituting the input dummy structure 5IN and one of the 2 transistors constituting the amplification circuit 5GN are connected to the drain of the transistor 31P. The sources of the other of the 2 transistors constituting the input dummy structure 5IN and the other of the 2 transistors constituting the amplification circuit 5GN are connected to the drain of the transistor 31N.

The input terminal INP is connected to the gate of the transistor 31P, and the input terminal INN is connected to the gate of the transistor 31N. The gates of the transistors 31P and 31N are also connected to a gate potential applying circuit 32. The gate potential applying circuit 32 is, for example, a circuit for generating a constant voltage.

As described above, the same effects as those of embodiment 1 can be obtained also in embodiment 3 in which the first load element pair 2 is replaced with the amplifier circuit 31.

Embodiment 4.

Fig. 4 is a configuration diagram showing a variable gain amplifier circuit according to embodiment 4 of the present invention. Differences from embodiment 1 described above will be described in detail with reference to fig. 4.

IN embodiment 1 described above, all of the input dummy structures 5IN, the amplifying circuits 5GN, and the output dummy structures 5ON are differential pairs. IN contrast, IN embodiment 4, as shown IN fig. 4, each input dummy structure 5IN, each amplification circuit 5GN, and each output dummy structure 5ON are all one transistor. Therefore, the first load element pair 2 is replaced with a first load element 2 a. Similarly, the second load element pair 3 is replaced with a second load element 3a, and the third load element pair 4 is replaced with a third load element 4 a. The input terminal IN is connected to the other terminal of the first load element 2a, that is, the sources of the input dummy structures 5I 1-5I 3 and the sources of the amplifying circuits 5G 1-5G 3. The output terminal OUT is connected to the power supply line VDD via the second load element 3 a. With this configuration, it is possible to obtain the same effect as that of embodiment 1 described above, and to avoid or suppress the variation in the passing phase caused by the gain change within an extremely narrow range.

In embodiment 4, all of the input dummy structure group 5I, the amplifier circuit group 5G, and the output dummy structure group 5O are operated for each transistor, but this need not be the case. That is, 1 or 2 of the input dummy structure group 5I, the amplifier circuit group 5G, and the output dummy structure group 5O may be configured by a differential pair in the same manner as in embodiments 1 to 3.

Embodiment 5.

Fig. 5 is a block diagram showing a variable gain amplifier according to embodiment 5 of the present invention. Differences from embodiment 1 described above will be described in detail with reference to fig. 5.

In embodiment 1, the output dummy structure group 5O is added to avoid or suppress the fluctuation of the output impedance caused by the gain change. However, the amount of power consumption increases with the addition of the output dummy structure group 5O. Therefore, embodiment 5 can further suppress the amount of power consumption as compared with embodiment 1.

In embodiment 5, as shown in fig. 5, in order to suppress the power consumption, the output dummy structure group 5O is not present. In embodiment 5, the input dummy structure group 5I is replaced with the dummy structure group 5D, and the output dummy structure group 5O is provided instead. The dummy structure group 5D corresponds to the second transistor group and the third transistor group in embodiment 5.

The dummy structure group 5D is a component having both the functions of the input dummy structure group 5I and the output dummy structure group 5O in embodiment 1. Therefore, as shown in fig. 5, the dummy structure group 5D is connected between the second load element pair 3 and the first load element pair 2. Fig. 5 shows 3 dummy structures 5D 1-5D 3 constituting the dummy structure group 5D. Here, "5 DN" is used as a symbol without referring to a specific dummy structure. The number of dummy structures 5DN constituting the dummy structure group 5D is not limited to 3.

Each dummy structure 5DN is a structure including 4 transistors in total by connecting two stages of differential pairs in cascade as shown in fig. 5. Specifically, in the dummy structure 5D1, the upper differential pair, which is the differential pair located on the second load element pair 3 side, is constituted by 2 transistors 5DU1P and 5DU1N, which are N-channel MOSFETs. The lower differential pairs as the remaining differential pairs are also each composed of 2 transistors 5DL1P, 5DL1N as N-channel MOSFETs.

The lower differential pair corresponds to a differential pair constituting the second transistor group in embodiment 5, and the upper differential pair corresponds to a differential pair constituting the third transistor group in embodiment 5. Thus, in embodiment 5, 2 drains of one differential pair constituting the second transistor group and 2 sources of one differential pair constituting the third transistor group are all connected to cascade the 2 differential pairs, thereby forming one dummy structure 5 DN.

As shown in fig. 5, the 2 transistors 5DU1P and 5DU1N constituting the upper differential pair have their gates connected to each other, their sources connected to each other, and their drains connected to the load elements 3P and 3N, respectively. As shown in fig. 5, the 2 transistors 5DL1P and 5DL1N constituting the lower differential pair have their gates connected to each other, their drains connected to each other, and their sources connected to the load elements 2P and 2N, respectively. The sources of the 2 transistors 5DU1P, 5DU1N are connected to the drains of the 2 transistors 5DL1P, 5DL 1N. That is, the total of 4 input terminals of the 25 DU1P and 5DU1N constituting the upper differential pair and the output terminals of the 25 DL1P and 5DL1N constituting the lower differential pair are all connected.

The gates of the 2 transistors 5DU1P and 5DU1N are connected to the gates of the 2 transistors 5DL1P and 5DL1N, and signal lines for the connection are connected to the gate potential control circuit 6. Thus, the same control signal is input to the gates of the 4 transistors constituting each dummy structure 5DN, and control is performed in units of the dummy structures 5 DN.

The gate potential control circuit 6 maintains the sum of the number of dummy structures 5DN operating in the dummy structure group 5D and the number of amplification circuits 5GN operating in the amplification circuit group 5G constant, and changes the combination of these numbers in accordance with the gain to be set. Thus, for example, when the total value is assumed to be 3, in a case where one dummy structure 5DN is operated in the dummy structure group 5D, 2 amplifier circuits 5GN are operated in the amplifier circuit group 5G. In the case where 2 dummy structures 5DN are operated in the dummy structure group 5D, one amplification circuit 5GN is operated in the amplification circuit group 5G.

As described above, each of the dummy structures 5DN constituting the dummy structure group 5D is a structure in which one differential pair constituting the second transistor group and the third transistor group, respectively, is connected in cascade. Therefore, when the total of the number of dummy structures 5DN operating in the dummy structure group 5D and the number of amplification circuits 5GN operating in the amplification circuit group 5G is maintained constant, the total number of transistors turned on in each of the second transistor group and the third transistor group is the same. In addition, the total number of transistors turned on in the first transistor group and the second transistor group is always constant.

For example, when the dummy structure 5D1 is operated, the gate potential control circuit 6 outputs a control signal for turning on the transistors 5DU1P, 5DU1N, 5DL1P, and 5DL 1N. The 2 drains of the lower differential pair are all connected with the upper differential pair. When the dummy structure 5D1 is turned on by this control signal, the 2 drains of the lower differential pair are connected to each other, and therefore signals having opposite phases are synthesized. As a result, the upper differential pair does not actually receive a signal from the lower differential pair, and therefore, even when turned on, no signal is output from the upper differential pair output terminals OUTP and OUTN. However, the impedance of the upper differential pair is reflected in the output impedance which is the impedance of the variable gain amplifier 1 when viewed from the output terminals OUTP and OUTN. The same applies to the dummy structure 5DN other than the dummy structure 5D 1.

Accordingly, also in embodiment 5, the sum of the number of dummy structures 5DN to be turned on and the number of amplifier circuits 5GN to be turned on is kept constant, and the combination of these numbers is changed in accordance with the gain to be set. Therefore, even when the gain is changed, the output impedance can be maintained constant or the variation of the output impedance can be suppressed within an extremely narrow range. Thus, the same effects as those of embodiment 1 can be obtained also in embodiment 5. Further, since the current path as in the output dummy structure group 5O is not newly formed, the amount of power consumption can be further reduced as compared with embodiment 1.

Fig. 6 is a diagram showing the amount of variation in the passing phase due to the gain of the variable gain amplifier according to embodiment 5 of the present invention. The amount of variation in the passing phase due to the gain is obtained by simulation. In fig. 6, the horizontal axis represents the gain setting value, and the vertical axis represents the phase variation amount. The unit of the phase variation amount is an angle. The solid line shows the result of embodiment 5, and the broken line shows the result of a conventional circuit, that is, a conventional variable gain amplifier. This conventional circuit is a circuit in which the output dummy structure group 5O and the third load element pair 4 are removed from the structure shown in fig. 1.

In this conventional circuit, the output impedance varies according to the gain setting value. Due to this variation in output impedance, as shown in fig. 6, the absolute value of the amount of variation in the passing phase increases as the gain setting value increases. In contrast, in embodiment 5, the output impedance is constant or substantially constant even if the gain setting value is different. Therefore, as shown in fig. 6, the passing phase hardly changes even if the gain setting value is changed. From the results, it can be confirmed that suppressing the change in the output impedance due to the gain setting value is effective for further improving the characteristics of the variable gain amplifier 1. The characteristics shown in fig. 6 or characteristics similar thereto can be obtained by embodiments 1 to 4.

Embodiment 6.

Fig. 7 is a block diagram showing a variable gain amplifier according to embodiment 6 of the present invention. The difference from embodiment 5 described above will be described in detail with reference to fig. 7.

In embodiment 6, as shown in fig. 7, the constant current source 21 is disposed between the first load element pair 2 and the ground, and the dummy structure group 5D and the amplification circuit group 5G are connected to the ground through the first load element pair 2 and the constant current source 21. Even if the constant current source 21 is added in this way, the output impedance can be maintained constant or the variation of the output impedance can be suppressed within an extremely narrow range, and therefore, the same characteristics as those of embodiment 5 can be achieved. The constant current source 21 is effective in high-precision gain.

Embodiment 7.

Fig. 8 is a block diagram showing a variable gain amplifier according to embodiment 7 of the present invention. The difference from embodiment 5 described above will be described in detail with reference to fig. 8.

In embodiment 7, as shown in fig. 8, the first load element pair 2 in fig. 5 is replaced with an amplifier circuit 31, and a gate potential applying circuit 32 is added. The amplifier circuit 31 is a differential pair having 2 transistors 31P and 31N with their sources grounded, as in embodiment 3. The source of each of the 2 transistors constituting the dummy structure 5DN and the 2 transistors constituting the amplification circuit 5GN is connected to the drain of the transistor 31P. The source of the other of the 2 transistors constituting the dummy structure 5DN and the source of the other of the 2 transistors constituting the amplification circuit 5GN are connected to the drain of the transistor 31N.

The input terminal INP is connected to the gate of the transistor 31P, and the input terminal INN is connected to the gate of the transistor 31N. The gates of the transistors 31P and 31N are also connected to a gate potential applying circuit 32.

As described above, also in embodiment 7 in which the first load element pair 2 is replaced with the amplifier circuit 31, the output impedance can be maintained constant or the variation in the output impedance can be suppressed within an extremely narrow range, and therefore, the same effect as that of embodiment 5 can be obtained.