阅读说明：本技术 显示基板及其制作方法、显示面板和显示装置 (Display substrate, manufacturing method thereof, display panel and display device ) 是由 魏玉龙 张震 于 2019-12-20 设计创作，主要内容包括：一种显示基板及其制作方法、显示面板和显示装置。所述显示基板包括衬底基板,以及依次位于所述衬底基板上的遮光层(S1)和薄膜晶体管阵列层；遮光层(S1)包括多个成像小孔(H1)；遮光层(S1)与薄膜晶体管阵列层之间设置有第一保护层(P0)；衬底基板上设有第一区域,薄膜晶体管阵列层包括的金属膜层在衬底基板上的正投影设置于所述第一区域之外；成像小孔(H1)在衬底基板上的正投影的至少一部分设置于所述第一区域内；第一保护层(P0)在衬底基板上的正投影至少覆盖第一区域的一部分；第一区域包括小孔区域(A0)；第一保护层(P0)在衬底基板上的正投影至少覆盖小孔区域(A0)；所述显示基板还包括缓冲层(Bf)。所述的显示基板及其制作方法、显示面板和显示装置能提升指纹识别效果。(A display substrate, a manufacturing method thereof, a display panel and a display device are provided. The display substrate comprises a substrate, and a light shielding layer (S1) and a thin film transistor array layer which are sequentially arranged on the substrate; the light-shielding layer (S1) includes a plurality of imaging apertures (H1); a first protective layer (P0) is arranged between the shading layer (S1) and the thin film transistor array layer; the substrate base plate is provided with a first area, and the orthographic projection of a metal film layer included by the thin film transistor array layer on the substrate base plate is arranged outside the first area; at least a portion of an orthographic projection of the imaging aperture (H1) on the substrate base is disposed within the first region; an orthographic projection of the first protective layer (P0) on the base substrate covers at least a part of the first area; the first region comprises an aperture region (a 0); an orthographic projection of the first protective layer (P0) on the substrate base plate at least covers the small hole area (A0); the display substrate further includes a buffer layer (Bf). The display substrate, the manufacturing method of the display substrate, the display panel and the display device can improve the fingerprint identification effect.)

A display substrate comprises a substrate, a light shielding layer and a thin film transistor array layer, wherein the light shielding layer and the thin film transistor array layer are sequentially arranged on the substrate; the light shield layer includes a plurality of imaging apertures;

a first protective layer is arranged between the shading layer and the thin film transistor array layer;

the substrate base plate is provided with a first area, and the orthographic projection of a metal film layer included by the thin film transistor array layer on the substrate base plate is arranged outside the first area; at least a portion of an orthographic projection of the imaging aperture on the substrate base is disposed within the first region;

an orthographic projection of the first protective layer on the substrate at least covers a part of the first area;

the first region comprises an aperture region within which at least a portion of an orthographic projection of the imaging aperture on the substrate base plate is disposed;

the orthographic projection of the first protective layer on the substrate at least covers the small hole area;

the display substrate further comprises a buffer layer arranged between the first protective layer and the thin film transistor array layer.

The display substrate of claim 1, wherein the first region comprises a first sub-region;

the thin film transistor array layer comprises a reset power line, a first reset transistor, a threshold compensation transistor and a driving transistor;

the orthographic projection of a first conductive part included by the semiconductor material layer pattern of the first reset transistor on the substrate does not overlap with the orthographic projection of a second conductive part included by the semiconductor material layer pattern of the threshold compensation transistor on the substrate;

the first conductive portion is electrically connected to a first electrode included in the first reset transistor; the first electrode is electrically connected with the reset power line;

the second conductive part is electrically connected to a second electrode included in the threshold compensation transistor; the second electrode is electrically connected to a gate of the driving transistor.

The display substrate of claim 1, wherein the first region comprises a second sub-region;

the thin film transistor array layer comprises a grid line, a threshold compensation transistor and a driving transistor;

the second sub-region is not overlapped with the orthographic projection of the grid line on the substrate, the orthographic projection of a second electrode included in the threshold compensation transistor on the substrate, the orthographic projection of a second conductive part included in the semiconductor material layer pattern of the threshold compensation transistor on the substrate and the orthographic projection of the first grid metal pattern on the substrate;

the second conductive part is electrically connected to a second electrode included in the threshold compensation transistor; the second electrode is electrically connected with the grid electrode of the driving transistor;

the first gate metal pattern is a gate metal pattern between the gate line and the gate electrode of the threshold compensation transistor included in the first gate metal layer in the thin film transistor array layer.

The display substrate of claim 1, wherein the first region comprises a third sub-region;

the thin film transistor array layer comprises a grid line, a threshold compensation transistor and a driving transistor;

the orthographic projection of the third sub-area and the grid line on the substrate base plate, the orthographic projection of a third conductive part included by the semiconductor material layer pattern of the threshold compensation transistor on the substrate base plate and the orthographic projection of the first grid metal pattern on the substrate base plate are between;

the semiconductor material layer pattern of the threshold compensation transistor comprises a first channel portion and a second channel portion, and the third conductive portion is arranged on the first channel portion and the second channel portion in a non-overlapping mode;

the first gate metal pattern is a gate metal pattern between the gate line and the gate electrode of the threshold compensation transistor included in the first gate metal layer in the thin film transistor array layer.

The display substrate of claim 1, wherein the first region comprises a fourth sub-region;

the thin film transistor array layer comprises a grid line, a first capacitor, a threshold compensation transistor and a first light-emitting control transistor;

the fourth sub-region is not overlapped with the orthographic projection of the grid line on the substrate, the orthographic projection of the first polar plate of the first capacitor on the substrate, the orthographic projection of the second electrode included in the threshold compensation transistor on the substrate and the orthographic projection of the fourth conductive part included in the semiconductor material layer pattern of the first light-emitting control transistor on the substrate;

the semiconductor material layer pattern of the threshold compensation transistor comprises a first channel part and a second channel part, and the semiconductor material layer pattern of the first light-emitting control transistor comprises a third channel part;

the fourth conductive portion is disposed between the second channel portion and the third channel portion.

The display substrate of claim 1, wherein the first region comprises a fifth sub-region;

the thin film transistor array layer comprises a first capacitor, a threshold compensation transistor, a first light-emitting control transistor, a first power line and a light-emitting control signal line;

the orthographic projection of the fifth sub-area and the first plate of the first capacitor on the substrate, the orthographic projection of the light-emitting control signal line on the substrate, the orthographic projection of the first power line on the substrate and the orthographic projection of a fourth conductive part included by the semiconductor material layer pattern of the first light-emitting control transistor on the substrate do not overlap;

the semiconductor material layer pattern of the threshold compensation transistor comprises a first channel part and a second channel part, and the semiconductor material layer pattern of the first light-emitting control transistor comprises a third channel part;

the fourth conductive portion is disposed between the second channel portion and the third channel portion.

The display substrate of claim 1, further comprising an anode layer disposed on a side of the thin film transistor array layer away from the first protective layer;

the thin film transistor array layer comprises a first power line and a first light emitting control transistor;

the pinhole region does not overlap with an orthographic projection of the first power line on the substrate and an orthographic projection of a third electrode included in the first light emission control transistor on the substrate;

the third electrode is electrically connected to the anode layer.

The display substrate according to claim 1, wherein a film formation temperature of the first protective layer is less than a threshold temperature;

the threshold temperature is equal to or higher than 230 degrees celsius and equal to or lower than 380 degrees celsius.

The display substrate of claim 1, wherein the first protective layer is made of an inorganic material or an organic material.

The display substrate of claim 9, wherein the first protective layer is made of silicon oxide or silicon nitride.

The display substrate of claim 1, wherein the first protective layer has a thickness greater than or equal to 100 nanometers and less than or equal to 400 nanometers.

The display substrate of claim 1, further comprising a fingerprint identification layer; the fingerprint identification layer is arranged on one side, far away from the light shielding layer, of the substrate base plate and comprises a fingerprint identification sensor;

the light shield layer is arranged on the light incidence side of the fingerprint identification sensor, and the imaging small hole allows light to enter the fingerprint identification sensor through the imaging small hole.

The display substrate of claim 1, wherein the light-shielding layer is made of an opaque material.

The display substrate of claim 1, further comprising a planarization layer and an anode layer sequentially disposed on a side of the thin film transistor array layer away from the buffer layer;

the orthographic projection of the imaging aperture on the substrate base plate is not overlapped with the orthographic projection of the anode layer on the substrate base plate.

The display substrate of any one of claims 1 to 14, wherein the buffer layer is made of silicon nitride, silicon oxide, or polysilicon.

The display substrate of any of claims 1-14, wherein the buffer layer has a thickness greater than or equal to 200 nanometers and less than or equal to 600 nanometers.

The display substrate of claim 1, wherein the metal film layer comprises a first metal layer, a second metal layer, and a third metal layer;

the grid line, the reset control signal line, the light-emitting control signal line, the second polar plate of the first storage capacitor and the grid of each transistor included in the pixel circuit are positioned in the first metal layer;

a reset power line and a first plate of the first storage capacitor are positioned in the second metal layer;

a first power line, a data line, and a first electrode and a second electrode included in the transistor are located in the third metal layer.

A manufacturing method of a display substrate comprises the following steps:

forming a light-shielding layer on a base substrate; the substrate base plate is provided with a first area, the shading layer comprises a plurality of imaging small holes, and at least one part of orthographic projections of the imaging small holes on the substrate base plate is arranged in the first area;

forming a first protective layer on one side of the shading layer far away from the substrate;

forming a thin film transistor array layer on the first protective layer, so that an orthographic projection of a metal film layer included in the thin film transistor array layer on the substrate is arranged outside the first area;

an orthographic projection of the first protective layer on the substrate at least covers a part of the first area;

the first region comprises an aperture region within which at least a portion of an orthographic projection of the imaging aperture on the substrate base plate is disposed; the orthographic projection of the first protective layer on the substrate at least covers the small hole area.

The method for manufacturing a display substrate according to claim 18, wherein the step of forming a first protective layer on the side of the light-shielding layer away from the base substrate comprises:

forming a first protective layer on one side of the light shielding layer far away from the substrate by adopting a low-temperature process; the film forming temperature of the first protective layer is less than a threshold temperature;

the threshold temperature is equal to or higher than 230 degrees celsius and equal to or lower than 380 degrees celsius.

A display panel comprising the display substrate of any one of claims 1 to 17.

A display device comprising the display panel according to claim 20.