阅读说明：本技术 封装结构及其制备方法 (Packaging structure and preparation method thereof ) 是由 陈富扬 简俊贤 吴政惠 林纬迪 于 2019-08-23 设计创作，主要内容包括：本发明公开了一种封装结构的制备方法,该方法包含：提供附加电路板,包含支持层、第一剥离层以及第一金属层；在第一金属层上形成第一介电层,该第一介电层具有多个孔洞,各孔洞具有端部且实质上在同一平面上彼此齐平；形成多个导电凸块且填满各孔洞,各导电凸块具有相对的第一端及第二端；形成线路层结构,包含至少一个线路层及至少一个第二介电层,线路层连接于第二端上,第二介电层位于线路层上；移除附加电路板；以及移除部分第一介电层以暴露出这些导电凸块。另公开了一种以前述制备方法所获得的封装结构,以获得高度共平面性的导电凸块。(The invention discloses a preparation method of a packaging structure, which comprises the following steps: providing an additional circuit board comprising a support layer, a first peeling layer and a first metal layer; forming a first dielectric layer on the first metal layer, the first dielectric layer having a plurality of holes, each hole having an end and being substantially flush with each other on the same plane; forming a plurality of conductive bumps and filling the holes, wherein each conductive bump is provided with a first end and a second end which are opposite; forming a circuit layer structure comprising at least one circuit layer and at least one second dielectric layer, wherein the circuit layer is connected to the second end, and the second dielectric layer is positioned on the circuit layer; removing the additional circuit board; and removing part of the first dielectric layer to expose the conductive bumps. Also disclosed is a package structure obtained by the above preparation method to obtain a highly coplanar conductive bump.)

1. A method for manufacturing a package structure, comprising:

providing an additional circuit board, wherein the additional circuit board comprises a supporting layer, a first metal layer and a first stripping layer arranged between the supporting layer and the first metal layer;

forming a first dielectric layer on the first metal layer, the first dielectric layer having a plurality of holes, wherein each of the holes has an end portion adjacent to the first metal layer, and each of the end portions are substantially flush with each other in the same plane;

forming a plurality of conductive bumps, wherein each hole is filled with each conductive bump, each conductive bump is provided with a first end and a second end opposite to the first end, and each first end corresponds to each end part;

forming a circuit layer structure on the first dielectric layer and each of the conductive bumps, wherein the circuit layer structure comprises at least one circuit layer and at least one second dielectric layer, the circuit layer is connected to the second end of each of the conductive bumps, and the second dielectric layer is located on the circuit layer;

separating the first dielectric layer from the additional circuit board; and

removing part of the first dielectric layer to expose each conductive bump.

2. The method of claim 1, wherein the additional circuit board further comprises a second metal layer and a second peeling layer disposed between the supporting layer and the second metal layer, the first peeling layer and the second peeling layer being disposed on two opposite surfaces of the supporting layer,

in the step of forming the first dielectric layer, the first dielectric layer is formed on the first metal layer and the second metal layer, respectively.

3. The method of claim 1, wherein the at least one circuit layer is a plurality of circuit layers, and the at least one second dielectric layer is a plurality of second dielectric layers.

4. The method of claim 1, wherein the holes are formed in a laser-controlled shape, and the conductive bumps are correspondingly formed in the shape.

5. The method of claim 1, wherein each conductive bump is conical, and an end of each hole is not connected to the first metal layer.

6. A package structure, comprising:

a first dielectric layer having an upper surface and a lower surface opposite to each other;

a plurality of conductive bumps having opposite first and second ends, each of the conductive bumps extending upwardly through the first dielectric layer, wherein each of the first ends is located on top of each of the conductive bumps, and each of the first ends are substantially flush with each other in a same plane, wherein each of the second ends is flush with the lower surface of the first dielectric layer; and

a circuit layer structure disposed under the first dielectric layer, the circuit layer structure comprising:

a first circuit layer disposed under the lower surface of the first dielectric layer, wherein the second ends of the conductive bumps are electrically connected to the first circuit layer;

the second dielectric layer covers the first circuit layer and the first dielectric layer and is provided with a plurality of first openings exposing the first circuit layer;

a plurality of first conductive holes disposed in the first openings of the second dielectric layer, each of the first conductive holes being electrically connected to the first circuit layer; and

and the second circuit layer is arranged below the second dielectric layer and is electrically connected with each first conductive hole.

7. The package structure of claim 6, further comprising a third dielectric layer covering the second circuit layer and the second dielectric layer and having at least one second opening exposing the second circuit layer.

8. The package structure of claim 6, wherein the conductive bump is a cone, a cylinder, a trapezoidal pillar, or a cuboid.

9. The package structure of claim 6, further comprising another package structure, wherein the first ends of the conductive bumps of each package structure abut each other.

10. The package structure of claim 6, further comprising a chip having a plurality of conductive contacts, wherein the first end of each conductive bump is in contact with each conductive contact.

Technical Field

The invention relates to the technical field of printed circuit boards, in particular to a packaging structure and a preparation method thereof.

Background

When a package substrate, a circuit board or a carrier is to be bonded to a chip, if a metal-metal direct-bonding (without using solder) method is used, conductive bumps on the package substrate, the circuit board or the carrier are required to be bonded to conductive bumps on the chip. In addition, when the package substrate, the circuit board or the carrier board is directly connected to the chip through metal-metal interconnection, high yield can be achieved only by high coplanarity.

The conventional conductive bump process is to expose and develop the photoresist to form a hole with a high aspect ratio and then to fill copper by electroplating to form the conductive bump. However, the uniformity of the height between the conductive bumps formed by this method is not good, and the conductive bumps are usually made to have higher coplanarity by chemical or physical polishing, but the coplanarity of the conductive bumps by chemical or physical polishing still does not meet the industry requirement, which causes the problems of low manufacturing cost and difficult control in specification.

Disclosure of Invention

In view of the above, an objective of an embodiment of the invention is to provide a package structure and a method for manufacturing the same, so as to solve the problems of poor uniformity of height of conductive bumps of a package substrate, a circuit board or a carrier, which results in high manufacturing cost and difficulty in controlling specification.

In order to achieve the above object, one embodiment of the present invention provides a method for manufacturing a package structure, including: providing an additional circuit board, wherein the additional circuit board comprises a supporting layer, a first metal layer and a first stripping layer arranged between the supporting layer and the first metal layer; forming a first dielectric layer on the first metal layer, the first dielectric layer having a plurality of holes, wherein each hole has an end adjacent to the first metal layer, each end being substantially flush with each other on the same plane; forming a plurality of conductive bumps, each conductive bump filling each hole, each conductive bump having a first end and a second end opposite to the first end, wherein each first end corresponds to each end; forming a circuit layer structure on the first dielectric layer and the conductive bumps, wherein the circuit layer structure comprises at least one circuit layer and at least one second dielectric layer, the circuit layer is connected to the second end of each conductive bump, and the second dielectric layer is positioned on the circuit layer; separating the first dielectric layer from the additional circuit board; and removing part of the first dielectric layer to expose the conductive bumps.

In some embodiments, the additional circuit board further includes a second metal layer and a second peeling layer disposed between the support layer and the second metal layer, the first peeling layer and the second peeling layer being disposed on two opposite surfaces of the support layer, respectively, wherein the step of forming the first dielectric layer forms the first dielectric layer on the first metal layer and the second metal layer, respectively.

In some embodiments, the at least one line layer is a plurality of line layers and the at least one second dielectric layer is a plurality of second dielectric layers.

In some embodiments, each hole is shaped by laser control, and the shape of each conductive bump is correspondingly formed.

In some embodiments, each conductive bump is in the shape of a cone or pyramid, and the end of each hole is not connected to the first metal layer.

Another embodiment of the present invention provides a package structure, which includes a first dielectric layer, a plurality of conductive bumps, and a circuit layer structure. The first dielectric layer has an upper surface and a lower surface opposite to each other. The conductive bumps have opposite first ends and second ends, each conductive bump extends upwards to penetrate through the first dielectric layer, wherein each first end is positioned at the top of each conductive bump, the first ends are substantially flush with each other on the same plane, and the second ends are flush with the lower surface of the first dielectric layer. The circuit layer structure is arranged under the first dielectric layer and comprises a first circuit layer, a second dielectric layer, a plurality of first conductive holes and a second circuit layer. The first circuit layer is disposed under the lower surface of the first dielectric layer, and the second ends of the conductive bumps are electrically connected to the first circuit layer. The second dielectric layer covers the first circuit layer and the first dielectric layer and has a plurality of first openings exposing the first circuit layer. The first conductive holes are configured in the first openings of the second dielectric layer and are electrically connected with the first circuit layer. The second circuit layer is arranged under the second dielectric layer and is electrically connected with the first conductive holes.

In some embodiments, the package structure further includes a third dielectric layer covering the second circuit layer and the second dielectric layer and having at least one second opening exposing the second circuit layer.

In some embodiments, the conductive bump is a cone, a cylinder, a trapezoidal pillar, or a cuboid.

In some embodiments, the package structure further comprises another package structure, and the first ends of the conductive bumps of the package structures are butted against each other.

In some embodiments, the package structure further includes a chip having a plurality of conductive contacts, and the first end of each conductive bump is abutted with each conductive contact.

In summary, the present invention has the following advantages:

the method of manufacturing an Embedded Trace Substrate (ETS) is used to form a highly coplanar conductive bump by matching holes with controllable depth, instead of the conventional method of polishing a copper pillar by chemical polishing or physical polishing. Specifically, after controlling the holes with the same depth of the dielectric layer by laser, the conductive bumps and the circuit layer with high coplanarity are formed, and finally, part of the dielectric layer is removed to expose the conductive bumps. Therefore, the packaging structure and the chip, the circuit board or the packaging structure are directly butted by metal-metal by using the conductive bumps with high coplanarity, so that the yield is higher.

Drawings

In order to make the aforementioned and other objects, features, and advantages of the invention, as well as others which will become apparent, reference is made to the following description taken in conjunction with the accompanying drawings in which:

fig. 1 is a flow chart illustrating a method for manufacturing a package structure according to an embodiment of the invention;

FIGS. 2-11 are schematic cross-sectional views of various stages in a fabrication method according to various embodiments of the present invention;

FIGS. 12-15 are schematic cross-sectional views illustrating package structures according to other embodiments of the invention;

FIG. 16 is a cross-sectional view of two package structures directly butted together, metal to metal, in accordance with some embodiments of the present invention;

fig. 17 is a cross-sectional view of a package structure directly interfacing with a metal-to-metal chip according to some embodiments of the invention.

[ description of main element symbols ]

10 method

S11-S16 steps

100. 200, 300, 400, 500 packaging structure

110 additional circuit board

111 support layer

112 first peeling layer

113 second peeling layer

114 first metal layer

115 second metal layer

120 first dielectric layer

120a upper surface

120b lower surface

121 hole

122 end of the tube

130 conductive bump

131 first end

132 second end

140 circuit layer structure

141 wiring layer

142 second dielectric layer

143 conductive via

144 opening

145 first circuit layer

146 second dielectric layer

147 second circuit layer

148 third dielectric layer

149 first conductive via

150 second opening

900 chip

910 conductive contact

Detailed Description

While the present invention has been described in considerable detail with reference to certain preferred versions and embodiments thereof, it should be understood that the present invention is not limited to the disclosed versions and embodiments, but rather, is capable of other versions and embodiments. The various embodiments disclosed below may be combined with or substituted for one another where appropriate, and additional embodiments may be added to one embodiment without further recitation or description. In the following description, numerous specific details are set forth to provide a thorough understanding of the following embodiments. However, embodiments of the invention may be practiced without these specific details.

Spatially relative terms, such as "lower," "upper," "lower," "top," and the like, are used herein to facilitate describing one element or feature relative to another element or feature in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In this document, unless the context requires otherwise, the word "a" and "an" may refer broadly to the singular or plural. It will be further understood that the terms "comprises," "comprising," "includes" and/or "including," when used herein, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of other features, regions, integers, steps, operations, elements, components, and/or groups thereof.

Although the methods disclosed herein are illustrated below as a series of acts or steps, the order in which the acts or steps are presented should not be construed as a limitation of the present invention. For example, certain operations or steps may be performed in a different order and/or concurrently with other steps. Moreover, not all illustrated operations, steps and/or features may be required to implement an embodiment of the present invention. Further, each operation or step described herein may comprise several sub-steps or actions.

An embodiment of the present invention provides a method for manufacturing a package structure, in which the package structure obtained by the method can improve coplanarity of conductive bumps of the package structure and improve yield of butt joint between the package structure and a chip or the package structure. Fig. 1 is a flow chart illustrating a method 10 for fabricating a package structure 100 according to an embodiment of the invention, and fig. 2-11 are schematic cross-sectional views illustrating various stages of the method 10. As shown in fig. 1, the method 10 includes steps S11 through S16.

In step S11, an additional circuit board 110 is provided, as shown in fig. 2. Specifically, the additional circuit board 110 includes a supporting layer 111, a first peeling layer 112, a second peeling layer 113, a first metal layer 114, and a second metal layer 115. The first peeling layer 112 and the second peeling layer 113 are disposed on the opposite surfaces of the support layer 111, respectively. The first metal layer 114 is disposed on the first peeling layer 112, and the second metal layer 115 is disposed on the second peeling layer 113. In some embodiments, the material of the supporting layer 111 may be, for example, an organic polymer material such as Bismaleimide Triazine (BT) or glass, and the supporting layer 111 may also be a Copper Clad Laminate (CCL) (not shown) having a dielectric material (e.g., a prepreg) bonded to both surfaces of the supporting layer. In some embodiments, the first release layer 112 and the second release layer 113 may each be a release film (release film), or other techniques may be applied to provide the first release layer 112 and the second release layer 113, such as: mitsui, Nippon-Denk, Furukawa, Olin, or the like. In some embodiments, the thickness of the first metal layer 114 and the second metal layer 115 may be selected from a range of 1 micron to 10 microns, but is not limited thereto, and the material of the first metal layer 114 and the second metal layer 115 may be copper, aluminum, nickel, silver, gold, or an alloy thereof, but is not limited thereto. In other embodiments, the first metal layer 114 and the second metal layer 115 are not limited to a single layer, and may be a stack of a plurality of first metal layers 114 and a plurality of second metal layers 115.

In another embodiment, another metal layer (not shown) may be included between the two opposite surfaces of the supporting layer 111 and the first peeling layer 112 or the second peeling layer 113, and the thickness of the another metal layer may be selected from a range of 5 microns to 40 microns, and the another metal layer may be the same as or different from the metal layer 114/115, such as copper, aluminum, nickel, silver, gold, or alloys thereof, but is not limited thereto.

In step S12, a first dielectric layer 120 is formed on the first metal layer 114 and the second metal layer 115, as shown in fig. 3. It is understood that the step S12 and its subsequent steps S13-S16 may be formed on one surface of the additional circuit board 110, or may be formed on two opposite surfaces of the additional circuit board 110. In the present embodiment, the double-sided production of the additional circuit board 110 will be described as an example. The material of the first dielectric layer 120 may include resin or glass fiber. For example, the resin may be a phenolic resin, an epoxy resin, a polyimide resin, or polytetrafluoroethylene. Alternatively, the material of the first Dielectric layer 120 may also include a Photo-electrically-sensitive Dielectric material (Photo-electrically). In some embodiments, the first dielectric layer 120 may be formed by Lamination (deposition), coating, or other suitable processes.

As shown in fig. 4, the first dielectric layer 120 has a plurality of holes 121, wherein each hole 121 has an end portion 122 adjacent to the first metal layer 114 or the second metal layer 115, and each end portion 122 is substantially flush with each other on the same plane. In some embodiments, the holes 121 are formed in a shape and a uniform depth by controlling the aperture size of the laser, so that the ends 122 of the holes 121 are substantially flush with each other on the same plane. In one embodiment, "coplanar" may refer to the same horizontal plane. In one embodiment, the "same plane" may be parallel to the surface of the support layer 111.

In step S13, a plurality of conductive bumps 130 are formed, and each of the conductive bumps 130 fills each of the holes 121, as shown in fig. 5. Each conductive bump 130 has a first end 131 and a second end 132 opposite to the first end 131, wherein each first end 131 corresponds to each end 122. In some embodiments, the material of the conductive bumps 130 may include any conductive metal, including, but not limited to, copper. Since the hole 121 is controlled to have a shape and a depth consistent with each other by the laser in step S12, the shape of each conductive bump 130 is correspondingly formed. In the present embodiment, each conductive bump 130 is conical, and each conductive bump 130 is substantially flush with each other on the same plane.

In this embodiment, when the first end 131 of each conductive bump 130 is conical, if each first end 131 contacts the first metal layer 114 or the second metal layer 115, uneven tearing is easily formed when each first end 131 is removed from the first metal layer 114 or the second metal layer 115 due to the small contact area. To keep the first ends 131 substantially flush with each other in the same plane, the end 122 of each hole 121 is not connected to the first metal layer 114. That is, the holes 121 are drilled by laser, and the first metal layer 114 or the second metal layer 115 is not penetrated and exposed.

In step S14, a circuit layer structure 140 is formed on the first dielectric layer 120 and the conductive bumps 130, as shown in fig. 5-7. Specifically, the circuit layer structure 140 includes at least one circuit layer 141 and at least one second dielectric layer 142. The number of dielectric layers and circuit layers can be flexibly selected by those skilled in the art according to actual needs. It is understood that the minimum units constituting the line layer structure 140 are one dielectric layer and one line layer. The circuit layer 141 is connected to the second end 132 of each conductive bump 130; in some embodiments, each conductive bump 130 is formed together with the lowest circuit layer 141 and is made of the same material. The second dielectric layer 142 is disposed on the circuit layer 141, wherein the second dielectric layer 142 has a plurality of conductive vias 143 and is electrically connected to the circuit layer 141.

In some embodiments, the material of the second dielectric layer 142 may include resin and glass fiber. For example, the resin may be a phenolic resin, an epoxy resin, a polyimide resin, or polytetrafluoroethylene. Alternatively, the material of the second Dielectric layer 142 may also include a Photo-electrically-sensitive Dielectric material (Photo-electrically). In some embodiments, the second dielectric layer 142 may be formed by Lamination (deposition), coating, or other suitable processes. In some embodiments, the blind via required for forming the conductive via 143 can be formed by, but not limited to, Laser ablation (Laser ablation) on the second dielectric layer 142 to form the blind via, or exposure and development when the material of the second dielectric layer 142 is selected from photosensitive dielectric material to form the blind via for forming the conductive via 143.

A method of forming the line layer 141 according to some embodiments of the present invention is briefly described below. First, a photoresist layer (not shown) such as a dry film is formed on the first dielectric layer 120, and the photoresist layer is patterned by photolithography to expose a portion of the first dielectric layer 120. Then, an electroplating process and a photoresist layer removing process are performed to form the circuit layer 141. A photoresist layer (not shown) such as a dry film is formed on the second dielectric layer 142, and the photoresist layer is patterned by photolithography to expose a portion of the second dielectric layer 142. Then, an electroplating process and a photoresist layer removing process are performed to form the circuit layer 141 and the conductive via 143. In one embodiment, the material of the circuit layer 141 and the conductive via 143 may be copper, for example. In other embodiments, a seed layer (not shown) may be formed on the dielectric layer 120/142 before the circuit layer 141 is formed. The seed layer may be a single layer or a multi-layer structure composed of sublayers of different materials, such as a metal layer including a titanium layer and a copper layer on the titanium layer, or a palladium-plated copper layer, but not limited thereto. The seed layer may be formed by, but is not limited to, physical means such as sputtered titanium copper, or chemical means such as a palladium copper plated layer.

In some embodiments, the circuit layer structure 140 includes a plurality of circuit layers 141 and a plurality of second dielectric layers 142, wherein the uppermost second dielectric layer 142 serves as a protection layer, as shown in fig. 8, wherein the protection layer has a plurality of openings 144 such that a portion of the surface of the circuit layer structure 140 is exposed in the openings 144. Specifically, as shown in fig. 8, a part of the surface of the circuit layer 141 at the outermost layer of the circuit layer structure 140 is exposed in the opening 144. In various embodiments, the material of the protective layer may be a solder mask material, or may be a resin material, such as epoxy resin. Alternatively, the material of the passivation layer may be the same as the material of the first dielectric layer 120 or the second dielectric layer 142. The protective layer can be formed by, for example, bonding, printing, coating, or the like.

In step S15, the first dielectric layer 120 is separated from the additional circuit board 110, as shown in fig. 9-10. The support layer 111, the first peeling layer 112, and the second peeling layer 113 are removed from the structure illustrated in fig. 8 to form two package structures 100. Then, the first metal layer 114 and the second metal layer 115 are removed. In one embodiment, the manner of removing the first metal layer 114 and the second metal layer 115 includes, but is not limited to, etching (etching).

In step S16, a portion of the first dielectric layer 120 is removed to expose the conductive bumps 130, as shown in fig. 10-11. In one embodiment, the first dielectric layer 120 is removed by, but not limited to, plasma thinning (plasma thinning). In the present embodiment, each conductive bump 130 is a cone.

Fig. 12 is a schematic cross-sectional view of a package structure 200 according to another embodiment of the invention. The package structure 200 includes a plurality of conductive bumps 130 and a circuit layer structure 140. Compared to the package structure 100 shown in fig. 11, the conductive bumps 130 on the package structure 200 shown in fig. 12 have a trapezoidal pillar shape. The manufacturing method of the package structure 200 of the present embodiment is similar to the manufacturing method of the package structure 100, and the difference is that the shape of the hole 121 (refer to fig. 5) in the step S13 is controlled by laser to form a trapezoidal pillar shape corresponding to the shape of each conductive bump 130. In one embodiment, the end 122 of each hole 121 and the first metal layer 114 may be connected. That is, each hole 121 is drilled by laser, and penetrates through and exposes the first metal layer 114 or the second metal layer 115. In another embodiment, the end portion 122 of each hole 121 is not connected to the first metal layer 114. That is, the holes 121 are drilled by laser without penetrating and exposing the first metal layer 114 or the second metal layer 115.

Fig. 13 is a schematic cross-sectional view of a package structure 300 according to another embodiment of the invention. The package structure 300 includes a plurality of conductive bumps 130 and a circuit layer structure 140. Compared to the package structure 100 shown in fig. 11, the conductive bumps 130 on the package structure 300 shown in fig. 13 are rectangular solids. The manufacturing method of the package structure 300 of the present embodiment is similar to the manufacturing method of the package structure 100, and the difference is that the shape of each conductive bump 130 is formed into a rectangular parallelepiped by controlling the shape of the hole 121 (refer to fig. 5) in step S13 by laser.

Another method for manufacturing a package structure is provided in an embodiment of the invention, as shown in fig. 14, which is a schematic cross-sectional view of a package structure 400 in this embodiment. The manufacturing method of the package structure 400 is substantially similar to the manufacturing method of the package structure 100, except that the manufacturing method of the package structure 400 is to perform single-sided fabrication on the additional circuit board 110 to form the package structure 400. The layers, elements, and materials of the layers and elements in the single-sided fabrication are discussed above and will not be described in detail. In some embodiments, the material of the support layer 111 may be selected to be glass. Because the glass material has high rigidity and flatness, the two ends of the supporting layer 111 can be prevented from warping. Therefore, when the supporting layer 111 is made of glass, in addition to performing processes on two opposite surfaces of the supporting layer 111 to form the package structure 100, it is also feasible to perform processes on only one surface of the supporting layer 111 to form the package structure 400.

Fig. 15 is a schematic cross-sectional view illustrating a package structure 500 according to another embodiment of the invention. The package structure 500 includes a first dielectric layer 120, a plurality of conductive bumps 130, and a circuit layer structure 140. The first dielectric layer 120 has an upper surface 120a and a lower surface 120b opposite to each other. The conductive bumps 130 have opposite first ends 131 and second ends 132, and each conductive bump 130 extends upward through the first dielectric layer 120. The first ends 131 are located on top of the conductive bumps 130 (i.e., the first ends 131 are higher than the upper surface 120a), and the first ends 131 are substantially flush with each other on the same plane. These second ends 132 are flush with the lower surface 120b of the first dielectric layer 120. The circuit layer structure 140 is disposed under the first dielectric layer 120, and the circuit layer structure 140 includes a first circuit layer 145, a second dielectric layer 146, a second circuit layer 147, a plurality of first conductive vias 149, and a third dielectric layer 148. The first circuit layer 145 is disposed under the lower surface 120b of the first dielectric layer 120, and the second ends 132 of the conductive bumps 130 are electrically connected to the first circuit layer 145. The second dielectric layer 146 covers the first circuit layer 145 and the first dielectric layer 120 and has a plurality of first openings exposing the first circuit layer 145. The first conductive vias 149 are disposed in the first openings of the second dielectric layer 146, and the first conductive vias 149 are electrically connected to the first circuit layer 145. The second circuit layer 147 is disposed under the second dielectric layer 146 and electrically connected to the first conductive holes 149. The third dielectric layer 148 covers the second dielectric layer 146 and the second circuit layer 147, and has at least one second opening 150 exposing the second circuit layer 147. In one embodiment, the third dielectric layer 148 is also referred to as a solder mask layer, and the material thereof may be solder mask material or resin material, such as epoxy resin. The solder mask layer can be formed by, for example, bonding, printing, coating, or the like.

One embodiment of the present invention provides a direct metal-to-metal interface between two package structures by using conductive bumps with high coplanarity, as shown in fig. 16. The lower package structure 100 and the upper package structure 200 are butted to each other by the first ends 131 of the respective conductive bumps 130.

One embodiment of the present invention provides a metal-to-metal direct interface between the package structure 100 and the chip 900 by using conductive bumps with high coplanarity, as shown in fig. 17. The chip 900 has a plurality of conductive contacts 910, and each of the conductive contacts 910 is directly connected to each of the first ends 131.

In the package structure and the method for manufacturing the same according to an embodiment of the present invention, a method for manufacturing an Embedded Trace Substrate (ETS) is used in combination with a hole with a controllable uniform depth to form a highly coplanar conductive bump, so as to replace a conventional method for manufacturing a copper pillar by chemical polishing or physical polishing. Specifically, after controlling the holes with the same depth of the dielectric layer by laser, the conductive bumps and the circuit layer with high coplanarity are formed, and finally, part of the dielectric layer is removed to expose the conductive bumps. Therefore, the packaging structure and the chip, the circuit board or the packaging structure are directly butted by metal-metal by using the conductive bumps with high coplanarity, so that the yield is higher.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications may be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.