阅读说明：本技术 一种铜再布线层的制造方法、硅光器件及芯片 (Manufacturing method of copper rewiring layer, silicon optical device and chip ) 是由 杨妍 于 2020-10-21 设计创作，主要内容包括：本发明公开一种铜再布线层的制造方法、硅光器件及芯片,涉及硅光器件制造技术领域,用于解决硅光器件或芯片中的铝再布线层的电导率低、集肤效应大,高频特性不足的问题。铜再布线层的制造方法包括：提供一基底；在基底的表面形成再布线图形,再布线图形包括布线区和第一隔离区；在布线区形成铜再布线层；形成与铜再布线层接触的微凸块或凸块下金属。铜再布线层由上述铜再布线层的制造方法制造。本发明提供的铜再布线层的制造方法用于硅光器件和芯片制造。(The invention discloses a manufacturing method of a copper rewiring layer, a silicon optical device and a chip, relates to the technical field of manufacturing of silicon optical devices, and aims to solve the problems of low conductivity, large skin effect and insufficient high-frequency characteristics of an aluminum rewiring layer in the silicon optical device or the chip. The method for manufacturing the copper rewiring layer comprises the following steps: providing a substrate; forming a rewiring pattern on the surface of the substrate, wherein the rewiring pattern comprises a wiring area and a first isolation area; forming a copper rewiring layer in the wiring area; forming a micro bump or under bump metallization in contact with the copper rewiring layer. The copper rewiring layer is manufactured by the method for manufacturing the copper rewiring layer. The manufacturing method of the copper rewiring layer is used for manufacturing the silicon optical device and the chip.)

1. A method of manufacturing a copper rewiring layer, comprising:

providing a substrate;

forming a re-wiring pattern on the surface of the substrate, wherein the re-wiring pattern comprises a wiring region and a first isolation region;

forming a copper rewiring layer in the wiring area;

and forming a micro bump or under bump metal in contact with the copper rewiring layer.

2. The method of manufacturing a copper rewiring layer according to claim 1, wherein the base includes a semiconductor substrate, and an oxide layer formed on the semiconductor substrate; forming a re-wiring pattern on a surface of the substrate, including:

sequentially forming a barrier layer and a copper seed layer on the oxide layer;

forming a first photoresist layer on the copper seed layer;

and patterning the first photoresist layer to form the re-wiring pattern.

3. The method of manufacturing a copper redistribution layer as claimed in claim 2, wherein forming a copper redistribution layer in the wiring region includes:

forming a copper material layer in the wiring area;

removing the first photoresist layer;

and removing the part of the copper seed layer corresponding to the first isolation region to form the copper rewiring layer in the wiring region.

4. The method of claim 1, wherein after the copper redistribution layer is formed in the wiring region and before the micro-bump or under-bump metal is formed, the method further comprises:

and forming an opening layer on the copper rewiring layer, wherein the opening layer is provided with a plurality of openings.

5. The method of manufacturing a copper redistribution layer as claimed in claim 4, wherein forming an opening layer on the copper redistribution layer comprises:

forming a first dielectric layer covering the copper rewiring layer;

photoetching and developing the first dielectric layer to form a plurality of openings, wherein the plurality of openings are at least contacted with the surface of the copper rewiring layer;

and curing the first medium layer with a plurality of openings.

6. The method of manufacturing a copper redistribution layer as claimed in claim 4, wherein forming an opening layer on the copper redistribution layer comprises:

forming a second dielectric layer covering the copper rewiring layer;

forming a second photoresist layer covering the second dielectric layer;

photoetching and developing the second photoresist layer to form a photoresist pattern;

etching the second dielectric layer under the masking of the photoresist pattern to form a plurality of openings, wherein the plurality of openings are at least contacted with the surface of the copper rewiring layer;

and removing the photoresist pattern.

7. The method of claim 4, wherein forming a micro-bump or an under-bump metal comprises:

sequentially forming a barrier layer and a copper seed layer, wherein the barrier layer and the copper seed layer cover the surface of the opening layer and the side walls and the bottom wall of the plurality of openings of the opening layer;

forming a third photoresist layer, wherein the third photoresist layer covers the copper seed layer;

patterning the third photoresist layer to form a micro bump pattern or an under bump metal pattern, the micro bump pattern or the under bump metal pattern including an opening region and a second isolation region;

forming a micro-bump material layer or under-bump metal, wherein the micro-bump material layer or the under-bump metal material layer fills the opening area;

and removing the third photoresist layer and the part of the copper seed layer corresponding to the second isolation region to form the micro bump or the under bump metal.

8. The method of manufacturing a copper rewiring layer according to claim 7, wherein the opening region includes the opening and a flare over the opening; the diameter of the flaring is larger than that of the opening; and/or the thickness of the third photoresist layer is larger than the thickness of the micro-bump or the under-bump metal in the flaring.

9. A silicon optical device characterized by comprising a copper rewiring layer manufactured by the method for manufacturing a copper rewiring layer according to any one of claims 1 to 8.

10. A silicon photonics chip comprising the silicon photonics device of claim 9.

Technical Field

The invention relates to the technical field of silicon optical device manufacturing, in particular to a manufacturing method of a copper rewiring layer, a silicon optical device and a chip.

Background

The core content of a silicon-based optoelectronic device (silicon optical device for short) is to research how to miniaturize and silicon-plate a photonic device and integrate the photonic device with a nano electronic device. The method is characterized in that silicon or other materials compatible with silicon are utilized, a silicon process is utilized, a plurality of micro-nano-scale information functional devices are simultaneously manufactured on the same silicon substrate, and photons and/or electrons are used as carriers, so that a complete novel large-scale integrated chip with comprehensive functions is formed.

The preparation process of the silicon optical device generally depends on improvement or development under the support of the existing CMOS process and equipment, and part of the process needs to be developed again.

In the conventional CMOS process, aluminum metal is generally used in the RDL, and thus the existing RDL process of the silicon optical device also uses aluminum metal. The use of aluminum metal as the RDL has the problems of low conductivity, large skin effect and insufficient high frequency characteristics.

Disclosure of Invention

The invention aims to provide a manufacturing method of a copper rewiring layer, a silicon optical device and a chip, which are used for solving the problems of low conductivity, large skin effect and insufficient high-frequency characteristics of an aluminum rewiring layer in the silicon optical device or the chip.

In order to achieve the above purpose, the invention provides the following technical scheme:

a method of manufacturing a copper rewiring layer, comprising:

providing a substrate;

forming a rewiring pattern on the surface of the substrate, wherein the rewiring pattern comprises a wiring area and a first isolation area;

forming a copper rewiring layer in the wiring area;

forming a micro bump or under bump metallization in contact with the copper rewiring layer.

Compared with the prior art, the manufacturing method of the copper rewiring layer provided by the invention can form the copper rewiring layer in the silicon optical device, and the copper rewiring layer has conductivity and smaller skin effect compared with the traditional aluminum rewiring layer, so that the high-frequency characteristic of the copper rewiring layer is better. And the silicon optical device with the copper rewiring layer has higher electrical performance.

The invention also provides a silicon optical device. The silicon optical device includes a copper rewiring layer manufactured by the above-described method of manufacturing a copper rewiring layer.

Compared with the prior art, the beneficial effect of the silicon optical device provided by the invention is the same as that of the manufacturing method of the copper rewiring layer in the technical scheme, and the detailed description is omitted here.

The embodiment of the invention also provides a silicon optical chip. The silicon optical chip comprises the silicon optical device.

Compared with the prior art, the beneficial effects of the silicon optical chip provided by the invention are the same as those of the silicon optical device in the technical scheme, and the details are not repeated here.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:

fig. 1 is a flowchart of a method for manufacturing a copper redistribution layer according to an embodiment of the present invention;

FIG. 2 is a process diagram of a method of fabricating a copper redistribution layer in accordance with an embodiment of the present invention;

FIGS. 3A-3B are process diagrams of a method of fabricating a copper redistribution layer in accordance with an embodiment of the present invention;

FIGS. 4A-4B are process diagrams of a method of fabricating a copper redistribution layer in accordance with an embodiment of the present invention;

FIGS. 5A-5F are process diagrams of a method of fabricating a copper redistribution layer in accordance with an embodiment of the present invention;

fig. 6A to 6E are process diagrams of a method for manufacturing a copper re-wiring layer according to an embodiment of the present invention.

Reference numerals:

1-base, 101-oxide layer, 102-substrate,

2-a first photoresist layer, 201-a wiring region, 3-a copper material layer,

4-dielectric layer, 401-opening, 5-second photoresist layer,

501-opening pattern, 6-third photoresist layer, 7-under bump metal;

8-micro bumps.

Detailed Description

In order to facilitate clear description of technical solutions of the embodiments of the present invention, in the embodiments of the present invention, terms such as "first" and "second" are used to distinguish the same items or similar items having substantially the same functions and actions. For example, the first threshold and the second threshold are only used for distinguishing different thresholds, and the sequence order of the thresholds is not limited. Those skilled in the art will appreciate that the terms "first," "second," etc. do not denote any order or quantity, nor do the terms "first," "second," etc. denote any order or importance.

It is to be understood that the terms "exemplary" or "such as" are used herein to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

In the present invention, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a and b combination, a and c combination, b and c combination, or a, b and c combination, wherein a, b and c can be single or multiple.

In the process of manufacturing silicon-based optoelectronic devices (silicon optoelectronic devices for short), a packaging process is generally included. The packaging process generally involves the fabrication of a rewiring layer. The Redistribution Layer (RDL) is a structure in which the contact position of the circuit of the originally designed integrated circuit is changed by a wafer level metal wiring process and a bump process, so that the integrated circuit can be applied to different packaging forms. The technical field of silicon optical devices is a new device field of Semiconductor devices with short development time and high development difficulty, and the development process of the manufacturing process of the silicon optical devices is developed on the basis of a Complementary Metal Oxide Semiconductor (CMOS) manufacturing process by referring to the CMOS manufacturing process.

In a conventional CMOS process, the RDL is made of aluminum. On one hand, the process of using aluminum metal as RDL is simple. However, as silicon optical devices are developed, the process size of the devices starts to be smaller and smaller, and the performance requirements of the devices are higher and higher. Aluminum metal used as RDL has the problems of low conductivity, large skin effect and insufficient high-frequency characteristics. Due to the limitation of the electrical performance of the RDL formed of aluminum metal, it is difficult to satisfy the operating performance of the silicon optical device. Therefore, the current use of copper as the material of RDL is a technological development trend.

However, when copper is used as the RDL material, the silicon optical device production line, equipment and process established by the original CMOS reference cannot be used continuously. There is a need for a new method for manufacturing a redistribution layer to implement the application of copper metal in a redistribution layer of a silicon optical device.

In view of the above technical problems, embodiments of the present invention provide a method for manufacturing a copper redistribution layer. Fig. 1 illustrates a flowchart of a method for manufacturing a copper redistribution layer according to an embodiment of the present invention. As shown in fig. 1, the method of manufacturing a copper redistribution layer includes:

fig. 2 is a process diagram illustrating a method for manufacturing a copper redistribution layer according to an embodiment of the present invention. Referring to fig. 2, a substrate 1 is provided. The base 1 may be a conventional substrate 102 such as a bulk silicon substrate or a silicon-on-insulator substrate, and an oxide layer 101 formed on a surface of the substrate 102. For example, the oxide layer 101 may be formed on the surface of the substrate 102 by any conventional Deposition process, such as Chemical Vapor Deposition (CVD), Molecular Beam Epitaxy (MBE). The oxide layer 101 does not necessarily refer to a compound containing an oxygen element. Any of compounds produced by a redox reaction or compounds formed by a redox reaction with the silicon element of the substrate 102 may be used. The material of the oxide layer 101 may be silicon nitride, silicon oxide, or the like.

The base 1 may also be the base 1 on which active devices and passive devices have been formed on the substrate 102 through a front-end process. For example, the active device may be a silicon optically active device and the passive device may be a silicon optically passive device. The silicon optically active devices may include, but are not limited to, modulators and detectors. The silicon optical passive devices may include, but are not limited to, silicon or silicon nitride waveguides, gratings, arrayed waveguide gratings, microring resonators, multimode interferometers, thermo-optic devices, and the like. The surface of the substrate 1 having the active devices and the passive devices is further provided with an oxide layer 101 covering the above active devices and passive devices.

Fig. 3A to 3B are process diagrams illustrating a method of manufacturing a copper re-wiring layer according to an embodiment of the present invention. Referring to fig. 3A to 3B, a re-wiring pattern including a wiring region 201 and a first isolation region is formed on the surface of the substrate 1. The base 1 includes a semiconductor substrate 102, and an oxide layer 101 formed on the semiconductor substrate 102. The above-mentioned forming of the re-wiring pattern on the surface of the substrate 1 may include:

the oxide layer 101 may be silicon oxide at this time, and a barrier layer and a copper seed layer are sequentially formed on the oxide layer 101. The material of the barrier layer is at least one of tantalum, titanium, tantalum nitride and titanium nitride. In order to prevent the copper metal from diffusing in the oxide layer 101 and damaging the interlayer structure of the silicon optical device, the barrier layer is used to block the copper metal, and the copper metal is electrically connected to the oxide layer 101. The copper seed layer provides a basis for the subsequent formation of the copper material layer 3. The process of forming the barrier layer may be physical vapor deposition or chemical vapor deposition. The process of forming the copper seed layer may be physical vapor deposition. After the barrier layer or the copper seed layer is formed, surface cleaning is performed using plasma of an inert gas, such as argon.

Referring to fig. 3A, a first photoresist layer 2 is formed on the copper seed layer. The photoresist is a positive photoresist, such as a conventional photoresist that can be exposed to 365nm light. Copper metal is difficult to remove by adopting an etching mode, and a copper rewiring layer cannot be formed by negative etching. The conventional al rewiring layer forming process is not applicable.

Referring to fig. 3B, the first photoresist layer 2 is patterned to form a re-wiring pattern. The first photoresist layer 2 is exposed and developed to form the rewiring pattern. The area where the re-wiring pattern is developed forms the wiring area 201, and the area of the first photoresist layer 2 other than the wiring area 201 forms the first isolation area.

Fig. 4A to 4B are process diagrams illustrating a method of manufacturing a copper re-wiring layer according to an embodiment of the present invention. Referring to fig. 4A to 4B, a copper re-wiring layer is formed in the wiring region 201. The above-mentioned forming of the copper re-wiring layer in the wiring region 201 may include:

referring to fig. 4A, a copper material layer 3 is formed in the wiring region 201. The copper material layer 3 may be formed by electroplating.

The first photoresist layer 2 is removed. After removing the first photoresist layer 2, surface cleaning may be performed using acetic acid.

Referring to fig. 4B, a portion of the copper seed layer corresponding to the first isolation region is removed to form a copper re-wiring layer in the wiring region 201. After the copper material layer 3 is electroplated, the copper seed layer and the barrier layer corresponding to the first isolation region need to be removed, and the copper redistribution layer can be formed only by the copper material layer 3 corresponding to the wiring region 201 and the copper seed layer and the barrier layer below the copper seed layer. The copper seed layer and the barrier layer can be removed by wet etching.

Fig. 5A to 5B are process diagrams illustrating a method of manufacturing a copper re-wiring layer according to an embodiment of the present invention. Referring to fig. 5A to 5B, an opening 401 is formed on the copper rewiring layer, the opening 401 having a plurality of openings 401. The forming of the opening 401 in the copper rewiring layer may include:

referring to fig. 5A, a dielectric layer 4 is formed overlying the copper re-wiring layer, where dielectric layer 4 may be the first dielectric layer. The material of the first dielectric layer can be positive photoresist such as polybenzoxazole or polyimide. Polybenzoxazole is a positive photoresist that can be exposed to 365nm light.

Referring to fig. 5B, the first dielectric layer is patterned and developed to form a plurality of openings 401, and the plurality of openings 401 are in contact with at least the surface of the copper redistribution layer. The number and positions of the openings 401 correspond to the number and positions of the micro bumps 8 or the under bump metallurgy 7 to be arranged subsequently.

Referring to fig. 5C, the first dielectric layer having the plurality of openings 401 is cured. The technological parameters for curing the first dielectric layer include a curing temperature and a curing time, and when the first dielectric layer is polybenzoxazole, the curing temperature may be 200 ℃, and the curing time may be greater than or equal to 1 hour. The first dielectric layer serves to protect the copper redistribution layer and only exposes the portion to be connected with the micro-bump 8 or the under-bump metal 7. Wherein the mechanical property and the heat resistance of the polybenzoxazole are the better organic fibers at present. The overall performance of the silicon optical device can be improved.

The above-mentioned formation of the opening 401 in the copper rewiring layer may be realized by any curable positive photoresist, and is not limited to the above-mentioned polybenzoxazole or polyimide.

Fig. 5C to 5F are process diagrams illustrating a method of manufacturing a copper re-wiring layer according to an embodiment of the present invention. Referring to fig. 5C to 5F, when the material layer is not a photoresist, the forming of the opening 401 on the copper redistribution layer may further include:

referring to fig. 5C, a dielectric layer 4 is formed overlying the copper re-wiring layer, where dielectric layer 4 may be a second dielectric layer. The second dielectric layer may be a non-photoresist oxide layer such as silicon oxide or silicon nitride. The silicon oxide described above may be formed using plasma chemical vapor deposition. The shaping is not limited here.

Referring to fig. 5C, a second photoresist layer 5 is formed overlying the second dielectric layer 4. When the dielectric layer 4 is formed using a non-photoresist, an opening 401 is formed to fill the copper material layer 3. The opening 401 of the second dielectric layer is formed by etching.

Referring to fig. 5D, the second photoresist layer 5 is etched and developed to form a photoresist pattern including an opening pattern 501 for etching the dielectric layer. The photoresist is a positive photoresist, and 365nm exposure photoresist or other positive photoresists can be adopted.

Referring to fig. 5E, the second dielectric layer is etched under the mask of the photoresist pattern to form a plurality of openings 401, the plurality of openings 401 being in contact with at least the surface of the copper re-wiring layer. When the second dielectric layer is silicon nitride, the opening 401 may be formed by dry etching, and the reaction gas of the dry etching may be composed of fluorine sulfide and oxygen. When the second dielectric layer is silicon oxide, the opening 401 may be formed by dry etching, and the reaction gas of the dry etching is composed of oxygen and fluorocarbon. The opening 401 may be wet etched, and the reaction solution for the wet etching may be composed of hydrofluoric acid. The method of forming the opening 401 in the second dielectric layer is not limited to the above molding method, and the opening 401 may be formed.

Referring to fig. 5F, the photoresist pattern is removed. And removing the second photoresist layer 5, and cleaning with acetic acid after the removal is finished.

Fig. 6A to 6E are process diagrams illustrating a method of manufacturing a copper re-wiring layer according to an embodiment of the present invention. Referring to fig. 6A to 6E, a micro bump 8 or an under bump metal 7 is formed in contact with the copper re-wiring layer. The above-mentioned formation of the micro bump 8 or the under bump metal 7 includes:

a barrier layer and a copper seed layer are sequentially formed, and the barrier layer and the copper seed layer cover the surface of the opening 401 layer and the side walls and the bottom wall of the plurality of openings 401 included in the opening layer. The barrier layer and the copper seed layer are formed by physical vapor deposition. The material of the barrier layer may be at least one of tantalum, titanium, tantalum nitride, and titanium nitride.

Referring to fig. 6A, a third photoresist layer 6 is formed, the third photoresist layer 6 covering the copper seed layer. The height of the micro-bump 8 or the under-bump metal 7 relative to the substrate 1 is higher than that of the dielectric layer 4 (the dielectric layer 4 corresponds to the first dielectric layer or the second dielectric layer). It is therefore necessary to provide a corresponding space for the opening 401 in the dielectric layer 4 by means of the third photoresist layer 6.

Referring to fig. 6B, the third photoresist layer 6 is patterned to form a micro bump 8 pattern or an under bump metal 7 pattern, the micro bump 8 pattern or the under bump metal 7 pattern including an open region and a second isolation region. The third photoresist layer 6 is formed using a positive photoresist.

Referring to fig. 6C, a micro bump 8 material layer or an under bump metal 7 is formed, and the micro bump 8 material layer or the under bump metal 7 material layer fills the opening area. The open area may include an opening 401 and a flare over the opening 401. The flare is formed after development of the third photoresist layer 6. The diameter of the flare may be greater than the diameter of the opening 401. The thickness of the third photoresist layer 6 may be greater than the thickness of the microbump 8 or underbump metallization 7 within the counterbore. The material of the micro-bump 8 may be copper, nickel and silver-tin alloy, and the material of the under-bump metal 7 may be copper, nickel and gold. The micro bumps 8 and the under bump metallurgy 7 can be formed by electroplating. The shape of the micro-bumps 8 or the under-bump metallurgy 7 can be controlled by the flaring of the opening area and the size of the opening 401. The thickness of the micro-bump 8 or the under-bump metal 7 may be controlled by controlling the thickness of the third photoresist layer 6.

Referring to fig. 6D and 6E, the third photoresist layer 6 and the copper seed layer are removed to form the micro bump 8 or the under bump metallization 7. After the formation of the micro-bump 8 or the under-bump metal 7 is completed, the barrier layer and the copper seed layer outside the opening area need to be removed. The copper seed layer and the barrier layer can be removed by wet etching. And the materials used for the processing of the micro-bumps 8 and the under-bump metals 7 can be different. The thicknesses of the first photoresist layer and the second photoresist layer are different from each other with respect to the substrate 1, and particularly, when the third photoresist layer 6 is formed, the thickness of the third photoresist layer 6 is controlled to control the forming thicknesses of the micro bump 8 and the under bump metal 7. After the formation of the cylindrical structure shown in fig. 6E, the micro bump 8 is then formed into a ball shape by heating, and the detailed formation and illustration thereof are not repeated herein.

By the manufacturing method of the copper rewiring layer, the copper rewiring layer can be formed in the field of silicon optical devices, and therefore the performance of the silicon optical device with the copper rewiring layer is improved. The copper of the copper rewiring layer has higher conductivity and smaller skin effect than aluminum, and thus has better high frequency characteristics.

The embodiment of the invention also provides a silicon optical device. The silicon optical device comprises the copper rewiring layer and the copper rewiring layer manufactured by the manufacturing method of the copper rewiring layer.

Compared with the prior art, the beneficial effect of the silicon optical device provided by the invention is the same as that of the manufacturing method of the copper rewiring layer in the technical scheme, and the detailed description is omitted here.

The embodiment of the invention also provides a silicon optical chip. The silicon optical chip comprises the silicon optical device.

Compared with the prior art, the beneficial effects of the silicon optical chip provided by the invention are the same as those of the silicon optical device in the technical scheme, and the details are not repeated here.

The embodiment of the invention also provides a semiconductor device. The semiconductor device comprises the copper rewiring layer and the copper rewiring layer manufactured by the manufacturing method of the copper rewiring layer. The semiconductor device may be a CMOS device.

Compared with the prior art, the semiconductor device provided by the invention has the same beneficial effect as the manufacturing method of the copper rewiring layer in the technical scheme, and the detailed description is omitted here.

While the invention has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

While the invention has been described in conjunction with specific features and embodiments thereof, it will be evident that various modifications and combinations can be made thereto without departing from the spirit and scope of the invention. Accordingly, the specification and figures are merely exemplary of the invention as defined in the appended claims and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.