阅读说明：本技术 Pwm软开关阻抗调节并联均流固体功率控制器 (PWM soft switch impedance adjustment parallel current-sharing solid power controller ) 是由 洪峰 郑圣楠 陈奇 习志扬 任家琪 陈群 林豪 殷成彬 杜泽霖 于 2020-09-25 设计创作，主要内容包括：本发明是PWM软开关阻抗调节并联均流固体功率控制器,包括多组相互并联的固体功率控制器,每组固体功率控制器包括用于对所属固体功率控制器流经电流进行高精度差分采样的高端采样电路；用于通过输入控制器输入控制信号去启动微控制器工作,微控制器能够实现接收输入控制信号常通主副功率开关管、并对采样电流进行模拟量到数字量的转换判断均流状态进行调节控制输出PWM软开关驱动副功率开关管的输入控制器与微处理器驱动电路；实现对输入电压的导通与关断,用于导通给负载供电并通过PWM软开关控制副功率开关管导通状态用来改变导通阻抗实现多组固体功率控制器并联均流的并联功率开关管电路和电压转换电路；能够实现多路固体功率控制器并联均流。(The invention relates to a PWM (pulse-width modulation) soft switch impedance adjustment parallel current-sharing solid power controller, which comprises a plurality of groups of solid power controllers connected in parallel, wherein each group of solid power controllers comprises a high-end sampling circuit for carrying out high-precision differential sampling on current flowing through the solid power controller; the input controller and the microprocessor driving circuit are used for inputting a control signal through the input controller to start the microcontroller to work, and the microcontroller can realize that the input control signal is received to normally switch on the main power switching tube and the auxiliary power switching tube, and converts the sampling current from analog quantity to digital quantity to judge the current sharing state and regulate, control and output the PWM soft switch to drive the auxiliary power switching tube; the parallel power switch tube circuit and the voltage conversion circuit are used for realizing the on-off of input voltage, supplying power to a load in a conducting way, and changing the conducting impedance to realize the parallel current sharing of a plurality of groups of solid power controllers by controlling the conducting state of the auxiliary power switch tube through the PWM soft switch; the parallel current sharing of the multi-path solid power controller can be realized.)

PWM soft switch impedance adjustment connects solid power controller that flow equalizes in parallel, its characterized in that: the system comprises a plurality of groups of solid power controllers which are connected in parallel, wherein each group of solid power controllers comprises a high-end sampling circuit (1), an input controller and microprocessor driving circuit (2), a parallel power switch tube circuit (3) and a voltage conversion circuit (4);

the high-end sampling circuit (1) is used for carrying out high-precision differential sampling on the current flowing through the solid power controller;

the input controller and microprocessor driving circuit (2) is used for inputting a control signal through the input controller to start the microcontroller to work, the microcontroller can receive the input control signal and normally switch on the main power switch tube and the auxiliary power switch tube, and converts the sampling current from analog quantity to digital quantity to judge the current sharing state and regulate and control the output PWM soft switch to drive the auxiliary power switch tube;

the parallel power switch tube circuit (3) is used for realizing the on-off of input voltage, is used for conducting and supplying power to a load, and controls the conducting state of the auxiliary power switch tube through the PWM soft switch to change conducting impedance so as to realize the parallel current sharing of a plurality of groups of solid power controllers;

the voltage conversion circuit (4) is used for providing working voltage.

2. The PWM soft-switching impedance-regulated parallel current-sharing solid-state power controller of claim 1, wherein: the parallel power switch tube circuit (3) comprises a first main tube power switch tube BQ1 and a second auxiliary tube power switch tube BQ2, the drain electrode of the first main tube power switch tube BQ1 is connected with an input voltage VIN, the drain electrode of the second auxiliary tube power switch tube BQ2 is connected with the input voltage VIN, and the source electrode of the first main tube power switch tube BQ1 is connected with the source electrode of the second auxiliary power switch tube BQ2 to form the output end of the parallel power switch tube circuit (3).

3. The PWM soft-switching impedance-regulated parallel current-sharing solid-state power controller of claim 2, wherein: the high-end sampling circuit (1) comprises a first sampling resistor Rsamp, a first operational amplifier U1, a second sampling resistor R1, a third sampling resistor R2, a fourth sampling resistor R3 and a fifth sampling resistor Rf;

one end of the first sampling resistor Rsamp is connected with one end of the second sampling resistor R1, the other end of the first sampling resistor Rsamp is connected with one end of the third sampling resistor R2, one end of the first sampling resistor Rsamp is connected with the output end of the parallel power switch tube circuit (3), the other end of the first sampling resistor Rsamp is connected with one end of the output load Rload, and the other end of the output load Rload is grounded; the other end of the second sampling resistor R1 is in short circuit with the reverse input end of the first operational amplifier U1 and is connected with one end of a fifth sampling resistor Rf, the other end of the fifth sampling resistor Rf is connected with the output end of the first operational amplifier U1, the other end of the third sampling resistor R2 is in short circuit with the homodromous input end of the first operational amplifier U1 and is connected with one end of a fourth sampling resistor R3, the other end of the fourth sampling resistor R3 is connected with a digital power ground SGNG, the voltage input end of the first operational amplifier U1 is connected with VCC, the ground end of the first operational amplifier is connected with the digital power ground SGNG, and the output end of the first operational amplifier U1 is connected with a current sampling port Vs of the microprocessor G1.

4. The PWM soft-switching impedance-regulated parallel current-sharing solid-state power controller of claim 3, wherein: the input controller and microprocessor driving circuit (2) comprises an input controller C1, a microprocessor G1, a current sampling port Vs, a driving output port GA1, a driving output port GA2, a first driving resistor R4, a second driving resistor R5, a third driving resistor R6, a first driving triode BC1, a second driving triode BC2, a third driving triode BC3, a fourth driving triode BC4, a fourth driving resistor R7, a fifth driving resistor R8, a sixth driving resistor R9, a fifth driving triode BC5, a sixth driving triode BC6, a seventh driving triode BC7 and an eighth driving triode BC 8;

the output bus port Cc of the input controller C1 is connected with the input bus port Gc of the microprocessor G1, the microcontroller driving output interface GA1 is connected with the base of the first driving triode BC1, the collector of the first driving triode BC1 is short-circuited with one end of the third driving resistor R6 and the base of the second driving triode BC2 and is connected with one end of the first driving resistor R4, the emitter of the first driving triode BC1 is short-circuited with the other end of the third driving resistor R6 and the emitter of the second driving triode BC2 and is connected to the SGNG of a digital power supply ground, the other end of the first driving resistor R4 is short-circuited with one end of the second driving resistor R5 and the collector of the third driving triode BC3 and is connected to the power supply V15, the other end of the second driving resistor R5 is short-circuited with the collector of the second driving triode BC2 and the base of the third driving triode BC3 and is connected with the base of the fourth driving triode BC4, an emitter of a third driving triode BC3 is shorted with an emitter of a fourth driving triode BC4 and is connected with a gate of a first main power switching tube BQ1, a collector of the fourth driving triode BC4 is connected with an output end of a parallel power switching tube circuit (3), a microcontroller driving output interface GA2 is connected with a base of a fifth driving triode BC5, a collector of the fifth driving triode BC5 is shorted with one end of a sixth driving resistor R9 and a base of a sixth driving triode BC6 and is connected with one end of a fourth driving resistor R7, an emitter of the fifth driving triode BC5 is shorted with the other end of the sixth driving resistor R9 and an emitter of the sixth driving triode BC6 and is connected to a digital power ground SGNG, the other end of the third driving resistor R7 is shorted with one end of the fourth driving resistor R8 and a collector of a seventh driving triode 7 and is connected to a power supply V6, the other end of the fourth driving resistor R353642 is shorted with the base of the sixth driving triode BC 27 and the collector of the seventh driving triode BC 73727 and the eighth driving triode BC7 and is connected with an eighth driving triode BC 15 The base electrode of the driving triode BC8 is connected, the emitter electrode of the seventh driving triode BC7 is in short circuit with the emitter electrode of the eighth driving triode BC8 and is connected with the grid electrode of the second auxiliary power switch tube BQ2, and the collector electrode of the eighth driving triode BC8 is connected with the output end of the parallel power switch tube circuit (3).

5. The PWM soft-switching impedance-regulated parallel current-sharing solid-state power controller of claim 4, wherein: the first driving triode BC1, the second driving triode BC2, the third driving triode BC3, the fifth driving triode BC5, the sixth driving triode BC6 and the seventh driving triode BC7 are all NPN type triodes; the fourth driving transistor BC4 and the eighth driving transistor BC8 are both PNP transistors.

6. The PWM soft-switching impedance-regulated parallel current-sharing solid-state power controller of claim 4, wherein: the voltage conversion circuit (4) comprises a first voltage conversion resistor TR1, a first conversion voltage triode TBC1, a first voltage conversion capacitor TC1, a first voltage stabilizing diode ZG1, a digital power supply and a digital power supply ground SGNG;

the digital power supply is in short circuit with one end of a first voltage conversion resistor TR1 and is connected with a collector of a first conversion voltage triode TBC1, the other end of the first conversion resistor TR1 is in short circuit with a base of the first conversion voltage triode TBC1 and is connected with a cathode of a first voltage stabilizing diode ZG1, an anode of the first voltage stabilizing diode ZG1 is in short circuit with one end of a first voltage conversion capacitor TC1 and is connected with a digital power supply ground SGNG, and the other end of the first voltage conversion capacitor TC1 is in short circuit with an emitter of the first conversion voltage triode TBC1 and is connected with an operational amplifier power supply VCC.

Technical Field

The invention relates to the technical field of power electronics, in particular to a PWM (pulse-width modulation) soft switch impedance adjustment parallel current-sharing solid power controller.

Background

With the continuous development of technologies such as aviation manufacturing, control and maintenance, the overall performance of the airplane is greatly improved, the overall electric equipment on the airplane is increased rapidly, the power supply power is increased continuously, and the automatic power distribution system becomes the high-power distribution research direction of the airplane power system. The related research of Solid State Power Controllers (SSPCs) in an automatic Power distribution system is more and more emphasized by professionals, and meanwhile, some specific occasions also put higher requirements on the Solid State Power Controllers: due to the circuit layout and the influence of the ambient temperature, parasitic parameters of the solid power controllers are different; the resistance parameters of the switch tube are different due to the production process of the switch tube; when the solid power controllers are connected in parallel, the current distribution is unbalanced, so that the power switch tube of the solid power controller which flows more current bears more current stress, thereby reducing the service life of the power switch tube.

The current realization mode of the parallel current-sharing circuit of the solid power controller is to realize active current sharing by connecting a resistor in series in the parallel circuit or connecting a coupling inductor in series in the parallel circuit. For the mode of serially connecting resistors in a parallel circuit, due to the loss characteristic of the resistors, current sharing can be realized through the serially connected resistors, but the loss of the circuit can be increased at the same time, and the current sharing effect is poor. For the mode of serially coupling inductors in a parallel circuit, due to the problems of the size of an inductor magnetic core and the like, multi-path current sharing is difficult to achieve, so that the realization of high power density is limited, and the loss of the circuit can be increased due to serial coupling.

The common solid power controller realizes current sharing by selecting a master-slave mode, one unit is used as a main control unit, and the method controls all the units to realize current sharing by communicating with other units through interconnection lines.

Disclosure of Invention

The technical problem to be solved by the invention is to provide a PWM soft switch impedance adjustment parallel current-sharing solid power controller, realize that low-power consumption and high-power density parallel current sharing are normally conducted through a main power switch tube, and PWM realizes the soft switch conduction and disconnection of an auxiliary power switch tube to realize impedance adjustment, so that the power loss can be effectively reduced, the circuit structure is simplified, and the high-power density solid power controller is easy to realize.

In order to solve the technical problems, the technical scheme adopted by the invention is as follows:

PWM soft switch impedance adjustment connects in parallel current sharing solid power controller, its characterized in that: the system comprises a plurality of groups of solid power controllers, wherein each group of solid power controllers comprises a high-end sampling circuit, an input controller, a microprocessor driving circuit, a parallel power switch tube circuit and a voltage conversion circuit;

the high-end sampling circuit is used for carrying out high-precision differential sampling on the current flowing through the solid power controller;

the input controller and the microprocessor driving circuit are used for inputting a control signal through the input controller to start the microcontroller to work, the microcontroller can receive the input control signal to normally open the main power switch tube and the auxiliary power switch tube, and converts an analog quantity into a digital quantity for sampling current, judges a current sharing state, regulates and controls the output PWM soft switch to drive the auxiliary power switch tube;

the parallel power switch tube circuit is used for realizing the on-off of input voltage, is used for conducting and supplying power to a load, and changes the conducting impedance to realize the parallel current sharing of a plurality of groups of solid power controllers by controlling the conducting state of the secondary power switch tube through the PWM soft switch;

the voltage conversion circuit is used for providing working voltage.

The parallelly connected power switch tube circuit include first power switch tube BQ1 and the second secondary power switch tube BQ2 of being responsible for, first drain electrode of being responsible for power switch tube BQ1 link to each other with input voltage VIN, the drain electrode of the second secondary power switch tube BQ2 link to each other with input voltage VIN, first source electrode of being responsible for power switch tube BQ1 and the source electrode of the second secondary power switch tube BQ2 link to each other and form the output of parallelly connected power switch tube circuit.

The high-end sampling circuit comprises a first sampling resistor Rsamp, a first operational amplifier U1, a second sampling resistor R1, a third sampling resistor R2, a fourth sampling resistor R3 and a fifth sampling resistor Rf;

one end of the first sampling resistor Rsamp is connected with one end of the second sampling resistor R1, the other end of the first sampling resistor Rsamp is connected with one end of the third sampling resistor R2, one end of the first sampling resistor Rsamp is connected with the output end of the parallel power switch tube circuit, the other end of the first sampling resistor Rsamp is connected with one end of the output load Rload, and the other end of the output load Rload is grounded; the other end of the second sampling resistor R1 is in short circuit with the reverse input end of the first operational amplifier U1 and is connected with one end of a fifth sampling resistor Rf, the other end of the fifth sampling resistor Rf is connected with the output end of the first operational amplifier U1, the other end of the third sampling resistor R2 is in short circuit with the homodromous input end of the first operational amplifier U1 and is connected with one end of a fourth sampling resistor R3, the other end of the fourth sampling resistor R3 is connected with a digital power ground SGNG, the voltage input end of the first operational amplifier U1 is connected with VCC, the ground end of the first operational amplifier is connected with the digital power ground SGNG, and the output end of the first operational amplifier U1 is connected with a current sampling port Vs of the microprocessor G1.

The input controller and microprocessor driving circuit comprises an input controller C1, a microprocessor G1, a current sampling port Vs, a driving output port GA1, a driving output port GA2, a first driving resistor R4, a second driving resistor R5, a third driving resistor R6, a first driving triode BC1, a second driving triode BC2, a third driving triode BC3, a fourth driving triode BC4, a fourth driving resistor R7, a fifth driving resistor R8, a sixth driving resistor R9, a fifth driving triode BC5, a sixth driving triode BC6, a seventh driving triode BC7 and an eighth driving triode BC 8;

the output bus port Cc of the input controller C1 is connected with the input bus port Gc of the microprocessor G1, the microcontroller driving output interface GA1 is connected with the base of the first driving triode BC1, the collector of the first driving triode BC1 is short-circuited with one end of the third driving resistor R6 and the base of the second driving triode BC2 and is connected with one end of the first driving resistor R4, the emitter of the first driving triode BC1 is short-circuited with the other end of the third driving resistor R6 and the emitter of the second driving triode BC2 and is connected to the SGNG of a digital power supply ground, the other end of the first driving resistor R4 is short-circuited with one end of the second driving resistor R5 and the collector of the third driving triode BC3 and is connected to the power supply V15, the other end of the second driving resistor R5 is short-circuited with the collector of the second driving triode BC2 and the base of the third driving triode BC3 and is connected with the base of the fourth driving triode BC4, an emitter of a third driving triode BC3 is in short circuit with an emitter of a fourth driving triode BC4 and is connected with a grid of a first main power switch tube BQ1, a collector of the fourth driving triode BC4 is connected with an output end of a parallel power switch tube circuit, a microcontroller driving output interface GA2 is connected with a base of a fifth driving triode BC5, a collector of the fifth driving triode BC5 is in short circuit with one end of a sixth driving resistor R9 and a base of the sixth driving triode BC6 and is connected with one end of a fourth driving resistor R7, an emitter of the fifth driving triode BC5 is in short circuit with the other end of the sixth driving resistor R9 and an emitter of the sixth driving triode BC6 and is connected to a digital power ground SGNG, the other end of the third driving resistor R7 is in short circuit with one end of the fourth driving resistor R8 and a collector of a seventh driving triode BC7 and is connected to a power supply V15, the other end of the fourth driving triode R8 is in short circuit with a base of the sixth driving triode NG 6 and a seventh driving triode BC7 and a collector of the eighth driving triode BC7 The base electrode of the diode BC8 is connected, the emitter electrode of the seventh driving triode BC7 is short-circuited with the emitter electrode of the eighth driving triode BC8 and is connected with the grid electrode of the second secondary power switch tube BQ2, and the collector electrode of the eighth driving triode BC8 is connected with the output end of the parallel power switch tube circuit.

The first driving triode BC1, the second driving triode BC2, the third driving triode BC3, the fifth driving triode BC5, the sixth driving triode BC6 and the seventh driving triode BC7 are all NPN type triodes; the fourth driving transistor BC4 and the eighth driving transistor BC8 are both PNP transistors.

The voltage conversion circuit comprises a first voltage conversion resistor TR1, a first conversion voltage triode TBC1, a first voltage conversion capacitor TC1, a first voltage stabilizing diode ZG1, a digital power supply and a digital power supply ground SGNG;

the digital power supply is in short circuit with one end of a first voltage conversion resistor TR1 and is connected with a collector of a first conversion voltage triode TBC1, the other end of the first conversion resistor TR1 is in short circuit with a base of the first conversion voltage triode TBC1 and is connected with a cathode of a first voltage stabilizing diode ZG1, an anode of the first voltage stabilizing diode ZG1 is in short circuit with one end of a first voltage conversion capacitor TC1 and is connected with a digital power supply ground SGNG, and the other end of the first voltage conversion capacitor TC1 is in short circuit with an emitter of the first conversion voltage triode TBC1 and is connected with an operational amplifier power supply VCC.

The PWM soft switch impedance adjustment parallel current-sharing solid power controller has the following beneficial effects that: the PWM soft switch impedance adjustment parallel current-sharing solid power controller does not need to add redundant elements in a circuit to change impedance so as to avoid unnecessary loss, can realize the wireless current limiting of a plurality of units, and has simple logic of a control program and easy realization. Furthermore, the parallel current-sharing solid power controller is more accurate in waveform control, and can accurately adjust the duty ratio within a set range to change the input impedance to realize parallel current sharing. The impedance of the auxiliary power switch tube of the parallel current-sharing solid power controller is adjusted through PWM, so that the problem that when a plurality of groups of solid power controllers are connected in parallel for power supply, different parasitic parameters are caused due to asymmetrical circuit layout and the like, the parameter characteristic change of a circuit device is influenced by environmental temperature factors, and the parallel current-sharing of a plurality of paths of solid power controllers is caused due to different production processes of the power switch tubes, so that the single-path solid power controller bears larger current for a long time and the service life is shortened is solved. The parallel current-sharing solid power controller realizes the non-connection current limiting, the current limiting value is set through the program of each unit microcontroller, when the sampling detection current is higher than the set current, PWM (pulse-width modulation) output is carried out to adjust impedance, and the current limiting is realized.

Drawings

FIG. 1 is a schematic diagram of a PWM soft switch impedance adjusting parallel current-sharing solid power controller, which realizes that a digital PWM soft switch quickly adjusts the impedance of the solid power controller to realize a non-interconnection line current-limiting high-power density low-loss parallel current-sharing controller circuit.

Fig. 2 is a schematic circuit diagram of a PWM soft switching impedance adjustment parallel current-sharing solid power controller according to the present invention when two circuits are connected in parallel.

Fig. 3 is a schematic circuit diagram of a PWM soft switching impedance adjustment parallel current sharing solid power controller of the present invention implementing two parallel operation states for one time.

Fig. 4 is a schematic circuit diagram of the PWM soft switching impedance adjustment parallel current-sharing solid power controller of the present invention in a two-way parallel operating state.

Fig. 5 is a schematic circuit diagram of a three-way parallel connection working state of the PWM soft switching impedance adjustment parallel current-sharing solid power controller of the present invention.

Fig. 6 is a schematic circuit diagram of a four-time circuit for implementing two-way parallel operation by the PWM soft switching impedance adjustment parallel current-sharing solid power controller of the present invention.

Fig. 7 is a schematic diagram of a flow chart of a microprocessor program implementation in the PWM soft-switching impedance adjustment parallel current-sharing solid-state power controller according to the present invention.

The specification reference numbers: 1. a high-side sampling circuit; 2. an input controller and a microprocessor driving circuit; 3. the power switching tube circuits are connected in parallel; 4. a voltage conversion circuit.

Detailed Description

The invention is further described below with reference to the drawings and specific preferred embodiments.

As shown in fig. 1 and fig. 2, the PWM soft switching impedance adjustment parallel current sharing solid power controller is characterized in that: the system comprises a plurality of groups of solid power controllers, wherein each group of solid power controllers comprises a high-end sampling circuit 1, an input controller and microprocessor driving circuit 2, a parallel power switch tube circuit 3 and a voltage conversion circuit 4;

the high-end sampling circuit 1 is used for carrying out high-precision differential sampling on the current flowing through the solid power controller;

the input controller and microprocessor driving circuit 2 is used for inputting a control signal through the input controller to start the microcontroller to work, the microcontroller can receive the input control signal and normally switch on the main power switch tube and the auxiliary power switch tube, and converts the analog quantity into the digital quantity of the sampling current to judge the current sharing state and regulate and control the output PWM soft switch to drive the auxiliary power switch tube;

the parallel power switch tube circuit 3 is used for realizing the on-off of input voltage, is used for conducting and supplying power to a load, and controls the conducting state of the auxiliary power switch tube through the PWM soft switch to change conducting impedance so as to realize the parallel current sharing of a plurality of groups of solid power controllers;

the voltage conversion circuit 4 is used for providing working voltage.

Further, the parallel power switch tube circuit 3 includes a first main power switch tube BQ1 and a second auxiliary power switch tube BQ2, the drain of the first main power switch tube BQ1 is connected to the input voltage VIN, the drain of the second auxiliary power switch tube BQ2 is connected to the input voltage VIN, and the source of the first main power switch tube BQ1 is connected to the source of the second auxiliary power switch tube BQ2 to form the output end of the parallel power switch tube circuit 3.

Further, the high-side sampling circuit 1 includes a first sampling resistor Rsamp, a first operational amplifier U1, a second sampling resistor R1, a third sampling resistor R2, a fourth sampling resistor R3, and a fifth sampling resistor Rf;

one end of the first sampling resistor Rsamp is connected with one end of the second sampling resistor R1, the other end of the first sampling resistor Rsamp is connected with one end of the third sampling resistor R2, one end of the first sampling resistor Rsamp is connected with the output end of the parallel power switch tube circuit 3, the other end of the first sampling resistor Rsamp is connected with one end of the output load Rload, and the other end of the output load Rload is grounded; the other end of the second sampling resistor R1 is in short circuit with the reverse input end of the first operational amplifier U1 and is connected with one end of a fifth sampling resistor Rf, the other end of the fifth sampling resistor Rf is connected with the output end of the first operational amplifier U1, the other end of the third sampling resistor R2 is in short circuit with the homodromous input end of the first operational amplifier U1 and is connected with one end of a fourth sampling resistor R3, the other end of the fourth sampling resistor R3 is connected with a digital power ground SGNG, the voltage input end of the first operational amplifier U1 is connected with VCC, the ground end of the first operational amplifier is connected with the digital power ground SGNG, and the output end of the first operational amplifier U1 is connected with a current sampling port Vs of the microprocessor G1.

Further, the input controller and microprocessor driving circuit 2 includes an input controller C1, a microprocessor G1, a current sampling port Vs, a driving output port GA1, a driving output port GA2, a first driving resistor R4, a second driving resistor R5, a third driving resistor R6, a first driving transistor BC1, a second driving transistor BC2, a third driving transistor BC3, a fourth driving transistor BC4, a fourth driving resistor R7, a fifth driving resistor R8, a sixth driving resistor R9, a fifth driving transistor BC5, a sixth driving transistor BC6, a seventh driving transistor BC7, and an eighth driving transistor BC 8;

the output bus port Cc of the input controller C1 is connected with the input bus port Gc of the microprocessor G1, the microcontroller driving output interface GA1 is connected with the base of the first driving triode BC1, the collector of the first driving triode BC1 is short-circuited with one end of the third driving resistor R6 and the base of the second driving triode BC2 and is connected with one end of the first driving resistor R4, the emitter of the first driving triode BC1 is short-circuited with the other end of the third driving resistor R6 and the emitter of the second driving triode BC2 and is connected to the SGNG of a digital power supply ground, the other end of the first driving resistor R4 is short-circuited with one end of the second driving resistor R5 and the collector of the third driving triode BC3 and is connected to the power supply V15, the other end of the second driving resistor R5 is short-circuited with the collector of the second driving triode BC2 and the base of the third driving triode BC3 and is connected with the base of the fourth driving triode BC4, an emitter of a third driving triode BC3 is in short circuit with an emitter of a fourth driving triode BC4 and is connected with a gate of a first main power switch tube BQ1, a collector of the fourth driving triode BC4 is connected with an output end of a parallel power switch tube circuit 3, a microcontroller driving output interface GA2 is connected with a base of a fifth driving triode BC5, a collector of the fifth driving triode BC5 is in short circuit with one end of a sixth driving resistor R9 and the base of the sixth driving triode BC6 and is connected with one end of a fourth driving resistor R7, an emitter of the fifth driving triode BC5 is in short circuit with the other end of the sixth driving resistor R9 and the emitter of the sixth driving triode BC6 and is connected to a digital power ground SGNG, the other end of the third driving resistor R7 is in short circuit with one end of the fourth driving resistor R8 and the collector of a seventh driving triode 7 and is connected to a power supply V15, the other end of the fourth driving triode BC8 is in short circuit with the base of the sixth driving triode BC6 and the seventh driving triode BC7 and is connected with the base of an eighth driving triode BC The base electrode of the triode BC8 is connected, the emitter electrode of the seventh driving triode BC7 is in short circuit with the emitter electrode of the eighth driving triode BC8 and is connected with the grid electrode of the second secondary power switch tube BQ2, and the collector electrode of the eighth driving triode BC8 is connected with the output end of the parallel power switch tube circuit 3.

Further, the first driving triode BC1, the second driving triode BC2, the third driving triode BC3, the fifth driving triode BC5, the sixth driving triode BC6 and the seventh driving triode BC7 are all NPN-type triodes; the fourth driving transistor BC4 and the eighth driving transistor BC8 are both PNP transistors.

Further, the voltage conversion circuit 4 includes a first voltage conversion resistor TR1, a first conversion voltage transistor TBC1, a first voltage conversion capacitor TC1, a first zener diode ZG1, a digital power supply and a digital power ground SGNG;

the digital power supply is in short circuit with one end of a first voltage conversion resistor TR1 and is connected with a collector of a first conversion voltage triode TBC1, the other end of the first conversion resistor TR1 is in short circuit with a base of the first conversion voltage triode TBC1 and is connected with a cathode of a first voltage stabilizing diode ZG1, an anode of the first voltage stabilizing diode ZG1 is in short circuit with one end of a first voltage conversion capacitor TC1 and is connected with a digital power supply ground SGNG, and the other end of the first voltage conversion capacitor TC1 is in short circuit with an emitter of the first conversion voltage triode TBC1 and is connected with an operational amplifier power supply VCC.

The PWM soft switching impedance regulation parallel current-sharing solid power controller shown in fig. 2 is divided into the following four cases when two paths of parallel operation are realized:

in the working state 1, as shown in fig. 3, after power is turned on, the 15V power supplies of the first and second solid power controllers are converted into VCC to supply power to the operational amplifier of the sampling circuit, so that the basic circuit works normally. The first solid state power controller SSPC1 inputs a controller signal from the controller C1, the first solid state power controller SSPC1 microprocessor G1 receives the controller signal to output a driving signal to turn on the first main power switch BQ1 and the first solid state power controller SSPC1 and the second sub power switch BQ2 of the first solid state power controller SSPC1, the second solid state controller SSPC2 inputs the controller signal from the controller C1, and the second solid state power controller SSPC2 microprocessor G1 receives the controller signal to output a driving signal to turn on the second solid state power controller SSPC2, the first main power switch BQ1 and the second sub power switch BQ2 of the second solid state power controller SSPC 2. When the first solid state power controller SSPC1 and the second solid state power controller SSPC2 are operating normally. The current value flowing through the first solid state power controller SSPC1 is smaller than the reference current value of parallel current sharing set by the first solid state power controller SSCP1 microprocessor G1, the current value flowing through the second solid state power controller SSPC2 is smaller than the reference current value of parallel current sharing set by the second solid state power controller SSCP2 microprocessor G1, the current value flowing through the first solid state power controller SSPC1 microprocessor G1 is sampled and judged to be smaller than the reference current value of parallel current sharing set by the first solid state power controller SSPC1 microprocessor G1, the first solid state power controller SSPC1 microprocessor G1 outputs a high level from a GA1 port, the first solid state power controller SSPC1 first driving triode BC1 is turned on, the first solid state power controller SSPC1 second driving triode BC2 is turned off, the first solid state power controller SSPC1 third driving triode BC3 is turned on, the first solid state power controller SSPC1 fourth driving triode BC4 is turned off, outputting a high level to turn on the first solid state power controller SSPC1 first power switch tube BQ 1; the microprocessor G1 of the first solid state power controller SSPC1 outputs a high level from the GA2 port, the fifth driving transistor BC5 of the first solid state power controller SSPC1 is turned on, the sixth driving transistor BC6 of the first solid state power controller SSPC1 is turned off, the seventh driving transistor BC7 of the first solid state power controller SSPC1 is turned on, the eighth driving transistor BC8 of the first solid state power controller SSPC1 is turned off, and outputs a high level to turn on the second secondary power switching tube BQ2 of the first solid state power controller SSPC 1; meanwhile, the second solid power controller SSCP2 microprocessor G1 samples and judges that the current value flowing through the second solid power controller SSPC2 is smaller than the set parallel current-sharing reference value of the second solid power controller SSPC2 microprocessor G1, the second solid power controller SSPC2 microprocessor G1 outputs a high level from the GA1 port, the second driving transistor BC1 of the first solid power controller SSPC2 is turned on, the second driving transistor BC2 of the second solid power controller SSPC2 is turned off, the third driving transistor BC3 of the second solid power controller SSPC2 is turned on, the fourth driving transistor BC4 of the second solid power controller SSPC2 is turned off, and the first power switching transistor BQ1 of the second solid power controller SSPC2 is turned on by outputting a high level; the microprocessor G1 of the second solid state power controller SSPC2 outputs a high level from the GA2 port, the fifth driving transistor BC5 of the second solid state power controller SSPC2 is turned on, the sixth driving transistor BC6 of the second solid state power controller SSPC2 is turned off, the seventh driving transistor BC7 of the second solid state power controller SSPC2 is turned on, the eighth driving transistor BC8 of the second solid state power controller SSPC2 is turned off, and the second secondary power switching tube BQ2 of the second solid state power controller SSPC1 is turned on by outputting a high level, so that the circuit operates normally.

In the working state 2, as shown in fig. 4, after power is turned on, the 15V power supplies of the first and second solid power controllers are converted into VCC to supply power to the operational amplifier of the sampling circuit, so that the basic circuit works normally. The first solid state power controller SSPC1 inputs a controller signal from the controller C1, the first solid state power controller SSPC1 microprocessor G1 receives the controller signal to output a driving signal to turn on the first main power switch BQ1 and the first solid state power controller SSPC1 and the second sub power switch BQ2 of the first solid state power controller SSPC1, the second solid state controller SSPC2 inputs the controller signal from the controller C1, and the second solid state power controller SSPC2 microprocessor G1 receives the controller signal to output a driving signal to turn on the second solid state power controller SSPC2, the first main power switch BQ1 and the second sub power switch BQ2 of the second solid state power controller SSPC 2. When the first solid state power controller SSPC1 and the second solid state power controller SSPC2 are operating normally. The current value flowing through the first solid power controller SSPC1 is smaller than the reference current value of the parallel current sharing set by the first solid power controller SSCP1 microprocessor G1, the current flowing through the second solid power controller SSPC2 is larger than the reference current value of the parallel current sharing set and smaller than the maximum current limiting value set by the second solid power controller SSCP2 microprocessor G1, the current flowing through the first solid power controller SSPC1 is sampled and judged by the first solid power controller SSPC1 microprocessor G1 to be smaller than the reference current value of the parallel current sharing set by the first solid power controller SSCP1 microprocessor G1, the first solid power controller SSPC1 microprocessor G1 outputs a high level from a GA1 port, the first solid power controller SSPC1 turns on a first driving transistor BC1, the first solid power controller SSPC1 second driving transistor BC2, the first solid power controller SSPC1 third driving transistor BC3, The fourth driving triode BC4 of the first solid state power controller SSPC1 is turned off, and outputs a high level to turn on the first power switch tube BQ1 of the first solid state power controller SSPC 1; the microprocessor G1 of the first solid state power controller SSPC1 outputs a high level from the GA2 port, the fifth driving transistor BC5 of the first solid state power controller SSPC1 is turned on, the sixth driving transistor BC6 of the first solid state power controller SSPC1 is turned off, the seventh driving transistor BC7 of the first solid state power controller SSPC1 is turned on, the eighth driving transistor BC8 of the first solid state power controller SSPC1 is turned off, and outputs a high level to turn on the second secondary power switching tube BQ2 of the first solid state power controller SSPC 1; meanwhile, the second solid power controller SSCP2 microprocessor G1 samples and judges that the current flowing through the second solid power controller SSPC2 is greater than the reference current set by the second solid power controller SSCP2 microprocessor G1 program and is less than the maximum current-limiting value set by the second solid power controller SSCP2 microprocessor G1, the second solid power controller SSPC2 microprocessor G1 outputs a high level from the GA1 port, the first solid power controller SSPC2 second driving transistor BC1 is turned on, the second solid power controller SSPC2 second driving transistor BC2 is turned off, the second solid power controller SSPC2 third driving transistor BC3 is turned on, the second solid power controller SSPC2 fourth driving transistor BC4 is turned off, and the second solid power controller SSPC2 first power switching tube BQ1 is turned on by outputting a high level; the microprocessor G1 of the second solid state power controller SSPC2 calculates, through a program, that the output PWM from the GA2 output port of the microprocessor G1 of the second solid state power controller SSPC2 controls the second secondary power switching tube BQ2 of the second solid state power controller SSPC2 to perform soft switching, and adjusts the impedance of the second solid state power controller SSPC2, so as to adjust the current flowing through the first solid state power controller SSPC1 to increase, the current flowing through the second solid state power controller SSPC2 to decrease, and finally achieve a current sharing state.

In the working state 3, as shown in fig. 5, after power is turned on, the 15V power supplies of the first and second solid power controllers are converted into VCC to supply power to the operational amplifier of the sampling circuit, so that the basic circuit works normally. The first solid state power controller SSPC1 inputs a controller signal from the controller C1, the first solid state power controller SSPC1 microprocessor G1 receives the controller signal to output a driving signal to turn on the first main power switch BQ1 and the first solid state power controller SSPC1 and the second sub power switch BQ2 of the first solid state power controller SSPC1, the second solid state controller SSPC2 inputs the controller signal from the controller C1, and the second solid state power controller SSPC2 microprocessor G1 receives the controller signal to output a driving signal to turn on the second solid state power controller SSPC2, the first main power switch BQ1 and the second sub power switch BQ2 of the second solid state power controller SSPC 2. When the first solid state power controller SSPC1 and the second solid state power controller SSPC2 are operating normally. The current value flowing through the first solid state power controller SSPC1 is larger than the reference current value of parallel current sharing set by the first solid state power controller SSCP1 microprocessor G1 and smaller than the maximum current-limiting value set by the first solid state power controller SSCP1 microprocessor G1, the current flowing through the second solid state power controller SSPC2 is smaller than the reference current value of parallel current sharing set by the second solid state power controller SSCP2 microprocessor G1, the current flowing through the second solid state power controller SSPC2 of the second solid state power controller SSPC2 microprocessor G1 is sampled and judged to be smaller than the reference current value of parallel current sharing set by the second solid state power controller SSCP2 microprocessor G1, the second solid state power controller SSPC2 microprocessor G1 outputs a high level at a GA 42 port, the second solid state power controller SSPC2 turns on a second driving triode BC1, the second solid state power controller SSPC2 second driving triode BC5 is cut off, the second solid state power controller SSPC2 turns on a third driving triode BC3, The fourth driving triode BC4 of the second solid state power controller SSPC2 is turned off, and outputs a high level to turn on the first power switch tube BQ1 of the second solid state power controller SSPC 2; the microprocessor G1 of the second solid state power controller SSPC2 outputs a high level from the GA2 port, the fifth driving transistor BC5 of the second solid state power controller SSPC2 is turned on, the sixth driving transistor BC6 of the second solid state power controller SSPC2 is turned off, the seventh driving transistor BC7 of the second solid state power controller SSPC2 is turned on, the eighth driving transistor BC8 of the second solid state power controller SSPC2 is turned off, and the second secondary power switching tube BQ2 of the second solid state power controller SSPC1 is turned on by outputting a high level; meanwhile, the first solid power controller SSCP1 microprocessor G1 samples and judges that the current flowing through the first solid power controller SSPC1 is greater than the reference current set by the first solid power controller SSCP1 microprocessor G1 program and is less than the maximum current-limiting value set by the first solid power controller SSCP1 microprocessor G1, the first solid power controller SSPC1 first driving transistor BC1 is turned on, the first solid power controller SSPC1 second driving transistor BC2 is turned off, the first solid power controller SSPC1 third driving transistor BC3 is turned on, the first solid power controller SSPC1 fourth driving transistor BC4 is turned off, and the first solid power controller SSPC1 first power switch BQ1 is turned on at a high level; the microprocessor G1 of the first solid state power controller SSPC1 calculates, through a program, that the output PWM from the GA2 output port of the microprocessor G1 of the first solid state power controller SSPC2 controls the second secondary power switching tube BQ2 of the first solid state power controller SSPC1 to perform soft switching, adjusts the impedance of the first solid state power controller SSPC1, and thus, the current flowing through the second solid state power controller SSPC2 is adjusted to increase, the current flowing through the first solid state power controller SSPC1 is adjusted to decrease, and finally, the current sharing state is achieved.

In the working state 4, as shown in fig. 6, after power is turned on, the 15V power supplies of the first and second solid power controllers are converted into VCC to supply power to the operational amplifier of the sampling circuit, so that the basic circuit works normally. The first solid state power controller SSPC1 inputs a controller signal from the controller C1, the first solid state power controller SSPC1 microprocessor G1 receives the controller signal to output a driving signal to turn on the first main power switch BQ1 and the first solid state power controller SSPC1 and the second sub power switch BQ2 of the first solid state power controller SSPC1, the second solid state controller SSPC2 inputs the controller signal from the controller C1, and the second solid state power controller SSPC2 microprocessor G1 receives the controller signal to output a driving signal to turn on the second solid state power controller SSPC2, the first main power switch BQ1 and the second sub power switch BQ2 of the second solid state power controller SSPC 2. When the first solid state power controller SSPC1 and the second solid state power controller SSPC2 are operating normally. The value of current flowing through the first solid state power controller SSPC1 is greater than the value of the maximum current-limiting current set by the first solid state power controller SSCP1 microprocessor G1, the value of current flowing through the second solid state power controller SSPC2 is greater than the value of the maximum current-limiting current set by the second solid state power controller SSCP2 microprocessor G1, the value of current flowing through the first solid state power controller SSPC1 microprocessor G1 is sampled and judged to be greater than the value of the maximum current-limiting current set by the first solid state power controller SSCP1 microprocessor G1, the first solid state power controller SSPC1 microprocessor G1 outputs a low level from the GA1 port, the first solid state power controller SSPC1 first driving transistor BC1 is turned off, the first solid state power controller SSPC1 second driving transistor BC2 is turned on, the first solid state power controller SSPC1 third driving transistor BC5 is turned off to the first solid state power controller SSPC1 fourth driving transistor BC4, the output low level turns off the first solid state power controller SSPC1 first power switch BQ 1; the microprocessor G1 of the first solid state power controller SSPC1 outputs a low level from the GA2 port, the fifth driving transistor BC5 of the first solid state power controller SSPC1 is turned off, the sixth driving transistor BC6 of the first solid state power controller SSPC1 is turned on, the seventh driving transistor BC7 of the first solid state power controller SSPC1 is turned off, the eighth driving transistor BC8 of the first solid state power controller SSPC1 is turned on, and the second secondary power switching tube BQ2 of the first solid state power controller SSPC1 is turned off by the output low level; meanwhile, the second solid state power controller SSCP2 microprocessor G1 samples and judges that the current flowing through the second solid state power controller SSPC2 is larger than the maximum current-limiting value set by the second solid state power controller SSCP2 microprocessor G1, the second solid state power controller SSPC2 microprocessor G1 outputs a low level from the GA1 port, the first driving transistor BC1 of the second solid state power controller SSPC2 is turned off, the second driving transistor BC2 of the second solid state power controller SSPC2 is turned on, the third driving transistor BC3 of the second solid state power controller SSPC2 is turned off, the fourth driving transistor BC4 of the second solid state power controller SSPC2 is turned on, and the first power switching transistor BQ1 of the second solid state power controller SSPC2 is turned off at a low level; the microprocessor G1 of the second solid state power controller SSPC2 outputs a low level from the GA2 port, the fifth driving transistor BC5 of the second solid state power controller SSPC2 is turned off, the sixth driving transistor BC6 of the second solid state power controller SSPC2 is turned on, the seventh driving transistor BC7 of the second solid state power controller SSPC2 is turned off, the eighth driving transistor BC8 of the second solid state power controller SSPC2 is turned on, and the second secondary power switching tube BQ2 of the first solid state power controller SSPC2 is turned off by the output low level; the function of current limiting without interconnection wires of the first solid state power controller SSPC1 and the second solid state power controller SSPC2 is realized.

When the microprocessor starts to operate, firstly, clock initialization, timer initialization, module initialization and PIG structure initialization are carried out, after initialization is completed, the timer starts to count, the sampling value of the AG module is read after sampling timing is reached, the sampling value is judged, when the electric sampling current value does not exceed the current limiting value, the main power tube is normally on, the auxiliary power tube realizes PWM regulation, the conduction impedance of the solid power controller is changed, and when multiple paths are connected in parallel, the purpose of current sharing is achieved. Further judging whether the current set value is in phase with the sampling value; and if not, returning to sampling and repeating the steps.

The PWM soft switch impedance adjustment parallel current-sharing solid power controller realizes that the digital PWM soft switch rapid adjustment solid power controller impedance realizes the interconnection line-free current-limiting high-power density low-loss parallel current-sharing controller, the current-sharing circuit has the advantages that the impedance is changed without adding redundant elements in the circuit to reduce the circuit loss, a plurality of unit wireless current-limiting can be realized, the control program logic is simple, the realization is easy, the accurate adjustment duty ratio in the setting range changes the input impedance to realize the parallel current sharing, the control waveform is more accurate, the circuit topology is simple, the concrete expression is as follows: few devices, high power density and convenient realization. The PWM soft switch impedance adjustment parallel current-sharing solid power controller is low in cost, more stable and large in output current.

The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may be made by those skilled in the art without departing from the principle of the invention.