阅读说明：本技术 一种mosfet栅极负反馈有源驱动电路 (MOSFET grid negative feedback active driving circuit ) 是由 邵天骢 李志君 郑琼林 黄波 王俊兴 于 2020-10-15 设计创作，主要内容包括：本发明提供了一种MOSFET栅极负反馈有源驱动电路,用于SiC、GaN等宽禁带半导体器件在桥臂电路中的高速驱动。基于负反馈控制原理,在不牺牲开关速度的前提下,自动抑制栅源电压干扰,实现高速开关下的栅压稳定。所述电路包括：驱动推挽电路、驱动电阻、辅助电容和辅助MOSFET。其中驱动推挽电路为普通的MOSFET驱动芯片,驱动电阻为电阻R,辅助电容为电容C,辅助MOSFET为P沟道MOSFET Q_p。该MOSFET栅极负反馈有源驱动电路结构简单,易于实现,可在不牺牲SiC、GaN等宽禁带半导体器件开关速度的前提下,自动抑制栅源电压干扰,实现高速开关下的栅压稳定。(The invention provides a MOSFET grid negative feedback active driving circuit which is used for high-speed driving of wide bandgap semiconductor devices such as SiC, GaN and the like in a bridge arm circuit. Based on a negative feedback control principle, under the premise of not sacrificing the switching speed, the grid-source voltage interference is automatically inhibited, and the grid voltage stability under the high-speed switching is realized. The circuit comprises: the drive push-pull circuit, the drive resistor, the auxiliary capacitor and the auxiliary MOSFET are connected in series. The drive push-pull circuit is a common MOSFET drive chip, the drive resistor is a resistor R, the auxiliary capacitor is a capacitor C, and the auxiliary MOSFET is a P-channel MOSFET Q p . The MOSFET grid negative feedback active driving circuit has a simple structure, is easy to realize, can automatically inhibit grid source voltage interference on the premise of not sacrificing the switching speed of wide bandgap semiconductor devices such as SiC and GaN, and realizes the grid voltage stability under high-speed switching.)

1. A MOSFET grid negative feedback active driving circuit is used for connecting a driving signal to control the on and off of a controlled MOSFET, and is characterized in that: the method comprises the following steps:

an auxiliary MOSFET, wherein the auxiliary MOSFET is a P-channel MOSFET, the source of the auxiliary MOSFET is connected with the grid of the controlled MOSFET and is used for constructing a negative feedback regulation mechanism, and the drain of the auxiliary MOSFET is connected to a driving voltage; the driving voltage is the voltage of the driving chip after being filtered by the passive network.

2. A MOSFET gate degeneration active driving circuit as claimed in claim 1, wherein: further comprising: a first node, a second node, and a third node;

the driving push-pull circuit is used for providing driving current to drive the controlled MOSFET, the driving signal is connected to the driving push-pull circuit, and the driving push-pull circuit is connected with the third node in series;

one end of the driving resistor R is connected with the driving push-pull circuit in series, the other end of the driving resistor R is connected with a first node and used for limiting the charging and discharging current of the driving push-pull circuit to the auxiliary capacitor C, and the voltage difference between the first node and the source electrode of the controlled MOSFET is driving voltage;

one end of the auxiliary capacitor C is connected with the first node, the other end of the auxiliary capacitor C is connected with the source electrode of the controlled MOSFET through a third node, and the auxiliary capacitor C and the driving resistor R form a passive network and are used for adjusting the switching speed of the controlled MOSFET;

and the drain electrode and the grid electrode of the auxiliary MOSFET are connected with the driving resistor R in series through a second node, and the source electrode of the auxiliary MOSFET is connected with the grid electrode of the controlled MOSFET and used for constructing a negative feedback regulation mechanism.

3. A MOSFET gate degeneration active driving circuit as claimed in claim 1, wherein: the drive push-pull circuit comprises a MOSFET drive chip and an on bias voltage V_CCAnd turn-off bias voltage V_EE(ii) a The positive port of the output power supply of the MOSFET driving chip is connected to a turn-on bias voltage V_CCThe negative port of the output power supply of the MOSFET driving chip is connected to a turn-off bias voltage V_EEThe drive output port of the MOSFET drive chip is connected to one end of the drive resistor R, and the drive input port of the drive chip is connected to a drive signal; the turn-on bias voltage V_CCAnd off bias voltage V_EEAre all connected to the third node; in terms of driving capability, the output current of the driving chip of the MOSFET should not be less than (V)_CC-V_EE)/R_gWherein R is_gIs the gate parasitic resistance of the controlled MOSFET.

4. A MOSFET gate degeneration active driving circuit as claimed in claim 1, wherein: the drain-source breakdown voltage of the auxiliary MOSFET is not less than V_CC-V_EEAnd the continuous drain current is not less than (V)_CC-V_EE)/R_g。

Technical Field

The invention relates to a MOSFET grid negative feedback active driving circuit.

Background

The high switching speed of the MOSFET based on silicon carbide (SiC), gallium nitride (GaN) and other wide bandgap materials enables the converter to obtain the advantages of efficiency and power density, and is an important technical guarantee in the field of high-performance power electronic conversion. However, higher switching speeds cause more interference, and become one of the major bottlenecks that limit SiC/GaN MOSFETs to fully exhibit their fast characteristics.

Scholars at home and abroad research the grid voltage interference suppression method, and the method can be roughly classified into a passive suppression method and an active suppression method.

The passive method adopts a passive element to inhibit the parasitic oscillation of the grid, and mainly comprises the following steps: an auxiliary capacitor is added between the gate and the source, a negative turn-off voltage is adopted for gate driving, and the like, see documents [1-3 ]. Although the gate interference is suppressed by adding the auxiliary capacitance between the gate and the source to share the interference current from the miller capacitance and avoid the interference current from flowing into the gate, the additional auxiliary capacitance slows down the switching speed and increases the switching loss, resulting in poor switching performance. The grid drive adopts a negative turn-off voltage method, and the negative bias of the grid voltage is increased, so that the false conduction caused by the interference and the triggering of the grid is effectively prevented, but the negative stress of the grid voltage is deteriorated.

In order to achieve a better MOSFET grid voltage interference suppression effect, researchers introduce grid feedforward control and research various active suppression technologies. Document [4] introduces an auxiliary circuit composed of four switching tubes, forms a Multi-level Active Gate Driver (Multi-level AGD), detects an interference signal of a device through an fpga (field programmable Gate array) controller, predicts an oscillation trend based on a device parameter model to avoid interference influence, displays an actual measurement waveform in the document, and can effectively suppress Gate interference when dv/dt is 5V/ns. However, considering that the switching time and the gate disturbance oscillation period of the SiC/GaN MOSFET are as short as tens of nanoseconds, the propagation delay of the sampling may be comparable to or even longer than the switching time and the oscillation period, and the propagation delay problem of the detection signal is a challenge. The literature [2,3,5] studies Active Miller Clamp (AMC), which works on the principle of actively enabling an auxiliary transistor between the gate and source, clamping the gate directly to a negative bias voltage, after detecting that the gate voltage is above the clamping threshold. However, the immunity of the detection signal to interference during fast switching transients is a challenge, because higher dv/dt induces higher frequency gate-interference oscillations, and the detected signal is prone to large deviations due to interference from common source inductance, detection loop stray inductance. The literature [2] research shows that the AMC technology can obviously improve the grid interference oscillation when the dv/dt is lower than 20V/ns, but has limited mitigation effect on the grid interference oscillation, particularly negative oscillation, under the condition of higher dv/dt. Document [6] proposes two miller capacitance coupling oscillation suppression methods: firstly, the Gate Impedance adjustment technology (GIR) predicts the Gate oscillation trend according to the driving signal rule by an auxiliary circuit composed of a switch tube and a capacitor, controls the auxiliary switch tube through a logic signal generator, and reduces the Gate Impedance in the switching transient process, thereby clamping the Gate voltage and inhibiting the Gate interference, and the dv/dt can reach 24.4V/ns; secondly, a Gate Voltage Control (GVC) technique includes predicting a Gate oscillation trend according to a driving signal rule by an auxiliary circuit including two switching tubes and a diode, controlling the auxiliary switching tubes by a logic signal generator, and pre-charging a Gate source capacitor before a switching transient state so as to counter-balance the interference oscillation trend, wherein dv/dt can reach 24.9V/ns. In subsequent research, document [7] proposes an Intelligent Gate Driver (IGD), which is an auxiliary circuit composed of two switching tubes and two diodes, predicts the Gate oscillation trend according to the driving signal rule under different switching transients, controls the auxiliary switching tubes through a logic signal generator, and suppresses Gate interference by changing the Gate voltage and Gate impedance of a power device. The measured waveform shows that the IGD technology can effectively inhibit the gate interference when dv/dt is 40V/ns. However, under different working conditions, the voltage and the current borne by the MOSFET are different, and the amplitude and the frequency of the gate disturbance oscillation are different. When the operation condition of the MOSFET changes, the grid interference oscillation trend is predicted according to a fixed rule to be easy to generate over-compensation or under-compensation, and the feedforward control precision is influenced. The method for suppressing interference by utilizing feedforward control grid voltage generally predicts the oscillation trend according to the driving signal rule or according to the MOSFET parameter model by detecting the grid voltage or an interference source, and takes measures in advance to avoid parasitic oscillation. However, the high-speed switching interference causes the gate parasitic oscillation to have high-frequency characteristics, so that the detection signal is susceptible to interference and has obvious errors; the oscillation trend is influenced by the working environment of the MOSFET, is difficult to accurately predict, and easily causes inaccuracy of feedforward control.

In summary, the acceptable voltage change rate (dv/dt) of the MOSFET under the typical gate feedforward control is limited due to the high frequency characteristic of the gate disturbance and the feedforward control accuracy limitation, so that it is still a very challenging task to actively suppress the gate parasitic oscillation by controlling the gate voltage. The gate disturb phenomenon is more significant, and becomes one of the major bottlenecks in fully exploiting the fast characteristics of SiC/GaN MOSFETs.

The references are as follows:

[1]ZENG Z,LI X.Comparative Study on Multiple Degrees ofFreedom of Gate Drivers for Transient Behavior Regulation of SiC MOSFET[J].IEEE Transactions on Power Electronics,2018,33(10):8754-8763.

[2]STMicroelectronics AN-5355.Mitigation Technique of the SiC MOSFET Gate Voltage Glitches with Miller Clamp[EB/OL].Available online at https://www.st.com(accessed on 18March,2020).

[3]Avago Technologies AN-5314.Active Miller Clamp[EB/OL].Available online at http://www.avagotech.com(accessed on 18March,2020).

[4]ZHAO S,DEARIEN A,WU Y,et al.Adaptive Multi-Level Active Gate Drivers for SiC Power Devices[J].IEEE Transactions on Power Electronics,2020,35(2):1882-1898.

[5]CHEN Z,DANILOVIC M,BOROYEVICH D,et al.Modularized Design Consideration of a General-Purpose,High-Speed Phase-Leg PEBB Based on SiC MOSFETs:Proceedings ofthe 201114th European Conference on Power Electronics andApplications[C].Birmingham,UK:30Aug.-1Sept.2011.

[6]ZHANG Z,WANG F,TOLBERT L M,et al.Active Gate Driver for Crosstalk Suppression of SiC Devices in a Phase-Leg Configuration[J].IEEE Transactions on Power Electronics,2014,29(4):1986-1997.

[7]ZHANG Z,DIX J,WANG F,et al.Intelligent Gate Drive for Fast Switching and Crosstalk Suppression of SiC Devices[J].IEEE Transactions on Power Electronics,2017,32(12):9319-9332.

disclosure of Invention

The present invention provides a MOSFET gate negative feedback active driving circuit, which can automatically suppress gate-source voltage interference without sacrificing MOSFET switching speed and increasing circuit complexity.

The invention is realized by the following steps: a MOSFET grid negative feedback active driving circuit for connecting a driving signal to control the on and off of a controlled MOSFET comprises:

an auxiliary MOSFET, wherein the auxiliary MOSFET is a P-channel MOSFET, the source of the auxiliary MOSFET is connected with the grid of the controlled MOSFET and is used for constructing a negative feedback regulation mechanism, and the drain of the auxiliary MOSFET is connected to a driving voltage; the driving voltage is the voltage of the driving chip after being filtered by the passive network.

Further, still include: a first node, a second node, and a third node;

the driving push-pull circuit is used for providing driving current to drive the controlled MOSFET, the driving signal is connected to the driving push-pull circuit, and the driving push-pull circuit is connected with the third node in series;

one end of the driving resistor R is connected with the driving push-pull circuit in series, the other end of the driving resistor R is connected with a first node and used for limiting the charging and discharging current of the driving push-pull circuit to the auxiliary capacitor C, and the voltage difference between the first node and the source electrode of the controlled MOSFET is driving voltage;

one end of the auxiliary capacitor C is connected with the first node, the other end of the auxiliary capacitor C is connected with the source electrode of the controlled MOSFET through a third node, and the auxiliary capacitor C and the driving resistor R form a passive network and are used for adjusting the switching speed of the controlled MOSFET;

and the drain electrode and the grid electrode of the auxiliary MOSFET are connected with the driving resistor R in series through a second node, and the source electrode of the auxiliary MOSFET is connected with the grid electrode of the controlled MOSFET and used for constructing a negative feedback regulation mechanism.

Furthermore, the driving push-pull circuit comprises a MOSFET driving chip and an on bias voltage V_CCAnd turn-off bias voltage V_EE(ii) a The positive port of the output power supply of the MOSFET driving chip is connected to a turn-on bias voltage V_CCThe negative port of the output power supply of the MOSFET driving chip is connected to a turn-off bias voltage V_EEThe drive output port of the MOSFET drive chip is connected to one end of the drive resistor R, and the drive input port of the drive chip is connected to a drive signal; the turn-on bias voltage V_CCAnd off bias voltage V_EEAre all connected to the third node; in terms of driving capability, the output current of the driving chip of the MOSFET should not be less than (V)_CC-V_EE)/R_gWherein R is_gIs the gate parasitic resistance of the controlled MOSFET.

Further, the drain-source breakdown voltage of the auxiliary MOSFET is not less than V_CC-V_EEAnd the continuous drain current is not less than (V)_CC-V_EE)/R_g。

The invention has the advantages that: the MOSFET grid negative feedback active driving circuit is simple in structure, easy to realize, independent of an additional circuit and capable of being realized only by adopting a driving chip, a driving resistor, an auxiliary MOSFET and an auxiliary capacitor of a common MOSFET. Functionally, the MOSFET grid negative feedback active driving circuit can automatically inhibit grid source voltage interference on the premise of not sacrificing the switching speed of the MOSFET, and realizes grid voltage stability under high-speed switching. In the subsequent example, compared with the traditional passive suppression scheme, the MOSFET grid negative feedback active driving circuit can realize larger-amplitude grid-source voltage oscillation suppression, and the switching speed is not increased to a certain extent at the expense of the switching speed.

Drawings

The invention will be further described with reference to the following examples with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of a MOSFET gate degeneration active driving circuit according to the present invention;

FIG. 2 is a control block diagram of a MOSFET gate degeneration active drive circuit according to the present invention;

FIG. 3 shows a gate degeneration active drive in a bridge arm configuration according to an embodiment of the invention;

FIG. 4a is a gate degeneration actively driven Q according to an embodiment of the present invention_HPrinciple waveforms of the turn-on process;

FIG. 4b is a gate degeneration actively driven Q according to an embodiment of the present invention_HPrinciple waveforms of the turn-off process;

FIG. 5a is a circuit diagram of an experiment without any suppression measure compared to a MOSFET gate degeneration active driver circuit according to an embodiment of the present invention;

FIG. 5b is a circuit diagram of an experiment comparing a MOSFET gate degeneration active driving circuit with passive suppression measures according to an embodiment of the present invention;

FIG. 5c is a circuit diagram of an experimental comparison of a MOSFET gate degeneration active driver circuit using degeneration active driving, according to an embodiment of the present invention;

FIG. 6a is an experimental waveform for one switching cycle in a conventional drive circuit with no interference rejection according to an embodiment of the present invention;

FIG. 6b is a view of v in a conventional drive circuit with interference-free suppression according to an embodiment of the present invention_DS2Rising edge amplified experimental waveforms;

FIG. 6c is a view showing v in a conventional driving circuit for interference-free suppression according to an embodiment of the present invention_DS2A falling edge amplified experimental waveform;

FIG. 7a is an experimental waveform for one switching cycle in a driving circuit employing a passive quenching method according to an embodiment of the present invention;

FIG. 7b is a block diagram of an embodiment of the present inventionV in driving circuit using passive suppression method_DS2Rising edge amplified experimental waveforms;

FIG. 7c shows a schematic diagram of a driving circuit employing a passive suppression method according to an embodiment of the present invention_DS2A falling edge amplified experimental waveform;

FIG. 8a is an experimental waveform during one switching cycle in an active drive circuit using MOSFET gate degeneration in accordance with an embodiment of the present invention;

FIG. 8b is a graph of v in an active driving circuit using MOSFET gate degeneration in accordance with an embodiment of the present invention_DS2Rising edge amplified experimental waveforms;

FIG. 8c shows a schematic diagram of a circuit for driving an active device using MOSFET gate degeneration in accordance with an embodiment of the present invention_DS2Falling edge amplified experimental waveform.

Detailed Description

One embodiment of the present invention:

as shown in FIG. 1, the MOSFET Q is driven by the MOSFET grid negative feedback active driving circuit_N. If controlled MOSFET Q_NFor the active tube in the bridge arm circuit, at the starting moment of conduction, the PWM signal S is changed from low level to high level, and the output end of the driving chip is connected to a conduction bias voltage V_CCThe driving chip charges the auxiliary capacitor C through the driving resistor R, and the driving voltage v_GSIncrease gradually from V_EEUp to V_CC. At the initial moment, due to the controlled MOSFET Q_NOf the gate-source voltage v_GSIs still at the off bias voltage V_EEThis results in D_PIs higher than S_PAfter the potential difference exceeds the threshold voltage, Q_PThe parasitic body diode is conducted in the forward direction, and the driving chip passes through Q_PParasitic body diode is Q_NInput capacitance C_issCharging, Q_NOf the gate-source voltage v_GSIncreasing; in case v is present_GSIs too large so that S_PIs higher than D_PWhen the potential difference reaches Q_PWhen the threshold voltage is turned on, Q_PChannel conduction of Q_NInput capacitance C_issDischarge, v_GSIt will decrease accordingly; due to the existence of the negative feedback mechanism, the conduction processIn, Q_NOf the gate-source voltage v_GSWill closely follow the drive voltage v_GSChange. Similarly, at the start of the turn-off, the PWM signal S changes from high level to low level, and the output terminal of the driver chip is connected to the turn-off bias voltage V_EEThe driving chip discharges the auxiliary capacitor C and drives the voltage v_GSDecrease gradually from V_CCDown to V_EE. At the initial moment, due to the controlled MOSFET Q_NOf the gate-source voltage v_GSIs still at the conducting bias voltage V_CCThis makes S_PIs higher than D_PAfter the potential difference exceeds the threshold voltage, Q_PThe channel is conducted and the chip is driven to pass through Q_PThe channel of (A) is Q_NInput capacitance C_issDischarge, Q_NOf the gate-source voltage v_GSDecrease; in case v is present_GSToo small so that D_PIs higher than S_PWhen the potential difference is higher than the threshold voltage, Q_PThe parasitic body diode is turned on to be Q_NInput capacitance C_issCharging, v_GSIt will increase accordingly; due to the existence of the negative feedback mechanism, Q is generated during the turn-off process_NOf the gate-source voltage v_GSWill closely follow the drive voltage v_GSChange.

If controlled MOSFET Q_NAnd a passive tube in the bridge arm circuit needs to be turned off and clamped to resist external interference. At this time, the PWM signal S is always low level, and the output voltage of the gate driver chip is the off-bias voltage V_EEDriving voltage v_GS*＝V_EE。Q_NOf the gate-source voltage v_GSEqual to the turn-off bias voltage V in steady state_EE(ii) a When Q is_NOf the gate-source voltage v_GSWhen the interference fluctuates, a negative feedback mechanism is triggered. If Q_NOf the gate-source voltage v_GSThe interference rises when S_PIs higher than D_PAnd when the potential difference exceeds a threshold voltage, Q_PThe channel is conducted and the chip is driven to pass through Q_PThe channel of (A) is Q_NInput capacitance C_issDischarge, Q_NOf the gate-source voltage v_GSDecrease; if Q_NOf the gate-source voltage v_GSReduced interference when D_PElectricity (D) fromIs higher than S_PAnd when the potential difference exceeds a threshold voltage, Q_PThe parasitic body diode is turned on to be Q_NInput capacitance C_issCharging, v_GSIt will increase accordingly. Due to the existence of this negative feedback mechanism, Q_NOf the gate-source voltage v_GSWhen fluctuating due to interference, Q_NOf the gate-source voltage v_GSWill be clamped tightly to the driving voltage v_GS*＝V_EE。

As shown in fig. 2, is a negative feedback regulation mechanism unique to the circuit of the present invention. The driving circuit shields the interference of pulse voltage and pulse current through the mechanism, and realizes the grid voltage stability under the high-speed switch. Drive voltage v_GSAnd the reference signal is input into a grid negative feedback control loop as a grid source electrode reference signal. Reference signal and gate-source voltage v of controlled MOSFET_GSDifference, transconductance gain g through the auxiliary MOSFET_mControlling the input capacitance C of the controlled MOSFET_issInternal resistance of grid R_gTogether forming a controlled object. Considering the external interference n(s) of pulse voltage and pulse current, the displacement current is generated by the Miller capacitor to the C of the controlled MOSFET_issCharging and discharging the disturb gate source voltage. If v is_GSIncreased (or decreased), then compared with the reference value v_GSThe difference is increased, and the input capacitor C is adjusted after the transconductance gain of the driving tube_issDischarging (or charging), the gate-source voltage v of the controlled MOSFET_GSAnd recovering to be stable. The goal of gate degeneration control is to let the gate-source voltage v of the controlled MOSFET_GSTracking drive signal v_GSAnd shielding the interference n(s) of the pulse voltage and the pulse current. Under the premise of not sacrificing the switching speed, the grid-source voltage interference is automatically inhibited, and the grid voltage stability under the high-speed switching is realized.

As shown in fig. 3, this embodiment shows a negative feedback active drive circuit for a bridge arm configuration. Wherein, the upper tube Q of the bridge arm_HAnd bridge arm lower tube Q_LAre all represented in the form of junction capacitance, so that a user can conveniently understand the working principle of the MOSFET grid negative feedback active driving circuit. In FIG. 3, to distinguish the upper pipe from the lower pipe, the corner marks "1" and "2" are added, respectively, or the corner marks are added, respectively"L" and "H". R₁And R₂Representing the driving resistances of the upper and lower tubes, respectively, C₁And C₂Auxiliary capacitors, Q, representing upper and lower tubes, respectively_p1And Q_p2Representing the auxiliary MOSFETs of the upper and lower tubes, respectively. Bridge arm upper pipe Q_HAs active tube, in pulse control signal S₁Under the control of (3), switching on and off; bridge arm lower tube Q_LAs a passive tube, its control signal S₂Always at low level, Q_LThe channel is turned off and freewheels only with its parasitic body diode.

Miller capacitor C of MOSFET_gdHAnd C_gdLDecreases as the drain-source voltage increases. In order to facilitate the disclosure of the negative feedback active driving circuit principle, a piecewise linearized approximate curve is introduced in the following embodiments, fitting the actual curve. When the drain-source voltage is greater than the gate-source voltage, C_gdHAnd C_gdLHas a value of C_gd1(ii) a When the drain-source voltage is less than the gate-source voltage, C_gdHAnd C_gdLHas a value of C_gd2. The output current of the middle point of the bridge arm is approximately constant in one switching period, so that a constant current source is represented as I_L. Simultaneously, the DC voltage on the bridge arm is recorded as V_DC。

As shown in FIGS. 4a and 4b, Q of the circuit of FIG. 3 is shown_HTheoretical waveforms of the dynamic processes of switching on and off, respectively, as S₁Time point of change from low level to high level, S₁The moment of changing from high level to low level is the initial moment, and there are 4 main modes in the two dynamic processes respectively, and the details are as follows:

1. as shown in FIG. 4a, Q_HOpening process

Open mode 1: turn-on delay period t_d(on). Time 0, S₁Changing from low level to high level, driving the chip to pass through R₁As an auxiliary capacitor C₁Charging, drive voltage v_GS1Increase gradually from V_EE1Up to V_CC1. Due to the negative feedback mechanism, Q_HOf the gate-source voltage v_GS1V follow_GS1Change, also gradually increase, however, the active drive is type I due to the negative feedback of the gate as described in fig. 1System for a ramp signal v_GS1The tracking has certain error, but the tracking error does not influence the normal work of the driving circuit because the open loop amplification factor is large enough. In this mode, v is due to_GS1Yet less than threshold voltage V_GS,th，Q_HIs in an off state, i_D1＝0。v_DS1At V_DCUnchanged when v is_GS1Rises to V_GS,thWhen this mode ends.

Open mode 2: current rise phase t_ri。v_GS1From threshold voltage V_GS,thInitially, rise to V_GS,ILIndicates that the channel current can be maintained at I_LV is_GS1The value is obtained. v. of_DS1At V_DCAnd is not changed. Q_HCurrent i of_D1Starting from 0 and rising to I_L. In this process, the current i is flowing through the passive tube_D2Decrease of Q_LOf the gate-source voltage v_GS2Producing a slight rise, but not enough to trigger Q_P2And conducting. In ignoring Q_LUnder the condition of reverse recovery of a parasitic body diode, the mode rises to I when the current rises_LThe time of (1) is over.

Open mode 3: voltage drop phase t_fv1. Under the condition of a common driving circuit, the voltage enters the Miller platform, and the grid source voltage is maintained at V_gs,ILAnd is not changed. However, with an actively driven MOSFET with gate degeneration, Q is due to the degeneration mechanism described in the embodiment of fig. 1_HOf the gate-source voltage v_GS1Still following v_GS1Rise together and do not remain at V_gs,ILAnd is not changed. In this mode, v_DS1From V_DCBegins to fall, since the drain-source voltage is still greater than the gate-source voltage, C_gdHThe value of (C) is still relatively small_gd1) The phase v_DS1The descent speed is relatively fast. In this mode, Q_LIs of the drain-source voltage v_DS2Rises rapidly, thus Q_LOf the gate-source voltage v_GS2A relatively large rise is generated; due to the presence of the negative feedback mechanism described in the embodiment of FIG. 1, when S is_P2Is higher than D_P2And the potential difference exceeds a threshold voltage V_thWhen is, Q_P2Channel conductionThe driving chip passes Q_P2The channel of (A) is Q_LInput capacitance C_issLDischarge, Q_LOf the gate-source voltage v_GS2Reduction, interference suppression, v_GS2Go back to V_EE2. When v is_DS1Down to and v_GS1When numerically equal, the modality ends.

Open mode 4: voltage drop phase t_fv2. Due to the presence of the negative feedback mechanism described in the embodiment of FIG. 1, Q_HOf the gate-source voltage v_GS1Still following v_GS1Rise together and do not remain at V_gs,ILAnd is not changed. v. of_DS1Continue to drop because the drain-source voltage is less than the gate-source voltage, C_gdHIs relatively large (C)_gd2) The phase v_DS1The descent speed is relatively slow. When v is_DS1Down to V_DS(on)When this mode ends.

After mode 4 is turned on, Q is due to the presence of the negative feedback mechanism described above_HOf the gate-source voltage v_GS1Still following v_GS1Rise together to a high level V_CC1And finally completing the opening process.

2. As shown in FIG. 4b, Q_HShutdown procedure

Off mode 1: off delay phase t_d(off). Time 0, S₁Changing from high level to high level, driving the chip to pass through R₁As an auxiliary capacitor C₁Discharge, drive voltage v_GS1Decrease gradually from V_CC1Down to V_EE1. Due to the negative feedback mechanism in the embodiment of FIG. 1, Q_HOf the gate-source voltage v_GS1V follow_GS1Change, also decrease gradually, however, the active drive is a type I system due to the negative feedback of the gate shown in fig. 1, which is for the ramp signal v_GS1The tracking has certain error, but the tracking error does not influence the normal work of the driving circuit because the open loop amplification factor is large enough. Because the grid source voltage is still larger than the threshold voltage V_GS,th，Q_HIs in a conducting state, so that there is still i_D1＝I_L，v_DS1Is still at V_DS(on)And is not changed. When v is_GS1Down to V_GS,ILWhen it is in this modeAnd (6) ending.

Off mode 2: voltage rising phase t_rv1. Under the condition of a common driving circuit, the voltage enters the Miller platform, and the grid source voltage is maintained at V_GS,ILAnd is not changed. However, with an actively driven MOSFET with gate degeneration, Q is due to the degeneration mechanism described in the embodiment of fig. 1_HOf the gate-source voltage v_GS1Still following v_GS1Decrease together without maintaining at V_GS,ILDoes not change, but continues to fall. In this mode, v_DS1From V_DS(on)And starts to rise. Since the drain-source voltage is still less than the gate-source voltage, C_gdHThe value of (C) is still relatively large_gd2) The phase v_DS1The rising speed is relatively slow. When v is_DS1Rises to and v_GS1When numerically equal, the modality ends.

Off mode 3: voltage rising phase t_rv2. Due to the presence of the negative feedback mechanism shown in FIG. 1, Q_HOf the gate-source voltage v_GS1Still following v_GS1Decrease together. In this mode, v_DS1And the rise is continued. Since the drain-source voltage is greater than the gate-source voltage, C_gdHIs relatively small (C)_gd1) The phase v_DS1The rising speed is relatively fast. Q_LIs of the drain-source voltage v_DS2Falls rapidly, thus Q_LOf the gate-source voltage v_GS2A larger drop is generated; due to the existence of the negative feedback mechanism shown in FIG. 1, when D is present_P2Is higher than S_P2And the potential difference exceeds a threshold voltage V_thWhen is, Q_P2The parasitic body diode is conducted to drive the chip to pass through Q_P2The parasitic body diode of (2) is Q_LInput capacitance C_issLCharging, Q_LOf the gate-source voltage v_GS2Increase, interference suppression, v_GS2Go back to V_EE2. When v is_DS1Up to V_DCWhen this mode ends.

Off-mode 4: current reduction phase t_fi. Due to the presence of the negative feedback mechanism shown in FIG. 1, Q_HOf the gate-source voltage v_GS1Still following v_GS1Decrease all together until a threshold voltage V is reached_GS,th. In the processDue to the passive tube current i_D2Is elevated, Q_LOf the gate-source voltage v_GS2Producing a slight drop, but not enough to trigger Q_P2The parasitic body diode is turned on. In this mode, v_DS1At V_DCInvariable, Q_HCurrent i of_D1From I_LThe start drops to 0 and the modality ends.

After mode 4 is turned off, Q is due to the presence of a negative feedback mechanism as shown in the embodiment of FIG. 1_HOf the gate-source voltage v_GS1Still following v_GS1Decrease together from threshold voltage V_GS,thUntil it is reduced to a low level V_EE1And finally completing the turn-off process.

The design principle of the grid negative feedback active driving circuit parameter is described as follows.

(1) Selection principle of controlled MOSFET

When the grid negative feedback active drive is adopted, the controlled MOSFET is determined to be used as a switching device for main power electric energy conversion according to the working environment of the power conversion device. The method is consistent with the principle of power switch device model selection of the power conversion device in the traditional driving mode, generally under the rated working state of the power conversion device, the maximum working voltage and the maximum working current of the obtained device are calculated, the MOSFET is ensured to be in a safe working area, and the model of the MOSFET is determined by referring to the maximum drain-source voltage and the maximum drain-source current allowed by the device. In this embodiment, a device with a higher commercialization degree and a more typical high-power conversion field is selected as the controlled MOSFET to demonstrate and verify the technical feasibility of the proposed method. The MOSFET has a maximum drain-source voltage of 1200V and a maximum drain current of 56A, and is of the type IMZ120R030M 1H.

(2) Driver chip type selection and peripheral circuit design principle thereof

Since the threshold voltage of the controlled MOSFET is low (about 2-4V), although the gate negative feedback active driving circuit has the functions of stabilizing the gate-source voltage and shielding the influence of pulse voltage and pulse current interference, the instability problem of the gate is not completely eradicated. Therefore, the negative pressure for driving is necessary to be cut off. Recommended turn-on bias voltage V_CC18-22V, offOff bias voltage V_EE-2.5 to-5V. The golden anode drive power module QA01C series (or similar substitute products) can be used to achieve turning on and off the bias voltage. In view of the above, the design of this embodiment example uses the turn-on voltage V_CC20V, turn-off voltage V_EE＝-5V。

The common mode transient immunity CMTI is recommended to be more than or equal to 100V/ns (within the full temperature range). In terms of driving capability, the chip output current should not be less than (V)_CC-V_EE)/R_gWherein R is_gIs the gate parasitic resistance of the controlled MOSFET. For example, the in-gate resistance R of the selected controlled MOSFET (IMZ120R030M1H) described above_gThe chip output current should not be less than 8.3A because of 3 Ω, and the output current can reach 14A when the driving chip 1ED3124MU12H is used in this embodiment.

(3) Auxiliary MOSFET model selection principle

The auxiliary MOSFET needs to be implemented by selecting a device with channel characteristics which are dual to those of the controlled MOSFET, and in general, the controlled MOSFET is an N-channel MOSFET, so that the auxiliary MOSFET should be a P-channel MOSFET. Meanwhile, in order to ensure the control precision, the transconductance gain of the auxiliary MOSFET is far larger than 1 (S). In addition, because the auxiliary MOSFET needs to bear certain voltage and current in the turn-on and turn-off processes of the controlled MOSFET, the auxiliary MOSFET needs to be switched on according to the turn-on bias voltage V designed by the driving chip to ensure the safe operation of the auxiliary MOSFET_CCOff bias voltage V_EEAnd the grid characteristics of the controlled MOSFET, the voltage and current levels of the auxiliary MOSFET are selected, and the recommended drain-source breakdown voltage is not less than V_CC-V_EEAnd sustainable continuous drain current not less than (V)_CC-V_EE)/R_g. Based on the above analysis, the present embodiment uses FDS9435A as the P-channel auxiliary MOSFET, which has a drain-source breakdown voltage of 30(V), a sustainable continuous drain current of 25(a), and a transconductance gain of 10 (S).

(4) Design principle of auxiliary capacitor and driving resistor

The auxiliary capacitor and the driving resistor (such as C and R in FIG. 1) connected to the output terminal of the driving chip affect v together_GSThe ascending and descending speed. The auxiliary MOSFET is formed by a controlled MOSFET having an input capacitance of about nFThe transconductance gain of T is much greater than 1 (S). The open loop amplification of the gate degeneration active drive circuit is therefore sufficiently large. When v is_GSTracking the rising (falling) v of a ramp_GSWhen there is little deviation between the two, v_GSA and v_GSWith approximately equal ramp-up and ramp-down rates.

The auxiliary capacitor C has a decoupling function in function, and the 'electric perimeter' of a loop formed by the output end of the driving chip, the auxiliary MOSFET and the gate source electrode of the controlled MOSFET is shortened. It is recommended that the auxiliary capacitor C has an impedance of not more than 0.2 Ω at the undamped self-oscillation frequency of the power loop of the bridge arm circuit, that is:

in this embodiment, the output capacitance C of the controlled MOSFET (IMZ120R030M1H)_oss116pF stray inductance L of the power loop_oEstimated to be 50nH, so the auxiliary capacitance C should be no less than 12nF according to the above formula; the auxiliary capacitance C-20 nF is chosen engineering to ensure that its impedance at the undamped self-oscillation frequency of the power loop is sufficiently small.

After the auxiliary capacitor C is selected, the driving resistor R can be designed. The product τ of the driving resistor R and the auxiliary capacitor C is RC, which is the charge and discharge time constant of the RC circuit. The charging and discharging time constant τ is inversely proportional to the rising and falling slope of the gate-source voltage, i.e., a larger charging and discharging time constant τ will result in a slower rising and falling time of the gate-source voltage, and therefore, the switching speed of the controlled MOSFET will also be slower. On the contrary, if the switching speed of the controlled MOSFET needs to be increased, if the loss needs to be reduced and the efficiency needs to be improved, a smaller charging and discharging time constant τ can be adopted to obtain a faster switching speed. However, the driving resistor R also has to take current limiting and protecting effects on the driving chip, and the switching operation starts, so that the charging and discharging current of the driving chip to the auxiliary capacitor C through the driving resistor R reaches the peak value (V)_CC-V_EE) and/R. In order to maximize the load capacity of the driver chip selected in this embodiment and to obtain a relatively fast switching speed of the MOSFET, the present embodiment designs the charge/discharge current peak (V) according to 70% of the output current peak of the driver chip_CC-V_EE) and/R. Turn-on voltage V_CC20V, turn-off voltage V_EESince 70% of the maximum output current of 1ED3124MU12H is about 10A at-5V, the driving resistance R is 2.5 Ω, and the corresponding charge-discharge time constant τ is 50 nS. It should be noted that the design of the driving resistor R is only used for demonstration, and in industrial application, the driving resistor can be flexibly adjusted and selected according to comprehensive requirements of efficiency, loss, electromagnetic compatibility and the like in combination with the value of the auxiliary capacitor.

(5) PCB design of drive circuit

In order to ensure the reliability of hardware design, parasitic inductance in a power circuit needs to be reduced in a main power part, and drain-source voltage oscillation and peak of a power tube MOSFET are reduced. The embodiment adopts the mode that copper is spread on the upper layer and the lower layer and the middle via hole is connected. In the driving circuit, in order to make the parasitic inductance of the circuit as small as possible, the length of the driving circuit is shortened as much as possible, main components are close to the MOSFET of the power tube as much as possible under the condition of meeting safety regulations, and meanwhile, the driving circuit is shortened by adopting a mode of spreading copper in a large area, so that the auxiliary MOSFET can work effectively and is not influenced by stray parameters of leads.

As shown in fig. 5a, 5b and 5c, the experimental circuit in the double-pulse circuit of this embodiment includes an experimental circuit without any suppression measure compared with the MOSFET gate negative feedback active driving circuit, an experimental circuit with passive suppression measure compared with the MOSFET gate negative feedback active driving circuit, and an experimental circuit with negative feedback active driving compared with the MOSFET gate negative feedback active driving circuit; all are provided with a driving pulse to drive an active MOSFET Q_HSetting a negative voltage bias for turning off the passive MOSFET Q_LIn this example, the passive tube Q in three cases is compared_LGate-source voltage v_GS2And the method is used for verifying the effectiveness of stabilizing the grid-source voltage by adopting the MOSFET grid negative feedback active driving circuit under the interference condition.

As shown in fig. 6a to 6c, the active tube Q is an experimental waveform of the non-interference suppressed conventional driving circuit according to the embodiment of the present invention_HAnd a passive tube Q_LIs driven onlyThere are driving resistors, and the corresponding driving resistors are all 10 Ω. As shown in fig. 6a, the passive tube Q_LGate-source voltage v_GS2Larger oscillation occurs when the interference is received, the positive interference amplitude is as high as 7.9V, and the negative interference amplitude is as high as 7V. As shown in fig. 6b, the passive tube Q_LIs of the drain-source voltage v_DS2In the rising process, the rising slope of 100V-800V is about 43.7V/ns. As shown in fig. 6c, the passive tube Q_LIs of the drain-source voltage v_DS2In the descending process, the descending slope of 800V-100V is about 51.25V/ns. Visible, passive tube Q_LIs of the drain-source voltage v_DS2The rising and falling speed is faster, causing Q_LGate-source voltage v_GS2Is obviously unstable.

As shown in fig. 7a to 7c, the active tube Q is an experimental waveform of the driving circuit adopting the passive suppression method in this embodiment_HAnd a passive tube Q_LThe driving circuit adopts a method of connecting auxiliary capacitors of grid and source electrodes in parallel. Drive resistor R₁、R₂Is 10 omega, and the grid electrode and the source electrode are connected with an auxiliary capacitor C in parallel_a1、C_a2Is 2 nF. As shown in FIG. 7a, the passive tube Q_LGate-source voltage v_GS2The interference oscillation of (2) is relieved to a certain extent, the positive interference amplitude is about 4V, and the negative interference amplitude is also about 4V. As shown in fig. 7b, the passive tube Q_LIs of the drain-source voltage v_DS2In the rising process, the rising slope of 100V-800V is about 42.5V/ns. As shown in fig. 7c, the passive tube Q_LIs of the drain-source voltage v_DS2During the descending process, the descending slope of 800V-100V is about 39.6V/ns. Compared with the switching speed in the embodiments of fig. 6a to 6c, the switching speed is greatly reduced, and it can be seen that the passive gate oscillation suppression method using the gate-source parallel auxiliary capacitor effectively suppresses the gate-source oscillation, but at the expense of the switching speed.

As shown in fig. 8a to 8c, experimental waveforms of the MOSFET gate degeneration active driving circuit in this embodiment are shown. Active tube Q_HAnd a passive tube Q_LThe driving circuits of the driving circuit adopt active negative feedback driving. As shown in fig. 8a, the passive tube Q_LGate-source voltage v_GS2The interference oscillation of (2) is relieved to a greater extent, the positive interference amplitude is about 3V, and the negative interference amplitude is also about 3V.As shown in fig. 8b, the passive tube Q_LIs of the drain-source voltage v_DS2In the rising process, the rising slope of 100V-800V is about 50V/ns. As shown in fig. 8c, the passive tube Q_LIs of the drain-source voltage v_DS2In the descending process, the descending slope of 800V-100V is about 50V/ns. Compared with the passive suppression schemes in the embodiments of fig. 7a to 7c, the gate negative feedback active suppression circuit provided by the invention can realize larger gate-source voltage oscillation suppression without sacrificing the switching speed. In the case of the auxiliary capacitor (20nF), the switching speed is still improved to a certain extent compared to the embodiment of fig. 6a to 6 c.

Another embodiment of the present invention:

as shown in fig. 1, a MOSFET gate degeneration active driving circuit for connecting a driving signal to control the on and off of a controlled MOSFET comprises:

drive push-pull circuit for generating drive voltage v for controlling MOSFET-like wide bandgap semiconductor device_GSA first step of; namely, a driving current is provided to drive the controlled MOSFET, the driving signal is connected to the driving push-pull circuit, and the driving push-pull circuit is connected with the third node in series;

one end of the driving resistor R is connected with the driving push-pull circuit in series, and the other end of the driving resistor R is connected with the first node and used for limiting the charging and discharging current of the driving push-pull circuit to the auxiliary capacitor C and playing roles in current limiting and protecting; the voltage difference between the first node and the source electrode of the controlled MOSFET is a driving voltage;

one end of the auxiliary capacitor C is connected with the first node, the other end of the auxiliary capacitor C is connected with the source S of the controlled MOSFET through a third node, and the auxiliary capacitor C and the driving resistor R form a passive network and are used for adjusting the switching speed of the controlled MOSFET;

the auxiliary MOSFET is a P-channel MOSFET, the source electrode of the auxiliary MOSFET is connected with the grid electrode of the controlled MOSFET and used for constructing a negative feedback regulation mechanism, and the drain electrode of the auxiliary MOSFET is connected to a driving voltage; the driving voltage is the voltage of the driving chip after being filtered by the passive network; the drain electrode D of the P-channel MOSFET_pAnd gate G_pVia a second node and saidDriving resistors R connected in series and source S_pThe negative feedback control circuit is connected with a controlled MOSFET grid G and is used for constructing a negative feedback regulation mechanism and realizing grid voltage self-stabilization;

the drive push-pull circuit comprises a MOSFET drive chip and an on bias voltage V_CCAnd turn-off bias voltage V_EE(ii) a The positive port of the output power supply of the MOSFET driving chip is connected to a turn-on bias voltage V_CCThe negative port of the output power supply of the MOSFET driving chip is connected to a turn-off bias voltage V_EEThe drive output port of the MOSFET drive chip is connected to one end of the drive resistor R, and the drive input port of the drive chip is connected to a drive signal; the turn-on bias voltage V_CCAnd off bias voltage V_EEAre all connected to the third node; the drive push-pull circuit only adopts a drive chip of a common MOSFET, V_CCIn order to turn on the bias voltage, the recommended turn-on bias voltage value is 18-22V, V_EEFor turning off the bias voltage, the recommended value of the turn-off bias voltage is-2.5 to-5V, and the recommended Common Mode Transient Immunity (CMTI) of the driving chip is more than or equal to 100V/ns (within the full temperature range). In terms of driving capability, the chip output current should not be less than (V)_CC-V_EE)/R_gWherein R is_gIs the gate parasitic resistance of the controlled MOSFET.

The P-channel MOSFET needs to bear certain voltage and current in the turn-on and turn-off processes of the controlled MOSFET, so that the P-channel MOSFET needs to be switched on according to the turn-on bias voltage V designed by the driving chip to ensure the safe operation of the P-channel MOSFET_CCOff bias voltage V_EEAnd the grid characteristics of the controlled MOSFET, the voltage and current levels of the auxiliary MOSFET are selected, and the recommended drain-source breakdown voltage is not less than V_CC-V_EEAnd sustainable continuous drain current not less than (V)_CC-V_EE)/R_g. Meanwhile, in order to ensure the control precision, the transconductance gain of the P-channel MOSFET should be much larger than 1 (S).

The auxiliary capacitor C can adjust the switching speed of the controlled MOSFET, and can reduce the area of a loop formed by the driving chip, the auxiliary MOSFET and the grid source electrode of the controlled MOSFET, thereby realizing the high-frequency decoupling of the driving loop.

Although specific embodiments of the invention have been described above, it will be understood by those skilled in the art that the specific embodiments described are illustrative only and are not limiting upon the scope of the invention, and that equivalent modifications and variations can be made by those skilled in the art without departing from the spirit of the invention, which is to be limited only by the appended claims.