阅读说明：本技术 用于基于信号特性来显示信号的系统和方法 (System and method for displaying signals based on signal characteristics ) 是由 B·S·德拉库里克 S·法克哈 T·G·福克塞尔 B·弗拉吉尼克 S·J·阿斯瓦泰姆 于 2019-05-09 设计创作，主要内容包括：公开了用于基于诸如晚电位或早激活的信号特性来显示信号的系统、方法和计算机程序产品实施例。实施例通过由第一信号模块的第一数字信号处理器(DSP),将与第一心脏信号相关联的第一分组中的心搏与已知信号特性匹配来进行操作。实施例还响应于匹配,通过第二信号模块的第二DSP而在与第二心脏信号相关联的第二分组中搜索信号特性。实施例通过与第一信号模块和第二信号模块耦合的显示模块来显示第一心脏信号的一部分。实施例然后基于搜索,通过显示模块来显示包括信号特性的第二心脏信号的一部分,第二心脏信号的一部分与第一心脏信号所显示的部分时间同步。(System, method, and computer program product embodiments for displaying a signal based on a signal characteristic, such as late potential or early activation, are disclosed. Embodiments operate by matching, by a first Digital Signal Processor (DSP) of a first signal module, heart beats in a first packet associated with a first cardiac signal to known signal characteristics. Embodiments also search, by the second DSP of the second signal module, for signal characteristics in a second packet associated with the second cardiac signal in response to the match. Embodiments display a portion of the first cardiac signal via a display module coupled to the first signal module and the second signal module. Embodiments then display, by the display module, a portion of the second cardiac signal including the signal characteristic based on the searching, the portion of the second cardiac signal being time-synchronized with the portion displayed by the first cardiac signal.)

1. A system for visualization of a signal, comprising:

a memory, comprising:

a first signal module comprising a first Digital Signal Processor (DSP) configured to match heart beats in a first packet associated with a first cardiac signal to known signal characteristics;

a second signal module comprising a second DSP configured to search for late potentials in second packets associated with a second cardiac signal in response to the matching; and

a display module coupled to the first signal module and the second signal module and configured to:

displaying a portion of the first cardiac signal; and

based on the searching, displaying a portion of the second cardiac signal that includes the late potential, the portion of the second cardiac signal being temporally synchronized with the displayed portion of the first cardiac signal; and

at least one processor coupled to the memory and configured to execute the first signal module, the second signal module, and the display module.

2. The system of claim 1, wherein the display module is further configured to:

Displaying the portion of the first cardiac signal and the portion of the second cardiac signal side-by-side.

3. The system of claim 1, wherein the display module is further configured to:

displaying the portion of the second cardiac signal corresponding to the displayed portion of the first cardiac signal, wherein the portion of the first cardiac signal and the portion of the second cardiac signal are displayed vertically stacked.

4. The system of claim 3, wherein the display module is further configured to: adjusting an offset of the first cardiac signal based on the known signal characteristics, thereby fixing the first cardiac signal to a baseline.

5. A computer-implemented method for visualizing signals, comprising:

matching, by at least one processor of a first Digital Signal Processor (DSP) executing a first signal module, heartbeats in a first packet associated with a first cardiac signal to known signal characteristics;

searching, by the at least one processor of the second DSP executing the second signal module, for late potentials in second packets associated with the second cardiac signal in response to the matching;

Displaying, by the at least one processor executing a display module coupled to the first signal module and the second signal module, a portion of the first cardiac signal; and

displaying, by execution of the at least one processor of the display module coupled to the first signal module and the second signal module, a portion of the second cardiac signal including the late potential based on the searching, the portion of the second cardiac signal being time-synchronized with the displayed portion of the first cardiac signal.

6. The method of claim 5, further comprising:

displaying, by execution of the at least one processor of the display module, the portion of the first cardiac signal and the portion of the second cardiac signal side-by-side.

7. The method of claim 5, further comprising:

displaying, by execution of the at least one processor of the display module, the portion of the second cardiac signal corresponding to the displayed portion of the first cardiac signal, wherein the portion of the first cardiac signal and the portion of the second cardiac signal are displayed vertically stacked.

8. The method of claim 7, further comprising:

adjusting, by execution of the at least one processor of the display module, an offset of the first cardiac signal based on the known signal characteristic, thereby fixing the first cardiac signal to a baseline.

9. A non-transitory computer-readable device having instructions stored thereon, which, when executed by at least one computing device, cause the at least one computing device to perform operations comprising:

matching, by a first Digital Signal Processor (DSP) of a first signal module, heartbeats in a first packet associated with a first cardiac signal to known signal characteristics;

searching, by a second DSP of a second signal module, for late potentials in second packets associated with a second cardiac signal in response to the matching;

displaying, by a display module coupled to the first signal module and the second signal module, a portion of the first cardiac signal; and

displaying, by the display module coupled to the first signal module and the second signal module, a portion of the second cardiac signal including the late potential based on the searching, the portion of the second cardiac signal being time-synchronized with the displayed portion of the first cardiac signal.

10. The non-transitory computer-readable device of claim 9, wherein the operations further comprise:

displaying, by the display module, the portion of the first cardiac signal and the portion of the second cardiac signal side-by-side.

11. The non-transitory computer-readable device of claim 9, wherein the operations further comprise:

displaying, by the display module, the portion of the second cardiac signal corresponding to the displayed portion of the first cardiac signal, wherein the portion of the first cardiac signal and the portion of the second cardiac signal are displayed vertically stacked.

12. The non-transitory computer-readable device of claim 11, wherein the operations further comprise:

adjusting, by the display module, an offset of the first cardiac signal based on the known signal characteristic, thereby fixing the first cardiac signal to a baseline.

13. A system for visualization of a signal, comprising:

a memory, comprising:

a first signal module comprising a first Digital Signal Processor (DSP) configured to match heart beats in a first packet associated with a first cardiac signal to known signal characteristics;

A second signal module comprising a second DSP configured to search for early activation in a second cardiac signal in a period prior to the matched heartbeat; and

a display module coupled to the first signal module and the second signal module and configured to:

displaying a portion of the first cardiac signal; and

based on the searching, displaying a portion of the second cardiac signal that includes the early activation, the portion of the second cardiac signal being temporally synchronized with the displayed portion of the first cardiac signal; and

at least one processor coupled to the memory and configured to execute the first signal module, the second signal module, and the display module.

14. The system of claim 13, wherein the display module is further configured to:

displaying the portion of the first cardiac signal and the portion of the second cardiac signal side-by-side.

15. The system of claim 13, wherein the display module is further configured to:

displaying the portion of the second cardiac signal corresponding to the displayed portion of the first cardiac signal, wherein the portion of the first cardiac signal and the portion of the second cardiac signal are displayed vertically stacked.

16. The system of claim 15, wherein the display module is further configured to: adjusting an offset of the first cardiac signal based on the known signal characteristics, thereby fixing the first cardiac signal to a baseline.

17. A computer-implemented method for visualizing signals, comprising:

matching, by at least one processor of a first Digital Signal Processor (DSP) executing a first signal module, heartbeats in a first packet associated with a first cardiac signal to known signal characteristics;

searching, by the at least one processor of a second DSP executing a second signal module, for early activation in a second cardiac signal in a period prior to the matched heartbeat;

displaying, by the at least one processor executing a display module coupled to the first signal module and the second signal module, a portion of the first cardiac signal; and

displaying, by execution of the at least one processor of the display module coupled to the first signal module and the second signal module, a portion of the second cardiac signal including the early activation based on the searching, the portion of the second cardiac signal being temporally synchronized with the displayed portion of the first cardiac signal.

18. The method of claim 17, further comprising:

displaying, by execution of the at least one processor of the display module, the portion of the first cardiac signal and the portion of the second cardiac signal side-by-side.

19. The method of claim 17, further comprising:

displaying, by execution of the at least one processor of the display module, the portion of the second cardiac signal corresponding to the displayed portion of the first cardiac signal, wherein the portion of the first cardiac signal and the portion of the second cardiac signal are displayed vertically stacked.

20. The method of claim 19, further comprising:

adjusting, by execution of the at least one processor of the display module, an offset of the first cardiac signal based on the known signal characteristic, thereby fixing the first cardiac signal to a baseline.

21. A non-transitory computer-readable device having instructions stored thereon, which, when executed by at least one computing device, cause the at least one computing device to perform operations comprising:

matching, by a first Digital Signal Processor (DSP) of a first signal module, heartbeats in a first packet associated with a first cardiac signal to known signal characteristics;

Searching, by a second DSP of a second signal module, for early activation in a second cardiac signal in a period prior to the matched heartbeat;

displaying, by a display module coupled to the first signal module and the second signal module, a portion of the first cardiac signal; and

displaying, by the display module coupled to the first signal module and the second signal module, a portion of the second cardiac signal including the early activation based on the search, the portion of the second cardiac signal being temporally synchronized with the displayed portion of the first cardiac signal.

22. The non-transitory computer-readable device of claim 21, wherein the operations further comprise:

displaying, by the display module, the portion of the first cardiac signal and the portion of the second cardiac signal side-by-side.

23. The non-transitory computer-readable device of claim 21, wherein the operations further comprise:

displaying, by the display module, the portion of the second cardiac signal corresponding to the displayed portion of the first cardiac signal, wherein the portion of the first cardiac signal and the portion of the second cardiac signal are displayed vertically stacked.

24. The non-transitory computer-readable device of claim 23, wherein the operations further comprise:

adjusting, by the display module, an offset of the first cardiac signal based on the known signal characteristic, thereby fixing the first cardiac signal to a baseline.

25. A computer-implemented method, comprising:

accessing, by at least one processor, a first cardiac signal associated with a surface lead;

matching, by the at least one processor, a heartbeat of the first cardiac signal to a known signal pattern; and

searching, by the at least one processor, in a second cardiac signal for a period before and after the matched heartbeat, for an early activation or a late potential.

26. The method of claim 25, wherein the period of time is a user-defined period of time.

27. The method of claim 25, wherein the searching further comprises:

searching, by the at least one processor, for the early activation based on an amplitude threshold.

28. The method of claim 25, wherein the searching further comprises:

searching, by the at least one processor, a buffer for the early activation or the late potential, the buffer comprising a portion of the second cardiac signal.

29. The method of claim 25, wherein the matching further comprises:

matching, by the at least one processor, the heartbeat of the first cardiac signal to the known signal pattern based on a correlation function.

30. The method of claim 25, wherein the matching further comprises:

matching, by the at least one processor, the heartbeat of the first cardiac signal to the known signal pattern based on a Mean Absolute Deviation (MAD) function.

31. The method of claim 25, wherein the matching further comprises:

matching, by the at least one processor, the heartbeat of the first cardiac signal to the known signal pattern based on a confidence value.

32. The method of claim 31, wherein the confidence value is user defined.

33. The method of claim 25, further comprising:

interpolating, by the at least one processor, signal data from a catheter at the site of early activation to the site of late potential.

34. The method of claim 33, further comprising:

independently displaying, by the at least one processor, the signal data from the catheter with a late potential filter.

35. The method of claim 33, further comprising:

inferring, by the at least one processor, a location of a conduction delay between the location of the early activation and the location of the late potential.

36. A non-transitory computer-readable device having instructions stored thereon, which, when executed by at least one computing device, cause the at least one computing device to perform operations comprising:

accessing a first cardiac signal associated with a surface lead;

matching heart beats of the first cardiac signal to a known signal pattern; and

searching for early activation or late potential in a second cardiac signal for periods before and after the matched heart beat.

37. The non-transitory computer-readable device of claim 36, wherein the period of time is a user-defined period of time.

38. The non-transitory computer-readable device of claim 36, wherein the searching further comprises:

searching for the early activation based on an amplitude threshold.

39. The non-transitory computer-readable device of claim 36, wherein the searching further comprises:

searching a buffer for the early activation or the late potential, the buffer comprising a portion of the second cardiac signal.

40. The non-transitory computer-readable device of claim 36, wherein the matching further comprises:

matching the heart beats of the first cardiac signal to the known signal pattern based on a correlation function.

41. The non-transitory computer-readable device of claim 36, wherein the matching further comprises:

matching the beats of the first cardiac signal to the known signal pattern based on a Mean Absolute Deviation (MAD) function.

42. The non-transitory computer-readable device of claim 36, wherein the matching further comprises:

matching the heartbeat of the first cardiac signal to the known signal pattern based on a confidence value.

43. The non-transitory computer-readable device of claim 42, wherein the confidence value is user-defined.

44. The non-transitory computer-readable device of claim 36, the operations further comprising:

interpolating signal data from a catheter at the site of early activation to the site of late potential.

45. The non-transitory computer-readable device of claim 44, the operations further comprising:

independently displaying the signal data from the catheter using a late potential filter.

46. The non-transitory computer-readable device of claim 44, the operations further comprising:

inferring a location of conduction delay between the location of the early activation and the location of the late potential.

47. A computer-implemented method for filtering noise from an input signal, comprising:

accessing, by at least one processor, an input signal having a first harmonic frequency and having the noise;

determining, by the at least one processor, a silence period in the input signal;

storing, by the at least one processor, samples of the noise of the input signal in a buffer during the silence period;

subtracting, by the at least one processor, the samples from the single cycle of the noise in the buffer from the input signal to create a filtered signal, wherein the subtracting removes the first and second harmonic frequencies from the input signal and avoids introducing transient responses in the filtered signal; and

repeating, by the at least one processor, the determining, the storing, and the subtracting to refine the filtered signal.

48. The method of claim 47, wherein the determining further comprises:

calculating, by the at least one processor, a slope of the input signal; and

determining, by the at least one processor, that the slope is below a threshold, thereby determining the existence of the silence period.

49. The method of claim 47, wherein the storing further comprises:

averaging, by the at least one processor, samples of the input signal with corresponding samples of the noise of the input signal in the buffer to create averaged samples; and

replacing, by the at least one processor, the corresponding sample of the noise of the input signal in the buffer with the averaged sample.

50. The method of claim 47, wherein the first harmonic frequency is 60 Hz, and the second harmonic frequency is 120 Hz or 180 Hz.

51. The method of claim 47, wherein a frequency of the noise of the input signal is substantially constant.

52. The method of claim 51, wherein a size of the buffer is based on the frequency of the noise of the input signal.

53. A non-transitory computer-readable device having instructions stored thereon, which, when executed by at least one computing device, cause the at least one computing device to perform operations comprising:

accessing an input signal having a first harmonic frequency and having noise;

determining a silence period in the input signal;

storing samples of the noise of the input signal in a buffer during the silence period;

subtracting the samples from a single cycle of the noise in the buffer from the input signal to create a filtered signal, wherein the subtracting removes the first and second harmonic frequencies from the input signal and avoids introducing transient responses in the filtered signal; and

repeating said determining, said storing, and said subtracting to refine said filtered signal.

54. The non-transitory computer-readable device of claim 53, wherein the determining further comprises:

calculating a slope of the input signal; and

determining that the slope is below a threshold, thereby determining the existence of the silence period.

55. The non-transitory computer-readable device of claim 53, wherein the storing further comprises:

Averaging samples of the input signal with corresponding samples of the noise of the input signal in the buffer to create averaged samples; and

replacing the corresponding sample of the noise of the input signal in the buffer with the averaged sample.

56. The non-transitory computer-readable device of claim 53, wherein the first harmonic frequency is 60 Hertz and the second harmonic frequency is 120 Hertz or 180 Hertz.

57. The non-transitory computer-readable device of claim 53, wherein a frequency of the noise of the input signal is substantially constant.

58. The non-transitory computer-readable apparatus of claim 53, wherein a size of the buffer is based on the frequency of the noise of the input signal.

59. A computer-implemented method for filtering noise from an input signal, comprising:

accessing, by at least one processor, the input signal including the noise and a high frequency signal of interest;

high-pass filtering, by the at least one processor, the input signal to create a filtered signal;

isolating, by the at least one processor, artifacts associated with the noise in the filtered signal from the high frequency signal of interest; and

Blanking, by the at least one processor, the filtered signal for a fixed period before and after the isolated artifact, wherein the blanking removes the isolated artifact and allows the high frequency signal of interest to pass.

60. The method of claim 59, further comprising:

filtering, by the at least one processor, the input signal using a notch filter.

61. The method of claim 59, wherein isolating the artifacts further comprises:

calculating, by the at least one processor, a slope of the filtered input signal; and

determining, by the at least one processor, that the slope is above a threshold, thereby determining the presence of the artifact.

62. The method of claim 59, wherein isolating the artifacts further comprises:

characterizing, by the at least one processor, the artifact in an artifact template, wherein the blanking applies the artifact template as the selected filter to the isolated artifact in the filtered signal.

63. The method of claim 59, wherein accessing the input signal comprising the noise and the high frequency signal of interest further comprises: access the purkinje signal.

64. The method of claim 59, wherein accessing the input signal comprising the noise and the high frequency signal of interest results from performing a fast conducted tissue identification filtering.

65. The method of claim 59, wherein isolating the artifacts further comprises: isolating, by the at least one processor, the impulse response.

66. The method of claim 59, further comprising:

buffering, by the at least one processor, the filtered signal for the fixed period of time before and after the isolated artifact.

67. The method of claim 59, further comprising:

selecting, by the at least one processor, a filter based on the isolated artifacts; and

applying, by the at least one processor, the selected filter to blank the isolated artifact in the filtered signal.

68. A non-transitory computer-readable device having instructions stored thereon, which, when executed by at least one computing device, cause the at least one computing device to perform operations comprising:

accessing an input signal comprising noise and a high frequency signal of interest;

High-pass filtering the input signal to create a filtered signal;

isolating artifacts in the filtered signal associated with the noise from the high frequency signal of interest; and

blanking the filtered signal for a fixed period before and after the isolated artifact, wherein the blanking removes the isolated artifact and allows the high frequency signal of interest to pass.

69. The non-transitory computer-readable device of claim 68, further comprising:

a notch filter is used to filter the input signal.

70. The non-transitory computer-readable device of claim 68, wherein the isolating further comprises:

calculating a slope of the filtered input signal; and

determining that the slope is above a threshold, thereby determining the presence of the artifact.

71. The non-transitory computer-readable device of claim 68, wherein the isolating further comprises:

characterizing the artifact in an artifact template, wherein the blanking applies the artifact template as the selected filter to the isolated artifact in the filtered signal.

72. The non-transitory computer-readable device of claim 68, wherein accessing the input signal that includes the noise and the high frequency signal of interest further comprises: access the purkinje signal.

73. The non-transitory computer-readable device of claim 68, wherein accessing the input signal that includes the noise and the high frequency signal of interest results from performing fast conduction tissue identification filtering.

74. The non-transitory computer readable device of claim 68, wherein isolating the artifacts further comprises: the impulse response is isolated.

75. The non-transitory computer-readable device of claim 68, wherein the operations further comprise:

buffering the filtered signal for the fixed period of time before and after the isolated artifact.

76. The non-transitory computer-readable device of claim 68, wherein the operations further comprise:

selecting a filter based on the isolated artifacts; and

applying the selected filter to blank the isolated artifact in the filtered signal.

77. A computer-implemented method, comprising:

accessing, by at least one processor, the input cardiac signal;

matching, by the at least one processor, a portion of the input cardiac signal to a known signal pattern; and

displaying, by the at least one processor, an indication of a degree of the match.

78. The method of claim 77, wherein the known signal pattern is captured during a previous patient procedure or a current patient procedure and stored in a pattern template.

79. The method of claim 77, wherein the known signal patterns are stored in a database.

80. The method of claim 77, wherein the matching further comprises:

matching, by the at least one processor, the portion of the input cardiac signal to the known signal pattern based on a correlation function.

81. The method of claim 77, wherein the matching further comprises:

matching, by the at least one processor, the portion of the input cardiac signal to the known signal pattern based on a Mean Absolute Deviation (MAD) function.

82. The method of claim 77, wherein the matching further comprises:

matching, by the at least one processor, the portion of the input cardiac signal to the known signal pattern based on a confidence value.

83. The method of claim 77, wherein the indication of the degree of the match specifies a location to cardiac pace.

84. A non-transitory computer-readable device having instructions stored thereon, which, when executed by at least one computing device, cause the at least one computing device to perform operations comprising:

accessing the input cardiac signal;

matching a portion of the input cardiac signal to a known signal pattern; and

displaying an indication of a degree of the match.

85. The non-transitory computer readable device of claim 84, wherein the known signal pattern is captured during a previous patient procedure or a current patient procedure and stored in a pattern template.

86. The non-transitory computer-readable device of claim 84, wherein the known signal patterns are stored in a database.

87. The non-transitory computer-readable device of claim 84, wherein the matching further comprises:

matching the portion of the input cardiac signal to the known signal pattern based on a correlation function.

88. The non-transitory computer-readable device of claim 84, wherein the matching further comprises:

matching the portion of the input cardiac signal to the known signal pattern based on a Mean Absolute Deviation (MAD) function.

89. The non-transitory computer-readable device of claim 84, wherein the matching further comprises:

matching the portion of the input cardiac signal to the known signal pattern based on a confidence value.

90. The non-transitory computer-readable device of claim 84, wherein the indication of the degree of the match specifies a location to cardiac pace.

91. A computer-implemented method, comprising:

accessing, by at least one processor, the input cardiac signal;

accessing, by the at least one processor, a detection threshold;

matching, by the at least one processor, a portion of the input cardiac signal to a known signal pattern based on the detection threshold; and

displaying, by the at least one processor, a highlighted portion of the input cardiac signal based on the matching.

92. The method of claim 91, wherein the known signal pattern is captured during a previous patient procedure or a current patient procedure.

93. The method of claim 91, wherein the known signal patterns are stored in a database.

94. The method of claim 91, wherein the matching further comprises:

matching, by the at least one processor, the portion of the input cardiac signal to the known signal pattern based on a correlation function.

95. The method of claim 91, wherein the matching further comprises:

matching, by the at least one processor, the portion of the input cardiac signal to the known signal pattern based on a Mean Absolute Deviation (MAD) function.

96. The method of claim 91, wherein the matching further comprises:

first matching, by the at least one processor, the portion of the input cardiac signal to the known signal pattern;

determining, by the at least one processor, a first confidence value based on the first match;

second matching, by the at least one processor, a portion of a second input signal to the known signal pattern;

determining, by the at least one processor, a second confidence value based on the second match;

averaging, by the at least one processor, the first confidence value and the second confidence value to create an average confidence value; and

Determining, by the at least one processor, that the average confidence value is above the detection threshold.

97. The method of claim 91, wherein the displaying further comprises:

displaying, by the at least one processor, the highlighted portion of the input cardiac signal based on a color associated with the known signal pattern.

98. The method of claim 91, wherein the matching further comprises:

matching, by the at least one processor, the portion of the input cardiac signal to the known signal pattern based on a weighted particular region of the known signal pattern.

99. A non-transitory computer-readable device having instructions stored thereon, which, when executed by at least one computing device, cause the at least one computing device to perform operations comprising:

accessing the input cardiac signal;

accessing a detection threshold;

matching a portion of the input cardiac signal to a known signal pattern based on the detection threshold; and

displaying a highlighted portion of the input cardiac signal based on the matching.

100. The non-transitory computer readable device of claim 99, wherein the known signal pattern is captured during a previous patient procedure or a current patient procedure.

101. The non-transitory computer-readable device of claim 99, wherein the known signal patterns are stored in a database.

102. The non-transitory computer-readable device of claim 99, wherein the matching further comprises:

matching the portion of the input cardiac signal to the known signal pattern based on a correlation function.

103. The non-transitory computer-readable device of claim 99, wherein the matching further comprises:

matching the portion of the input cardiac signal to the known signal pattern based on a Mean Absolute Deviation (MAD) function.

104. The non-transitory computer-readable device of claim 99, wherein the matching further comprises:

first matching the portion of the input cardiac signal to the known signal pattern;

determining a first confidence value based on the first match;

second matching a portion of a second input signal to the known signal pattern;

determining a second confidence value based on the second match;

averaging the first confidence value and the second confidence value to create an average confidence value; and

Determining that the average confidence value is above the detection threshold.

105. The non-transitory computer-readable device of claim 99, wherein the displaying further comprises:

displaying the highlighted portion of the input cardiac signal based on a color associated with the known signal pattern.

106. The non-transitory computer-readable device of claim 99, wherein the matching further comprises:

matching the portion of the input cardiac signal to the known signal pattern based on a weighted particular region of the known signal pattern.

107. A system for producing a clean unipolar signal, comprising:

an Electrocardiogram (ECG) circuit board configured to process ECG signals; and

a plurality of intra-cardiac (IC) circuit boards each configured to process a corresponding IC signal,

wherein the ECG circuit board and the plurality of IC circuit boards share substantially the same circuit configuration and components, and

wherein the ECG circuit boards process the ECG signals using substantially the same paths that each IC circuit board uses to process its corresponding IC signals.

108. The system of claim 107, wherein a single Wilson Central Terminal (WCT) signal is used for the ECG circuit board and the plurality of IC circuit boards.

109. A system for performing an Electrophysiological (EP) process, comprising:

an Electrocardiogram (ECG) circuit board configured to receive an ECG signal;

a plurality of intra-cardiac (IC) circuit boards each configured to receive a corresponding IC signal;

a communication interface communicatively coupled to a remote device; and

a processor coupled to the ECG circuit board, the plurality of IC circuit boards, and the communication interface, the processor configured to:

receiving feedback from the remote device via the communication interface; and

controlling, via the communication interface, the remote device based on the ECG signal, each corresponding IC signal, and the feedback from the remote device.

110. The system of claim 109, wherein the remote device is selected from the group consisting of: ultrasound machines, Radio Frequency (RF) generators, stimulators, three-dimensional imaging devices, intracardiac echocardiography (ICE) machines, fluoroscopy machines, and defibrillators.

111. The system of claim 109, wherein the communication interface is communicatively coupled to the remote device using a communication protocol selected from the group consisting of: digital imaging and communications in medicine (DICOM), ethernet, Universal Serial Bus (USB), and Institute of Electrical and Electronics Engineers (IEEE) 802.11.

Technical Field

Embodiments included herein relate generally to cardiac Electrophysiology (EP) signal acquisition and recording systems. More particularly, system, apparatus and method embodiments for communicating biomedical signals between a patient and monitoring and therapy devices are disclosed.

Background

Catheter ablation is a method of treating arrhythmias, such as atrial fibrillation, which is a disease of the heart muscle characterized by abnormal conduction. Depending on the severity of the problem, multiple ablation procedures may be required to achieve effective results. This is because current Electrophysiological (EP) techniques have limitations in accurately locating the tissue to be ablated, which is the source of the abnormality.

A conventional diagnostic procedure begins with an Electrocardiogram (ECG) that is acquired from electrodes attached to the skin surface of a subject (e.g., patient). The medical team evaluates the ECG signal and determines if a drug and/or ablation is indicated. If ablation is indicated, an EP study is performed. The catheter is inserted into the heart via the patient's neck or groin and the electrical activity of the heart is recorded. Based on this EP study, ablation is performed on the region(s) of the heart where the medical team suspects to cause abnormal heart rhythm(s).

An ablation catheter is inserted into a patient's blood vessel and is directed to a site in the heart that causes tissue of abnormal electrical propagation. The catheter may use different energy sources (most commonly hot or cold) to scar the tissue, reducing its ability to initiate and/or transmit abnormal electrical impulses, thereby ablating abnormal heart rhythms. ECG signals are recorded from surface electrodes on the patient's skin, and Intracardiac (IC) signals may be acquired from a catheter inside the patient's heart and recorded as an Electrogram (EGM). Both ECG and ic (egm) signals are small signals that require conditioning and amplification to be accurately evaluated.

In conventional EP systems, to confirm whether ablation therapy is successful for a certain tissue site, a medical team must often stop the ablation procedure and collect physiological signals (e.g., heart) from a monitoring device (e.g., an ECG monitor). This is because current systems cannot accurately and simultaneously detect, acquire and isolate delicate dirty signals (amplitude in the range of 0.1-5mV and frequency in the range of DC to 1 kHz) in real time during the application of large ablation signals (on the order of hundreds of volts at frequencies around 450 kHz).

In particular, U.S. patent application publication No. US2006/0142753A1 to Francischelli et al proposes a system and method for ablating and assessing the integrity or transmurality of tissue to be ablated by monitoring the depolarizing ECG signal from an electrode adjacent to it. Francischelli et al note that in order to minimize noise sensing problems during measurement of ECG signals from electrodes on an ablation device, the measurement is preferably performed during interruption of delivery of ablation energy to the ablation electrodes.

In general, some current EP recording systems can effectively support treatment of arrhythmias that exhibit large amplitude, low frequency signals (such as atrial flutter and supraventricular tachycardia). However, more complex and prevalent arrhythmias characterized by low amplitude, high frequency signals (such as atrial fibrillation and ventricular tachycardia) have not found effective assessment of all relevant signals.

Equipping with line noise and pacing signals can make signal detection, acquisition, and feature extraction more complex. To reduce noise and artifacts from various electrical signal information, current EP recorders use low-pass, high-pass, and notch filters. Unfortunately, conventional filtering techniques can alter the signals and make it difficult or impossible to see the low amplitude, high frequency signals inherent in cardiac monitoring, and visualization of these signals can help treat atrial fibrillation and ventricular tachycardia. It has recently been recognized that guarantees on waveform integrity, such as for low noise acquisition of IC and ECG signals in an EP environment, have not previously been achieved due to contamination by artifacts and noise.

In particular, Martinez-Inieta et al in an article entitled "wave form integration in Electrical Fidelization" The Forgotten Issue of Cardiac Electrophysiology "(annual review of biomedical engineering, 4.18.2017) indicated that The noise of high frequency and broadband equipment was" inevitably recorded "during signal acquisition, and that other complications of acquisition also come from other various signals, including 50Hz or 60Hz mains, high frequency patient muscle activity, and low frequency baseline wander (due to breathing or catheter movement or catheter contact instability). Martinez-Iniesta et al further note that conventional filtering results in significant changes in waveform and spectral properties and poor noise reduction. However, active filtering between 30 and 300Hz is still a conventional EP practice.

Conventional practice distorts the morphological characteristics of the generated signal, resulting in loss of relevant (interesting) signal information and affecting signal validity. Martinez-Iniesta et al propose software solutions that use only preprocessing and noise reduction methods to reduce medium and high frequency noise, but there is no solution that combines low frequency noise reduction components in software with noise reduction components in hardware. An ideal feature of EP systems is the ability to preserve the integrity of the original signal information using a combination of hardware and software that can reduce noise in the signal (or improve high signal-to-noise ratio) while minimizing hardware filtering that might otherwise eliminate the signal content of interest.

Currently, the primary method of ablation treatment for paroxysmal and persistent atrial fibrillation is Pulmonary Vein Isolation (PVI), where a medical team uses a cardiac mapping system to reconstruct the heart geometry in 3D and perform ablation at anatomical locations, such as the pulmonary veins from which the atrial fibrillation originates. The procedure takes 2-8 hours and the physician may not have access to a persistent lesion/scar to isolate the problematic tissue from the left atrium. Thus, the patient is often required to return to performing additional ablation procedures to complete the treatment. However, by being able to clearly observe the cardiac signal during ablation and determine whether the ablation lesion is transmural, additional ablation procedures and possible complications may be minimized.

Conventional EP systems may suffer from other limitations. First, users often want to process and display multiple features of a signal in near real-time. For example, a medical team may wish to simultaneously display various and multiple versions of ECG, IC, and other physiological signals in near real-time to assess different signal attributes. Conventional EP systems typically cannot process and display multiple versions of a signal simultaneously in near real-time.

Second, users often wish to dynamically apply new digital signal processing functions to a signal without interfering with other digital signal processing functions already applied to the signal. Conventional solutions do not enable a user to dynamically apply new digital signal processing functions to a signal without stopping the capture of the signal or interfering with other digital signal processing functions already applied to the signal.

Finally, users often desire to synchronize the processing and display of multiple signals in near real-time. For example, a user may want to synchronize the display of multiple processed versions of the same signal. In addition, medical teams may wish to synchronize the display of multiple processed versions of ECG, IC, and other physiological signals. This is because the ability of a medical team to make effective clinical diagnoses may depend on comparing multiple signals at the same point in time. Conventional solutions may not be able to process and synchronize the display of multiple processed signals in near real-time.

Disclosure of Invention

Apparatus, systems, and methods for EP signal acquisition and recording with a number of improvements in noise and artifact reduction in various biomedical applications are disclosed.

Embodiments of the disclosed EP system can record raw (unaltered) cardiac and other physiological signals with multiple display options and with low noise and large input signal dynamic range. With minimal use of filters in hardware (e.g., hardware filters for AC coupling, anti-aliasing, and RF suppression only), the raw signals acquired by the acquisition module are filtered and processed in accompanying software using a digital processing module. The use of software-based digital signal processing algorithms allows for simultaneous display of signals in real time in a single window or multiple windows, either as raw signals or as a combination of raw and processed signals. Further, the visualization and review capabilities of the disclosed EP system allow a user to mark features specified in the algorithm on real-time tracking.

The disclosed EP system allows for the display of signals where more than one signal processing algorithm is applied simultaneously, a feature not found in conventional systems. This allows the user to view the signal filtered in a variety of ways, for particular reasons. In a real-time window, the waveform of interest may be displayed as the original signal or any combination of the original signal and the filtered signal to enable better visualization of the signal in the presence of noise and artifacts.

All displayed signals are time synchronized. The user may choose to open multiple review windows and be able to display the results of various signal processing algorithms, independent of real-time tracking.

From a clinical perspective, the disclosed EP system can significantly assist a medical team in making decisions for patients undergoing various medical treatments (e.g., ablation), with benefits including, but not limited to: suppression of RF energy for purer, reliable recording of intracardiac signals, reduction of baseline drift, and reduction of noise; dynamic range for better visualization, in particular visualization of very low amplitude signals temporarily located within large amplitude signals; real-time digital processing and raw signal recording to facilitate signal filtering and reduce artifacts and noise without affecting the raw information; high quality monopolar signals to assist in determining tissue type and catheter position; improved waveform integrity and reduced artifacts of signal processing by-products, allowing medical teams to improve surgical outcomes; and improved signal information, allowing the medical team to provide more accurate catheter tip locations for ablation and other levels and durations of treatment to improve treatment effectiveness.

In some embodiments of the system for visualizing the signal using late potentials, the memory comprises: a first signal module comprising a first Digital Signal Processor (DSP) configured to match heart beats (beats) in a first packet associated with a first cardiac signal to known signal characteristics; and a second signal module comprising a second DSP configured to search for late potentials in second packets associated with the second cardiac signal in response to a match. The memory further includes a display module coupled to the first signal module and the second signal module, the display module configured to display a portion of the first cardiac signal based on the search and to display a portion of the second cardiac signal including the late potential, the portion of the second cardiac signal being time-synchronized with the displayed portion of the first cardiac signal. The system also includes at least one processor coupled to the memory and configured to execute the first signal module, the second signal module, and the display module. Execution of the system components by a computer system implements various method embodiments for visualizing signals using late potentials. The computer system includes a non-transitory computer-readable device having instructions stored thereon that, when executed by at least one computing device, cause the at least one computing device to perform operations that implement the method steps.

In some embodiments of the system to visualize signals using early activation, the memory comprises a first signal module comprising a first DSP configured to match heart beats in a first packet associated with the first cardiac signal to known signal characteristics; and a second signal module comprising a second DSP configured to search for early activation in the second cardiac signal within a period of time prior to the matched heartbeat. The memory further includes a display module coupled to the first signal module and the second signal module, the display module configured to display a portion of the first cardiac signal based on the search and to display a portion of the second cardiac signal including the early activation, the portion of the second cardiac signal being time-synchronized with the displayed portion of the first cardiac signal. The system also includes at least one processor coupled to the memory and configured to execute the first signal module, the second signal module, and the display module. Some method embodiments and non-transitory computer-readable device embodiments for visualizing signals using early activation are also disclosed.

Some method and non-transitory computer-readable device embodiments implement the steps of: accessing a first cardiac signal associated with a surface lead, matching a heartbeat of the first cardiac signal to a known signal pattern, and searching for an early activation or late potential in a second cardiac signal at a time period before or after the matched heartbeat.

Other method and non-transitory computer-readable device embodiments for filtering noise from an input signal using notch filtering implement the steps of: accessing an input signal having a first harmonic frequency and having noise; determining a silence period in the input signal; storing noise samples of the input signal during the quiet period in a buffer; subtracting samples from a single cycle of noise in the buffer from the input signal to create a filtered signal, wherein the subtracting removes the first harmonic frequency and the second harmonic frequency from the input signal and avoids introducing transient responses in the filtered signal; and repeating the determining, storing and subtracting to refine the (refine) filtered signal.

Some method and non-transitory computer-readable device embodiments for filtering noise from an input signal using high frequency filtering implement the steps of: accessing an input signal comprising noise and a high frequency signal of interest; high-pass filtering an input signal to create a filtered signal; isolating artifacts associated with noise in the filtered signal from the high frequency signal of interest; optionally selecting a filter based on the isolated artifacts; and blanking the filtered signal for a fixed period before and after the isolated artifact, wherein blanking optionally uses a selected filter to remove the isolated artifact and allow the high frequency signal of interest to pass.

Some method and non-transitory computer-readable device embodiments for pattern matching implement the steps of: accessing the input cardiac signal; matching a portion of the input cardiac signal to a known signal pattern; and displaying an indication of the degree of match. Other embodiments for pattern matching match a portion of the input cardiac signal to a known signal pattern based on a detection threshold and display a highlighted portion of the input cardiac signal based on the matching.

Also disclosed are system embodiments for generating a clean unipolar signal, the system embodiments comprising: an Electrocardiogram (ECG) circuit board configured to process ECG signals and a plurality of intra-cardiac (IC) circuit boards configured to process corresponding IC signals, wherein the ECG circuit board and the plurality of IC circuit boards share substantially the same circuit configuration and components and the ECG circuit board processes ECG signals using substantially the same path that each IC circuit board uses to process its corresponding IC signal.

Other system embodiments for performing Electrophysiology (EP) processing are disclosed, the system embodiments including an ECG circuit board configured to receive ECG signals, a plurality of IC circuit boards each configured to receive IC signals, a communication interface communicatively coupled to a remote device, and a processor coupled to the ECG board, the plurality of IC circuit boards, and the communication interface. Such system embodiments may be configured to receive feedback from the remote device via the communication interface and to control the remote device based on the ECG signal, the IC signal, and the feedback from the remote device via the communication interface.

Drawings

The accompanying drawings, which are incorporated herein and constitute part of this specification, illustrate the present embodiments and, together with the description, further serve to explain the principles of the embodiments and to enable a person(s) skilled in the pertinent art to make and use the embodiments.

Fig. 1 illustrates a block diagram of a conventional Electrophysiology (EP) environment with patient connections and interference sources.

Fig. 2 illustrates a hardware system block diagram of the disclosed EP hardware system, in accordance with some embodiments.

Fig. 3 illustrates a block diagram of a multi-channel analog-to-digital input/output of an EP hardware system input stage, in accordance with some embodiments.

Fig. 4 illustrates a block diagram of a single channel of an EP hardware system input stage, in accordance with some embodiments.

Fig. 5A illustrates a block diagram of an overall EP system, in accordance with some embodiments.

Fig. 5B illustrates a high-level abstraction of the overall EP system hardware and software according to some embodiments.

Fig. 6A illustrates a schematic diagram of a large signal input protection portion of an input protection circuit of an EP hardware system, according to some embodiments.

Fig. 6B illustrates a schematic diagram of an electrostatic discharge (ESD) protection portion of an input protection circuit of an EP hardware system, according to some embodiments.

Fig. 7 illustrates a schematic diagram of a Radio Frequency (RF) filtering portion of an input protection circuit of an EP hardware system, in accordance with some embodiments.

Fig. 8A-8E illustrate voltage signal diagrams of a typical defibrillation signal at the input of an input protection circuit according to an exemplary embodiment.

Fig. 9A-9E illustrate voltage signal graphs of a typical ablation signal at the input of an input protection circuit according to an example embodiment.

Fig. 10 illustrates a schematic diagram of a meter and gain stage of an EP hardware system, according to some embodiments.

Fig. 11 illustrates a schematic diagram of a large signal detection/fast recovery circuit of an EP hardware system, according to some embodiments.

Fig. 12 illustrates a voltage signal diagram showing slow recovery occurring after a large unwanted signal is subjected to the input protection, instrumentation and gain stages of EP hardware system circuitry when a large signal detection/fast recovery circuit is disconnected, according to an exemplary embodiment.

Fig. 13A-13C illustrate voltage signal diagrams showing the fast recovery that occurs after a large unwanted signal is provided to the input protection, instrumentation and gain stages of the EP hardware system circuitry when a large signal detection/fast recovery circuit is connected, according to an example embodiment.

Fig. 14A-14D illustrate signal diagrams of voltage signals at various internal nodes when a large signal detection/fast recovery circuit is connected, according to an example embodiment.

15A-15B illustrate signal diagrams of current signals across a resistor at the output of a connected large signal detection/fast recovery circuit according to one exemplary embodiment.

Fig. 16 illustrates a schematic diagram of a low frequency feedback circuit for use as a dynamic current source for an EP hardware system, in accordance with some embodiments.

17A-17D illustrate signal diagrams of a typical in-band voltage differential input signal that is subject to 60Hz common mode noise entering an EP hardware system, according to an example embodiment.

18A-18D illustrate signal diagrams of exemplary differential voltage signals that are subject to 60Hz common mode noise as they travel through the EP hardware system, according to one exemplary embodiment.

Fig. 19A-19D illustrate signal diagrams of a typical 500kHz ablation input signal, according to an example embodiment, the 500kHz ablation input signal being in a frequency range to be attenuated by an RF filter of the EP hardware system.

Fig. 20A-20B illustrate signal diagrams of a typical 500kHz ablation input signal at a shield input that enables an RF filter to attenuate the input signal of an EP hardware system, according to an example embodiment.

21A-21D illustrate signal diagrams of a typical 500kHz ablation input signal that has been attenuated after it has traveled through an instrumentation amplifier and after it has traveled through a fully differential operational amplifier of an EP hardware system according to one exemplary embodiment.

FIG. 22A illustrates a modification of the visualization of an ECG or IC signal according to an exemplary embodiment.

Fig. 22B illustrates the ability of an EP system to reveal differential amounts of artifacts of low amplitude cardiac signals and EP signals in the presence of noise and large signal processes according to an exemplary embodiment.

Fig. 22C illustrates the ability of an EP system to remove 60Hz noise without saturation or delay recovery, while maintaining the 60Hz signal as a component of the original waveform, according to an exemplary embodiment.

Figure 23 illustrates a schematic diagram of an improved wilson central terminal-right leg drive (WCT-RLD) circuit, in accordance with some embodiments.

Figure 24 illustrates a schematic diagram of a dual T feedback network interfacing with an RLD circuit of a WCT-RLD circuit, in accordance with some embodiments.

Figure 25 illustrates a signal diagram of the output of the dual T feedback network of the WCT-RLD circuit according to an example embodiment.

FIG. 26 is a block diagram of a system for processing and displaying multiple signals in near real time according to some embodiments.

Fig. 27 is a block diagram of a queuing module for storing generated packets associated with different base signals, in accordance with some embodiments.

Fig. 28 is a block diagram of a configuration path module for generating processed time-aligned signals from a base signal set at runtime, in accordance with some embodiments.

Fig. 29 is a block diagram of a signal module generated by a signal factory module according to some embodiments.

FIG. 30 is a block diagram of a display module for displaying one or more signals according to some embodiments.

FIG. 31 is a block diagram of a monitoring module for performing error checking according to some embodiments.

Fig. 32 illustrates an example adjustment to the sweep speed of a display module, according to some embodiments.

FIG. 33 illustrates signal management for a display module according to some embodiments.

FIG. 34 illustrates example adjustments of the zoom and clipping factors for a display module, according to some embodiments.

FIG. 35 illustrates mode search management for a display module, according to some embodiments.

FIG. 36 illustrates a highlighted late potential search result in a display of a display module according to some embodiments.

Figure 37A illustrates the use of a display module configured as a waterfall view in accordance with some embodiments.

Fig. 37B illustrates a correspondence between signals in a conventional display module and a display module configured as a waterfall view, in accordance with some embodiments.

FIG. 37C illustrates the use of a display module configured as a dynamic view in accordance with some embodiments.

FIG. 37D illustrates using a display module configured as a trigger view in accordance with some embodiments.

Fig. 38 illustrates signal capture in a display of a display module configured as a review window, in accordance with some embodiments.

FIG. 39 illustrates amplitude measurements performed in a display of a display module configured as a review window, in accordance with some embodiments.

FIG. 40 is a flow diagram of a method for near real-time processing and display of multiple signals, according to one embodiment.

Fig. 41 is a flow diagram of a method for configuring one or more signal modules according to some embodiments.

Fig. 42 is a flow diagram of a method for generating a signal module according to a signal processing specification, according to some embodiments.

Fig. 43 is a flow diagram of a method for equalizing processing delays associated with each DSP of one or more signal modules, according to some embodiments.

Fig. 44 is a flow diagram of a method for receiving one or more signal samples for one or more signals using an input module, according to some embodiments.

Fig. 45 is a flow diagram of a method for converting one or more signal samples into one or more packets using a packetizer in accordance with some embodiments.

Fig. 46 is a flow diagram of a method for distributing packets containing one or more signal samples to a queuing module according to some embodiments.

Fig. 47 is a flow diagram of a method for distributing packets from a queuing module to a signal module associated with the packet according to some embodiments.

Fig. 48 is a flow diagram of a method for processing a packet using a signal module associated with the packet, according to some embodiments.

FIG. 49 is a flow diagram of a method for displaying processed packets to a display screen using a display module, according to some embodiments.

Fig. 50 illustrates an example of a signal with superimposed noise, in accordance with some embodiments.

FIG. 51 illustrates an example of a conventional method of removing noise using a notch filter, according to some embodiments.

Fig. 52 illustrates an example of the result of applying the conventional filter of fig. 51, in accordance with some embodiments.

Fig. 53 illustrates an example of a 180Hz harmonic that is still present at the output of the conventional filter of fig. 51, in accordance with some embodiments.

FIG. 54 illustrates an example of notch filtering for signals with 60Hz and 180Hz noise, according to some embodiments.

Fig. 55 illustrates an example of a notch filter using 100 samples and storing exactly 3 60Hz cycles, according to some embodiments.

Fig. 56 illustrates an example of a notch filter calculating a silence time, in accordance with some embodiments.

Fig. 57 illustrates an example of a notch filter that accumulates copies of noise and subtracts the noise copies from the noise signal, in accordance with some embodiments.

FIG. 58 illustrates an example of the results of a notch filter according to some embodiments.

Fig. 59 is a flow diagram of a process for notch filtering noise from an input signal, according to some embodiments.

Fig. 60 illustrates an example of a conventional high pass filter according to some embodiments.

Fig. 61 illustrates an example of a signal containing high frequency signals from conductive regions of the heart and sharp local spikes from various sources, in accordance with some embodiments.

Fig. 62 illustrates an example of a resulting output of filtering the signal of fig. 61 using the high pass filter of fig. 60, in accordance with some embodiments.

FIG. 63 illustrates an example of a resulting output of filtering the signal of FIG. 61 using a high pass filter that allows the high frequency signal of interest to pass while removing pulses, in accordance with some embodiments.

FIG. 64 is a flow diagram of a process for high pass filtering noise from an input signal according to some embodiments.

FIG. 65 illustrates an example of a review window for selecting a data range using vertical calipers, according to some embodiments.

Fig. 66 illustrates an example of saving a selected pattern as a reference heart beat, according to some embodiments.

FIG. 67 illustrates an example of a window of selectable modes to be searched, according to some embodiments.

FIG. 68 illustrates an example of a pattern search summary view in the review window of FIG. 65 in which multiple matching patterns are displayed, in accordance with some embodiments.

FIG. 69 illustrates an example of a pattern search summary view in the review window of FIG. 68 with a single matching pattern displayed and other patterns hidden in the review window of FIG. 68, in accordance with some embodiments.

FIG. 70 illustrates an example of a detailed view of the review window of FIG. 65 in accordance with some embodiments.

FIG. 71 illustrates an example of a pattern matching confidence value provided by a lead (lead), in accordance with some embodiments.

Fig. 72 is a flow diagram of a process for pattern matching according to some embodiments.

Fig. 73 is a flow diagram of a process for pattern matching according to some embodiments.

Fig. 74 illustrates an example of a search definition window for creating and managing searches for late potentials and early activations, in accordance with some embodiments.

Fig. 75 illustrates an example of a late potential detection configuration window for various search parameters that define a late potential, in accordance with some embodiments.

Fig. 76 illustrates an example showing the location of late potentials and their confidence of detection, in accordance with some embodiments.

Fig. 77 illustrates an example of an early activation detection configuration window for defining various search parameters for early activation, in accordance with some embodiments.

Fig. 78 illustrates an example showing locations of early activations and their detection confidence, in accordance with some embodiments.

Fig. 79 illustrates an example of a search definition window for managing defined late potential searches and early activation searches, in accordance with some embodiments.

Fig. 80 is a flow diagram of a process for detecting early activation or late potential according to some embodiments.

Figure 81 illustrates an example of a waterfall display configuration window according to some embodiments.

Figure 82 illustrates an example of a waterfall view using a time pattern, according to some embodiments.

Fig. 83 illustrates an example of a waterfall view using a heart beat pattern, in accordance with some embodiments.

FIG. 84 illustrates an example of a display parameter window according to some embodiments.

FIG. 85 illustrates an example computer system according to some embodiments.

The features and advantages of the present embodiments will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.

Detailed Description

Devices, systems, and methods related to unique amplifier topologies are disclosed for conditioning the heart (e.g., ECG and IC) and other physiological signals, particularly for clearly defining and recording low amplitude, low frequency information that may be obtained during ablation and other similar large signal perturbations such as pacing and stimulation. During surgery, the tip of the catheter (or other electrode) may be connected to a pacing, ablation and stimulator system to allow visualization, pacing, ablation and stimulation without mode switching. For example, the disclosed devices, systems, and methods may effectively separate an ablation signal from a cardiac signal during ablation while providing input protection against high voltages, such as from a defibrillation signal. Similarly, the disclosed devices, systems, and methods can effectively separate the stimulation signal from the physiological signal during stimulation.

Since different system recording requirements cannot be met simultaneously for each signal type, each block or module of the system can be performance optimized to achieve the various signal conditioning requirements desired by the clinician. Various embodiments may enable the system to simultaneously treat the heart, pace, ablate, defibrillate, stimulator, and other physiological signal types by detecting, adjusting, and displaying signals of interest to monitor, for example, the effect of an ongoing procedure on the cardiac signal.

Additionally, various embodiments may ensure that multiple low amplitude cardiac signals are acquired in the presence of many sources of electrical noise and environmental interference in addition to the large signals injected during ablation and stimulation surgery, pacing, or defibrillation. The cardiac signal of interest can also be displayed in an uncomplicated and clinically relevant manner, processing the signal in real time or near real time to display the overall causal relationship between the physician-initiated procedure and the resulting cardiac signal, while identifying signal artifacts and removing unnecessary noise. The present disclosure identifies hardware and software embodiments that achieve these objectives.

The present disclosure relates to "unipolar" and "bipolar" signals, both of which are widely used in EP recording, but for supplemental purposes. Both unipolar and bipolar signals are derived from potential differences recorded at two (or more) different, separate electrodes on the patient's body, in particular the patient's limbs and chest, for example for measuring ECG signals, or from potential differences recorded at two (or more) different, separate catheters placed directly on the heart tissue, for example for measuring IC signals.

It is conventional to use a 12-lead electrocardiogram system which includes connections to each of the following limbs: right Arm (RA), Left Arm (LA), Right Leg (RL) and Left Leg (LL), and six precordial connections V1-V6 from six separate electrodes located at different positions of the patient's chest, respectively. Individual ECG electrode wires are connected to clips at the end of the patient bed, from where they are routed to the data acquisition system. All leads are conventionally connected to protection circuitry to prevent damage to the meter due to defibrillation potentials or static electricity from the environment.

Bipolar signals are a standard configuration for certain ECG measurements (leads I, II, III), but IC signals can also be collected directly from the surface of the heart. Bipolar signals may be obtained by attaching two (or more) electrodes in close proximity in a particular region of the heart or heart tissue and measuring the potential difference between the electrodes, providing information about local electrical activity (such as late potentials caused by damaged myocardium). However, bipolar IC signals do not provide information about the direction of propagation of the electrical pulses. For example, one of the difficulties with current bipolar mapping (mapping) is that it is not possible to know whether the signal of interest is from a distal or proximal electrode. This is important because pacing and energy delivery is provided by means of the distal electrode.

By placing one IC electrode on the surface of the patient's heart and the other electrode at a distance from the first electrode as a reference signal, a unipolar signal is generated from a point source, such as may be obtained from the IC potential. The unipolar leads from the IC electrodes are connected such that one lead acts as the active lead while the other lead(s) are at the result of the inactive or calculated inactive position (WCT, described below). Thus, the current flowing to the movable electrode produces a positive deflection, while the current flowing away from the movable electrode produces a negative deflection. This provides information about the direction of propagation of the cardiac signal. Unipolar recordings are particularly useful when directional information is required, such as in determining the depolarization and repolarization pathways of the endocardium and epicardium. Methods of using the first derivative of two unipolar signals are disclosed herein.

Leads may also be connected to the limbs to create imaginary triangles, called "Einthoven's triangles". In this way, a true bipolar lead can be obtained by referencing each connection to one of the other two connections (e.g., LA to RA for I; LL to RA for II, and finally LA to LL for III). The average of the three limb leads RA, LA and LL may then be approximated to a point of zero potential to provide a reference electrode (WCT, discussed below). Here, the vector sum of I lead and III lead is II lead.

Using the concept of Einthoven's triangle, Wilson Central Terminal (WCT), which is a circuit concept used in the art (and discussed further in this disclosure), may be used as a neutral electrode, serving as the electrical center of the heart as a reference. WCT may be used when the IC signal is intended to be displayed in a unipolar manner. When using WCT as a reference for the unipolar signal, the unipolar signal can approximate a widely spaced bipolar signal for consistent unipolar recording. The WCT may prevent having to use an additional catheter as a reference for unipolar recording of IC signals.

In the present disclosure, "near real-time" refers to the acquisition and visualization of signals by the EP system from the time they appear at the input of the EP system's hardware circuitry to the time they are first displayed on the EP system display monitor, the signals being displayed in raw (unprocessed) form or after processing by the EP system Main Processing Unit (MPU) and one or more Digital Signal Processing (DSP) modules. The "near real time" for the original signal may be less than about five (5) milliseconds, and the "near real time" for the processed signal may be less than about fifty (50) milliseconds.

Fig. 1 is a block diagram illustrating a conventional EP environment 100 with patient connections and interference sources. As understood by one of ordinary skill in the art, the patient 118 may be connected to diagnostic equipment such as a pulse oximeter 104, one or more ECG units 106, an infusion pump 108, an electroanatomical mapping system 110, a data acquisition system 112 (such as the EP system disclosed herein), an ablation generator 114, a neurostimulator 128, and other diagnostic equipment (such as an external defibrillator) as well as several IC catheters. Such diagnostic equipment may be connected to and powered by 120-240V, 50/60Hz AC mains 102. The laboratory diagnostic equipment may be connected to ground 120 by means of its power supply connection.

As the number of connections to the patient 118 increases, the leakage current 122 from all patient connections through the patient 118 to the ground 120 increases, thereby increasing the likelihood of interference and adverse effects. When such devices are connected simultaneously and operated simultaneously, the total leakage current 122 may safely allow up to tens of microamps in the case of a fundamental mains frequency of 50Hz or 60Hz, with harmonics extending to several kilohertz. This leakage current 122 may substantially interfere with the processing of ECG and IC signals. In addition, the patient 118 may be capacitively 124 and inductively 126 coupled 120/240 with AC mains 102. The patient 118 may additionally pick up RF interference 116 from equipment proximate the EP environment (e.g., wireless headsets, mobile phones, and wireless monitors).

For reference, table 1 summarizes desired and undesired signals found in a conventional medical meter/EP environment, as well as their signal characteristics.

Table 1: signal characterization in conventional EP environments

Due to equipment noise and other EP environmental disturbances, the measured voltage on the patient's body may be as high as 1-3V RMS (root mean square) in the spectral range of 50Hz to tens of megahertz. However, the amplitude of the cardiac signal may be measured in the range of 25 microvolts to 5 millivolts. To display these signals in a noisy environment, the cardiac signal is conventionally amplified and displayed while delivering, for example, RF ablation energy at a frequency of 500kHz, at about 70V RMS, or providing cardiac stimulation of up to 25mA, without losing detail (so that, for example, no relevant information is lost) and with very little noise added (so that, for example, the details of the signal are not masked).

For proper acquisition and identification of cardiac signals of interest in such environments, a very high signal-to-noise ratio (SNR) is desired (about 30dB), but cannot be achieved without methods to minimize or eliminate electrical interference sources before they must be electrically processed by software methods. Conventional hardware approaches for conditioning signals in such noisy environments include shielded cables, equipment grounding, balancing inputs and outputs, differential amplification, filtering, reducing circuit impedance, electrical isolation, or signal enhancement techniques. These conventional methods have had limited success in achieving adequate SNR.

The disclosed hardware embodiments can reduce interference while applying novel circuit topologies to minimize noise, isolate IC and ECG signals of interest, condition those signals, and remove unwanted artifacts. This can be done before passing the signal to the processing software, which provides near real-time visualization and comprehensive signal review to the electrophysiologist. Embodiments of the EP system described herein may achieve substantial SNR improvements.

Fig. 2 is a hardware system block diagram representing a disclosed EP hardware system 200, the EP hardware system 200 including, for example, an EP workstation 201 and an EP console 214, in accordance with some embodiments. The system may include an EP console 214, the EP console 214 having an optical interface 216 to EP measurement hardware from a user input, visualization and review workstation (herein "EP workstation" 201). The EP workstation 201 may include, for example, a conventional laboratory PC 208 having a keyboard/mouse 210 and a monitor dispatcher 206, the monitor dispatcher 206 facilitating the multiple monitors 202, 204 to provide a multi-signal, multi-context display capability for EP signal visualization and review software. The EP workstation 201 may also include an additional optical interface 212 for electrically isolated data transfer from the EP console 214, for example, over USB 2.0.

The EP console 214 may include one or more ECG amplifiers 218, one or more unipolar amplifiers 220 for processing unipolar signals, and one or more bipolar amplifiers 222 for processing bipolar signals from a plurality of ECG and EGM monitoring units 224. The EP console 214 may also include a dedicated AC input filter 234, an AC/DC power supply 236, and a DC/DC power supply 238 to condition and convert the mains 120/240V, 50/60Hz source power 240 into DC power for use by diagnostic equipment. ECG and EGM electrode inputs 232 may enter the EP console 214 via a deflection coil (yoke)226, the deflection coil 226 providing additional input impedance for protection. Junction boxes (1 and 2)228, 230 may provide a convenient plug-in interface for IC conduit inputs (not shown) for subsequent processing by EGM monitoring unit 224.

Fig. 3 is a block diagram of a multi-channel analog-to-digital input/output module 300 representing an EP hardware system input stage, including an ECG board 302 and an IC board 316, according to some embodiments. The ECG board 302 and the IC board 316 represent a portion of the ECG amplifier 218, the unipolar amplifier 220, and the bipolar amplifier 222 of fig. 2. The ECG board 302 and the IC board 316 include a plurality of EP hardware system input stage 400 channels (see fig. 4) discussed below. Fig. 3 illustrates one (1) 8-channel ECG board and one (1) multi-channel IC board according to an exemplary embodiment. Some embodiments have at least sixteen (16) channels. Other embodiments may include more or fewer channels.

In fig. 3, the analog inputs V1-V6304 represent six separate ECG (precordial) electrodes that may be placed at various locations on the patient's chest. Analog inputs LL, RA, and LA 306 represent the left leg, right arm, and left arm limb leads, respectively. The analog output RL 308 represents the patient return line for driving the right leg as discussed later in this disclosure. WCT 314 (also discussed later in this disclosure) on ECG board 302 represents a wilson central terminal that also uses analog inputs LL, RA, and LA 306. The output of the WCT 314 may then be input to each channel in the EP hardware system input stage 400 corresponding to the analog inputs V1-V6304. Each of the digital outputs V1-V6310 represents an adjusted and digitized version of the corresponding analog input V1-V6304. In one exemplary embodiment, digital output I, II 312 may include in conditioned and digitized form LA reference to RA as lead I and LL reference to RA as lead II. The average of the three limb leads LL, RA and LA 306 may then be approximated as a point of zero potential, thereby providing a reference level for the generation of RL 308.

In fig. 3, the multiple analog inputs of IC board 316 represent possible connections and channels from the intracardiac catheter to EP hardware system input stage 400 (see fig. 4). The IC board 316 may accept either unipolar or bipolar IC signals. INDIF 318 represents a neutral electrode that provides a reference for a plurality of unipolar neutral leads. Signal 320 of ICUniWCT1, 2 through N represents the unipolar IC signal of the reference WCT. Signal 322 for ICUniINDIF1, 2 through N represents the active electrode for each IC unipolar signal. ICDiff1, signals 324 for 2 through N represent a plurality of bipolar differential signals from the IC conduits. The multiple digital outputs represent conditioned and digitized versions of the analog input, specifically ICUniWCT1, 2-to-N signal 326; ICUniINDIF1, 2-to-N signal 328; and ICDiff1, 2 through N signal 330.

Fig. 4 is a block diagram representing a single channel of an EP hardware system input stage 400 with circuitry for input protection, signal filtering, detection, feedback, and amplification, according to some embodiments. The circuitry is represented in the block diagram by blocks numbered 1 through 11, each representing a portion of a hardware function. This division and marking of the blocks is for ease of description and is not intended to limit the scope of protection afforded by the appended claims. As described below, the input protection and signal filtering section of EP hardware system input stage 400 includes symmetric positive and negative circuitry to generate a differential version of each input signal for differential signal amplification stage 532.

Fig. 5A is a block diagram 500 of the overall EP system disclosed herein, generally illustrating an interface of a Main System Unit (MSU) (hardware component) 504 to a Main Processing Unit (MPU) (software component) 514, in accordance with some embodiments. Fig. 5A will be discussed in more detail later in this disclosure.

Fig. 5B is a block diagram 524 showing the main sections of the EP hardware system input stage 400, with sections 530, 532, 534 cross-referenced to the sections shown in the EP hardware system input stage 400.

In fig. 5B, analog input protection/filtering stage 530 includes block 1-input protection 402a, block 2-RF filter 404a, block 3-buffer 406a, block 4-DC block 408a, block 10-low frequency feedback 420a, and block 11-mask driver 422 a. The symmetrical negative circuitry includes block 1-input protection 402b, block 2-RF filter 404b, block 3-buffer 406b, block 4-DC block 408b, block 10-low frequency feedback 420b, and block 11-mask drive 422 b. The signal amplification stage 532 includes differential circuitry including block 5-instrumentation amplifier/filter 410, block 6-differential amplifier 1/filter 412, block 7-differential amplifier 2/filter 414, and block 9-large signal detection/fast recovery 418. The a/D converter stage 534 includes a block 8-a/D converter 416. The a/D converter stage 534 also includes a communication module 510 (shown in fig. 5A), the communication module 510 being capable of formatting signals for transmission over the fiber optic link 512 to a digital processing stage 528, which in some embodiments is represented by MPU 514.

The functionality of the particular blocks 1-11 of fig. 4, the single channel of the EP hardware system input stage 400, is described in the following paragraphs.

Analog input protection/filtering stage

The analog input protection/filtering stage 530 of the EP system shown in fig. 5B includes blocks 1-input protection 402a, 402B; block 2-RF filters 404a, 404 b; block 3 — buffers 406a, 406 b; block 4-DC blocks 408a, 408 b; block 10 — low frequency feedback 420a, 420 b; and block 11-mask drivers 422a, 422 b. These elements according to some embodiments are described in more detail in the following paragraphs.

Input protection circuit system

Fig. 6A, 7 and 6B illustrate circuits including an analog input protection/filtering stage 530 of the disclosed EP system, in accordance with some embodiments. Fig. 6A illustrates overvoltage protection circuitry 600 (represented in fig. 4 by blocks 1(402a, 402 b)), which overvoltage protection circuitry 600 can protect other EP hardware system input stage 400 circuits from large transient voltages, such as defibrillation pulses in particular. The analog input protection/filtering stage 530 may prevent the input voltage from exceeding the range that the circuit can actually handle.

Specifically, the analog input protection/filtering stage 530 may reduce high voltage transients at the input of the ECG, IC, and other electrode leads connected to the patient's body to less than ten (10) volts, for example, at the input of the EP system buffer. The analog input protection/filtering stage 530 may prevent large signals, such as from a defibrillator, from damaging other portions of the system. Additionally, the analog input protection/filtering stage 530 may perform these functions without absorbing, for example, more than 10% of the energy of the applied defibrillation pulse, without clamping, or without adding non-linearity when applying the ablation signal.

Fig. 6A illustrates one exemplary embodiment of the overvoltage protection circuitry 600 of block 1, the overvoltage protection circuitry 600 including an off-the-shelf gas tube (GDT)608, the gas tube 608 may be ignited at very high voltages, such as voltages above 300V, to provide high voltage surge protection. The GDT 608 is coupled to two stages of diodes 610, 612 (and resistors 602, 604) designed to clip (clip) the signal sequentially to 18V, for example removing defibrillation signals up to 5000V, for example. Diode 610 represents an off-the-shelf electrostatic discharge (ESD) voltage suppressor device that may assist GDT 608 until GDT 608 is fully conductive. Diode 612 represents an off-the-shelf bidirectional ESD protection diode that may limit the In2 input of the RF filter (block 2) to 18V at the node labeled (a) In fig. 6A and 7.

Conventionally, a defibrillation signal of about 5000V will clamp to +/-5V to prevent injury. With the present disclosure, the defibrillation signal may be similarly clamped, but an ablation signal having an ablation voltage of about 200V, for example at 500kHz, may be passed linearly and attenuated by the input resistors RCable, 602, 604 and block 2 (fig. 4, 404a, 404b), the RF filter 702.

Fig. 7 illustrates an RF filter/shield driver 700, the RF filter/shield driver 700 including an RF filter 702 and a shield driver 730. The RF filter/shield driver 700 is connected to the overvoltage protection circuitry 600 of fig. 6A at a node labeled (a) for passing a signal In12 through the analog input protection/filtering stage 530. The RF filter 702 of the RF filter/shield driver 700 is described in more detail below. Shield drive 730 of RF filter/shield drive 700 is also described below.

The input overvoltage protection circuitry 600 does not clamp the ablation signal; instead, the ablation signal is linearly attenuated (e.g., by the input resistances RCable, 602, 604 and RF filter 702 being proportionally reduced) so that it is not inadvertently altered. For example, if an ablation signal is clamped by the input overvoltage protection circuitry 600, there will be no access to the content of that signal beyond the clamping. Advantageously, the linear attenuation of the ablation signal by the disclosed EP system may allow recording of small cardiac signals of a few millivolts during ablation. One of ordinary skill in the art will appreciate that the apparatus, systems, and methods disclosed herein apply similarly to other high frequency signals that may need to be passed through a protection circuit (e.g., unclamped) to prevent generation of non-linearities that would affect the signal of interest.

Fig. 6B shows ESD input protection circuitry 620 at the last section of analog input protection/filtering stage 530. ESD input protection circuitry 620 is coupled to RF filter/shield driver 700 at the node labeled (b) of fig. 7. The ESD protection chip 622 may provide ESD protection for the data lines up to 30kV and may respond to overvoltage conditions in nanoseconds. Any number of off-the-shelf ESD protection devices may be used for this purpose.

Transient Voltage Suppressor (TVS) diodes 628, 630 may provide ESD protection in excess of 16kV by shunting excess current when the induced voltage exceeds its breakdown voltage. The TVS diodes 628, 630 may act as "clamping" or limiting devices to suppress overvoltages that exceed their breakdown voltage and may automatically reset when the overvoltage subsides. The TVS diodes 622, 630 may also respond to overvoltages faster than other common overvoltage protection components; for example, "clamping" occurs within about 1 picosecond. TVS diodes generally have the advantage of preventing very fast and potentially damaging voltage transients.

Fig. 8A-8E and 9A-9E illustrate sample signal diagrams demonstrating how the front-end input protection circuit handles high voltage transients and ESD, according to an example embodiment. Fig. 8A illustrates the voltage v (defib) of a representative defibrillator signal applied to the input of the input protection circuit labeled "EP signal" in fig. 6A. In a laboratory setting, the defibrillator signal may be obtained by applying 5000 volts to a 32 μ F capacitor, and then discharging the capacitor to a connected electrode on the patient. Due to inductance and resistance, the amplitude received at the electrodes is approximately 4500 volts, lasting tens of milliseconds.

Fig. 8B-8E illustrate different voltage levels as the defibrillation signal progresses through the circuit. V (in) of fig. 8B is the voltage on GDT 608 of fig. 6A. The GDTs have very low capacitance (e.g., less than 1pF) and high impedance (e.g., greater than 100MOhms) in the off state. They act as a gap between the two electrodes. When GDTs ionize and conduct, they can have very low resistance (e.g., a few ohms) and have large current carrying capacity (e.g., carrying tens of amperes of current); thus, they act as a short circuit. One disadvantage of GDTs, as shown in the graph for v (in) in fig. 8B, is that they may take some time to turn on. The GDTs should trigger at 230V but the voltage will rise to a higher level before they can effectively turn on and begin conducting. The on-time may be several hundred nanoseconds. The resistor RCable in FIG. 6A limits the current flowing into GDT 608. This may reduce the power consumed in the system and may also ensure that the analog input protection/filtering stage 530 does not shunt any appreciable power for the patient.

ESD voltage suppressor diodes 610 in fig. 6A may turn on faster (e.g., within one nanosecond), but have a lower power/energy capacity so that they can activate quickly. As shown in the signal diagram for V (P1) in fig. 8C, when the GDTs 608 are fully on, they can hold the voltage at P1 to about 30V. When GDT 608 is fully turned on, ESD voltage suppressor diode 610 is no longer active.

The next stage In fig. 6A is an ESD protection diode bidirectional pair 612, which can limit the signal at In12 (the input to the RF filter (block 2)) to about 18V, as shown In the signal diagram for V (In12) In fig. 8D. The signal passing through the RF filter will be further described in the RF filter (block 2) section below.

Finally, as shown In fig. 6B, at In13, after the signal has been filtered by the RF filter of block 1, ESD protection chip 622 may clip the signal at VDD by +/-diode drop (e.g., +/-5.7 volts) as shown In the signal diagram for V (In13) of fig. 8E.

Those of ordinary skill in the art will appreciate that the combination of input protection circuitry shown in fig. 6A and 6B, including GDT 608, diode 610, diode 612, ESD protection chip 622, and TVS diodes 628, 630, protects the circuitry of the EP recording system. However, the circuitry itself may be detrimental to achieving high quality EP recording during ablation. For example, if the ablation signal is clipped, the resulting non-linearity can cause noise and mask the cardiac signal of interest. Since the medical team may wish to see the cardiac signal during ablation, the integration of the RF filter of block 2 with the input protection circuitry is an improvement over conventional solutions. The disclosed embodiments allow for unwanted and potentially destructive or damaging signal attenuation while linearly filtering the ablation signal and monitoring the ECG and IC signals.

For example, fig. 9A-9E are signal diagrams illustrating progression of an ablation signal through the input protection circuit of fig. 6A, 7, and 6B. As shown by curve v (defib) in fig. 9A, the ablation input at the sensor electrode is 400 Vpp. As the signal travels through the stages of the input protection circuit, the signal is attenuated by resistor RCable (as shown by curve V (In) of fig. 9B), resistor 602 (as shown by curve V (P1) of fig. 9C), resistor 604 (as shown by curve V (In12) of fig. 9D), and capacitor 716 (as shown by curve V (In13) of fig. 9E). The ablation signal voltage level is 100Vpp at node In of fig. 6A, 12Vpp at node In12 of fig. 6A, and 60mV at node In13 after the RF filter of fig. 7. The ablation signal does not trigger the protective device, but is linearly attenuated, allowing observation and/or recording of the cardiac signal during ablation. The ablation signal may be further filtered at each of blocks 5, 6 and 7 (see fig. 4, 5B and 10) of the signal amplification stage 532 and at the a/D converter (block 8 in fig. 4) with a 100dB low pass filter at 950 Hz.

RF filter circuitry with low frequency feedback and shield drive

In addition to contributing to the input protection circuitry to filter and linearly attenuate the ablation signal at the EP system input, the RF filter 702 may also work in conjunction with the low frequency feedback circuitry of block 10 (see fig. 4, 420a and 420b, and fig. 16, 1600) to enable the overall circuit to continue to linearly attenuate the ablation signal (e.g., having a voltage amplitude of about 200V in the frequency range of about 300kHz to about 600 kHz) in near real time during cardiac monitoring, while, for example, passing small cardiac signals (e.g., having a frequency range of about 0.01Hz to about 500 Hz).

The RF filter 702 may be designed to linearly attenuate the amplitude of the ablation signal by at least 75% in some embodiments, or even by at least 90% in other embodiments, for example. For example, the RF filter 702 may be designed to provide substantially no attenuation of input signals having frequencies less than 5 kHz. The RF filter 702 may also work in conjunction with a shield drive 730 (see fig. 4, 422a and 422b and fig. 7) of the block 11, the shield drive 730 may work in conjunction with the input capacitors 706, 714, 716 of the RF filter 702 to help maintain a high input impedance for the overall circuit. This high input impedance may help minimize input losses of the cardiac signal of interest. The shield drive 730 is discussed further below.

Low frequency feedback circuit

The low frequency feedback circuit 1600 of block 10 (see fig. 4, 420a and 420b) may provide positive feedback to the RF filter of block 2 (see fig. 4, 404a and 404b and fig. 7, 702) to increase the input impedance to the EP system, thereby reducing signal attenuation. This is advantageous because the input impedance of the EP system in the frequency range of the cardiac signal may be compromised by the RF filter 702.

In particular, the high input impedance at instrumentation amplifier 1001 of fig. 10 may be significantly reduced by the presence of RLC network elements 706, 708, 714, 716 of RF filter 702 depending on the frequency of the input signal (e.g., 100 times at 60 Hz). Although the RF filter 702 is advantageous at ablation frequencies, the reduction in impedance at low frequencies may reduce the amplitude of the cardiac signal and affect common mode rejection. Without mitigating the effects of the RF filter 702, the advantages of the instrumentation amplifier 1001 would otherwise be lost.

To mitigate this loss and maintain high common mode rejection (e.g., on the order of 100 dB), it is desirable to maintain high impedance at the power line frequencies so that variations in the source impedance do not convert common mode signals to differential signals. Block 10, the low frequency feedback circuit 1600 shown in fig. 16 receives buffered versions of the signal of interest from the buffers 406a, 406b of block 3 as Buf 11602. The low frequency feedback circuit 1600 then applies an operational amplifier 1606 to drive Shield1 (Shield 1)728 at the bottom (i.e., bottom plate) of the capacitors 706, 714, 716 in the RF filter 702. In particular, the operational amplifier 1606 acts as a driver to eliminate load effects and maintain a high input impedance of the analog input protection/filtering stage 530 into the signal amplification stage 532.

When the low frequency feedback circuit 1600 of block 10 drives the RF filter 702 at a low frequency, there is little or no change in the voltage across the capacitors 714, 716. Thus, at low frequencies, the capacitors 706, 714, 716 act as an open circuit and maintain a high input impedance. But at higher frequencies the feedback from the low frequency feedback circuit 1600 of block 10 is reduced due to the low pass filtering function of block 10.

Specifically, the combination of capacitor 1666 and resistor 1693 at the inverting input of operational amplifier 1606 filters high frequencies. The output of this circuit no longer tracks the input and Shield 1728 (also the reference node of RF filter 702) is held at a fixed level with respect to high frequency signals. This enables the passive RLC networks 706, 708, 710, 712, 714, 716 of the RF filter 702 to attenuate high frequency signals.

Specifically, the block 10 low frequency feedback circuit 1600 (see fig. 4, 420a and 420b) takes the buffered signal from the block 3 buffer circuit (see fig. 4, 406a and 406b) and generates a correction signal to Shield 1728 of fig. 7, i.e., the equivalent input is at capacitors 706, 714, 716 (see fig. 4, 404a and 404b) of the RF filter 702 of block 2 as the feedback signal. This feedback to the capacitors 706, 714, 716 is provided as a dynamic current source for the circuit.

The RF filters 702 of blocks 2404 a, 404b are enabled for high frequency filtering, but when feedback is received from the low frequency feedback circuit 1600 of blocks 10420 a, 420b, the RF filters 702 are disabled at low frequencies. At high frequencies, the capacitors 706, 714, 716 in the RF filter 702 act as shunt capacitors effectively short-circuiting the signal at RF frequencies. The impedance of the capacitors 706, 714, 716 decreases linearly as the frequency becomes higher. The low frequency feedback circuit 1600 does not affect the EP system at high frequencies.

At low frequencies, the low frequency feedback correction signal Shield 1728 from block 10 (see fig. 16) to block 11 (Shield drive 730 of fig. 7) drives the lower plates of the capacitors 706, 714, 716 so that these capacitors mimic the input signal. This controls the reference node of the RF filter 702. Specifically, the voltages at the plates of the capacitors 706, 714, 716 vary in synchronization with each other, and the low frequency feedback circuit 1600 drives the lower plates of the capacitors 706, 714, 716 of the RF filter 702 to the same voltage as the upper plates, so that the voltage difference at the plates of the capacitors 706, 714, 716 becomes zero, and the capacitors 706, 714, 716 act as an open circuit.

The goal of the low frequency feedback is to drive the difference between Shield 1728 and Buf11602 to zero, so that Shield 1728 equals Buf 11602. When this occurs, the input capacitance can be eliminated. At high frequencies, the positive feedback from the operational amplifier 1606 is reduced to zero. Additionally, at high frequencies, capacitor 722 (e.g., which is 30 times larger than the other capacitors in the circuit) serves as a short between Shield 1728 and ground. This effectively grounds the reference node of the RF filter 702, thereby completely enabling it to attenuate RF frequencies. Thus, the block 10 low frequency feedback circuit 1600 works in conjunction with the unique arrangement of the block 2RF filter 702 elements to remove the loading effects of the RF filter 702 before passing the signal to the block 5 instrumentation amplifier 1001.

In this manner, instrumentation amplifier 1001 may condition the cardiac signal without overlaying the ablation signal. The result is that at low frequencies, the input to the entire circuit still sees a very high input impedance (e.g., on the order of tens of MOhms), which is advantageous for visualizing high fidelity cardiac signals in an EP environment. Additionally, block 10 is a symmetric (e.g., mirrored) circuit such that common mode noise is subtracted as the signal propagates through the circuit. Another advantage of the low frequency feedback circuit 1600 is that its output Shield 1728 can be used to drive the outer Shield of the input cable, for example at OutS1 of Shield drive 730 of fig. 7.

Shield drive circuit

Block 11 (see fig. 4, 422a and 422b), and in particular Shield drive 730 shown in fig. 7, receives the output (Shield 1728 of fig. 16) of low frequency feedback circuit 1600 of block 10 (see fig. 4, 420a and 420b) and provides positive feedback to the cable Shield at OutS1, thereby reducing the effective input capacitance of the input cable. Thus, the path from the lower plates of the input capacitors 714, 716 in the RF filter 702 of block 2 (see fig. 4, 404a and 404b) to the shielding of the input cable further helps to make the input impedance as large as possible. This high input impedance minimizes input loss of the cardiac signal of interest. In some embodiments, if shield driving is not desired, the shield drive connection is grounded.

Signal buffering and DC blocking circuitry

Block 3 (see fig. 4, 406a and 406b) is a low noise unity gain driver that helps to minimize the input loss of the cardiac signal. In particular, it may provide a high input impedance to minimize the loading of the input stage on the cardiac signal and to drive the signal amplification stage 532. In block 3, two operational amplifiers (circuits not shown) form two buffers that act as unity gain followers that buffer the input and provide a high input impedance for the input.

Block 4, the DC block (see fig. 4, 408a and 408b) is a high pass module (circuitry not shown) that prevents input offsets from the patient body's sensor/tissue interface from entering the amplifier gain stage. In block 4, two DC blocking capacitors (not shown) protect the input from large offsets from the catheter.

Signal amplification stage

The signal amplification stage 532 (see fig. 5B) of the EP system comprises a differential circuitry: block 5-instrumentation amplifier/filter 410, block 6-differential amplifier 1/filter 412, block 7-differential amplifier 2/filter 414, and block 9-large signal detection/fast recovery circuit 418. These circuits are described in more detail in the following paragraphs.

Instrumentation amplifier/filter circuit

Block 5 (see fig. 4, 410) is an instrumentation amplifier/filter that provides amplification for the differential signal and common mode rejection of unwanted signals from the equipment laboratory or medical environment, particularly power line noise and related harmonics. Block 5, detailed in fig. 10, has a gain stage 1001 with a differential gain of about 20 at its output and it provides additional filtering for RF attenuation by means of its RC network 1008, 1010, 1012, 1014. The two operational amplifiers 1006, 1016 are, for example, low-noise devices designed to receive the cardiac signal at the input of the instrumentation amplifier 1001 before the cardiac signal has been amplified. The differential signal from the block 5 instrumentation amplifier 1001 then enters the precision resistor block 1018 of the block 6 differential amplifier # 11017.

Differential amplifier/filter circuitry

Block 6 (see fig. 4, 412) has a differential amplifier 1020, the differential amplifier 1020 referencing a common mode voltage, producing a fully differential output with unity gain. Block 6 differential amplifier # 11017 may provide additional filtering for RF attenuation. Maintaining fully differential signal paths helps to reduce noise coming in from the digital portion of the system. Such noise appears mainly as common mode noise and is rejected. This portion of the signal amplification stage 532 also shifts the DC bias of the cardiac signal from 0 up to 2.5V and limits its output from 0 to 5V.

At the output of block 6 of the first fully differential amplifier 1020 with the reference common mode, the common mode level is set to 2.5V when the signal enters the block 7 differential amplifier # 21021. The circuit continues to low pass filter the ablation signal to the output of block 7 (B2OutP, B2 OutN). Block 7, which has a second fully differential amplifier 1034 similar to the differential amplifier 1020 of block 6, has a gain of approximately 0.5, with the circuit elements 1022, 1024, 1026, 1028, 1030, 1032, 1036, 1038, 1040, 1042 providing additional filtering of the RF attenuation. This portion of the signal amplification stage 532 maintains a fully differential signal path to continue to suppress noise.

The gain introduced by block 7 allows the circuit to clip the signal at the input limits of an a/D converter, block 8 (see fig. 4, 416), which may be, for example, a delta-sigma converter (not shown). As previously described, block 6 differential amplifier # 11017 clips each output signal to a bias level of +/-2.5 volts with respect to 2.5 volts. With a gain of 0.5, the output of the block 7 differential amplifier # 21021 produces a signal bias of 2.5 volts, with a range of +/-1.25 volts for each output, or a peak-to-peak difference of 2.5 volts. For example, in some embodiments, this represents a limit for the 24-bit A/D converter 416. By clipping and matching the output limits, the input to the a/D converter 416 is prevented from being overdriven. Since delta-sigma converters may exhibit irregular behavior when overdriven, possibly leading to spurious results, embodiments advantageously allow the full input range of the a/D converter, but not much.

The overall gain of the signal amplification stage 532 of the disclosed EP system may be, for example, less than or equal to 20 in some embodiments, or less than or equal to 50 in other embodiments. For example, in some embodiments, a gain of about 20 at the output of instrumentation amplifier 1001, a unity gain at the output of differential amplifier # 11017, and a gain of about 0.5 at the output of differential amplifier # 21021 yields a system gain of about 10 at the input of a/D converter 416. In general, the signal amplification stage 532 may include an instrumentation amplifier 1001 with a gain at its output greater than one (1), a differential amplifier # 11017 with a gain at its output of about one (1), and a differential amplifier # 21021 with a gain at its output less than one (1).

The overall low gain of the system provides a further improvement over conventional systems due to its improved ability to remove noise. Conventional systems with 16-bit a/D converters require high gain to visualize small signals that are obscured in the presence of high amplitude signals. Conventional systems may have a gain of, for example, up to 5000, resulting in signal saturation occurring rapidly. Furthermore, if a lower gain is used with a 16-bit converter, quantization noise can adversely affect the output result. With the disclosed system having a low gain of about 10, the system is coupled to a 24-bit a/D converter, saturation can be prevented until a small signal input of, for example, at least 250mV, and quantization noise is avoided.

Large signal detection/fast recovery circuit system

The output from block 6 differential amplifier # 11017, in addition to being passed to block 7 differential amplifier # 21021, is passed to block 9 (see fig. 4, 418 and 10), the large signal detection/fast recovery circuit 1100 of fig. 11. The large signal detection/fast recovery circuit 1100 may remove large signals and quickly recover from large transients. This circuit is referred to as a "fast recovery" circuit because its ability to recover from saturation is much faster than conventionally implemented.

In particular, the large signal detection/fast recovery circuit 1100 may detect that the differential input signal has exceeded 100mV for a duration of, for example, at least 10 milliseconds, which is identified as an abnormal operating range. Upon detection of this condition, the large signal detection/fast recovery circuit 1100 may reduce the time constant after the DC blocking stage of block 4 (see fig. 4, 408a, and 408b) to ensure that the cardiac signal does not remain saturated. However, the large signal detection/fast recovery circuit 1100 has a negligible effect under normal operation. For example, the large signal detection/fast recovery circuit 1100 may have no effect on fast transients generated by pacing, which may be the signal of interest to be monitored and recorded in an EP environment, and whose transient duration is typically less than 10 milliseconds.

In one embodiment, the first stage of the large signal detection/fast recovery circuit 1100 has, for example, two operational amplifiers 1108, 1112. The gain of the op-amp 1108 (e.g., approximately 40) determines the activation threshold, i.e., at which the large signal detection/fast recovery circuit 1100 may operate to limit (or "soft-clamp") the signal. The activation threshold determines how large the signal must be before the large signal detection/fast recovery circuit 1100 becomes active and begins to pull the voltages at nodes In14 and In24 toward the common mode level. For example, an operational amplifier 1108 having a gain of about 80 may activate the large signal detection/fast recovery circuit 1100 at about 50 mV; an operational amplifier 1108 with a gain of about 40 may activate the large signal detection/fast recovery circuit 1100 at about 100 mV; and an operational amplifier 1108 having a gain of about 20 may activate the large signal detection/fast recovery circuit 1100 at about 200 mV. When the signal amplitude reaches the set amplitude level determined by the gain, the voltage will be sufficient to overcome the activation threshold of the first pair of diode stages 1114, 1116 for activating the large signal detection/fast recovery circuit 1100.

Operational amplifier 1112 generates a unity gain to buffer the common-mode (CM) signal, which provides a common-mode reference for the signal passing through operational amplifier 1108. The operational amplifier 1108 receives the U4Out1 and U4Out2 signals from block 6 (see FIG. 10). Therefore, the average of the U4Out1 and U4Out2 signals are referenced to the common mode node (CMB of FIG. 11). The signal out of the operational amplifier 1108 passes through a first pair of diode stages 1114, 1116, the first pair of diode stages 1114, 1116 limiting the charging of the subsequent capacitors 1120, 1124, 1128, 1132. These capacitors 1120, 1124, 1128, 1132 accumulate charge from the buffered U4Out1 and U4Out2 signals, producing maximum positive (+) and negative (-) charge for inverted and non-inverted versions of the signals U4Out1 and U4Out 2.

Capacitors 1120, 1124, 1128, 1132 together with resistors 1118, 1122, 1126, 1130 form an RC network at nodes C, D, E and F that together act as a timing network that determines a time constant. The time constant determines the time at which the signal can be at its maximum amplitude before the large signal detection/fast recovery circuit 1100 pulls the voltages at nodes In14 and In24 toward CM. This RC network is referred to hereinafter as a "timing library" 1158. Some embodiments of the timing bank 1158 may be designed to produce a time constant of at least 10 milliseconds, for example to prevent activation of the large signal detection/fast recovery circuit 1100 during a pacing signal of, for example, 2 milliseconds to 10 milliseconds duration. Other embodiments may be designed to produce a time constant of at least five (5) milliseconds.

As the capacitors 1120, 1124, 1128, 1132 charge, a difference is detected and a signal is passed through the second pair of diode stages 1146, 1148, which second pair of diode stages 1146, 1148 limits (or "soft clamps") the input to approximately, for example +/-100 mV. This may prevent the system from saturating in any appreciable amount of time (e.g., less than 100 milliseconds). The second pair of diode stages 1146, 1148 also ensures that there is no interaction between the large signal detection/fast recovery circuit 1100 and the EP system if the size/length of the signal is not sufficient to require limiting. In other words, the second pair of diode stages 1146, 1148 disconnects the large signal detection/fast recovery circuit 1100 when it is not advantageous to activate the large signal detection/fast recovery circuit 1100. The block 9 large signal detection/fast recovery circuit 1100 ensures that the EP system is not affected by large signal spikes and allows for a steady state response where the difference between the inverted and non-inverted U4Out1 and U4Out2 signals is about 100mV, for example where the operational amplifier 1108 has a gain of, for example, about 40.

The block 9 large signal detection/fast recovery circuit 1100 is located in the EP system at a location for removing large signal voltage offsets. One of ordinary skill in the art will appreciate that the large signal detection/fast recovery circuit 1100 may be located in other locations in the EP system where potential large signal spikes may occur and are undesirable. Those of ordinary skill in the art will also appreciate that electronic components, such as capacitors 1120, 1124, 1128, 1132 and resistors 1118, 1122, 1126, 1130 of the timing bank 1158 may be replaced in the large signal detection/fast recovery circuit 1100 to change the circuit activation level and time. As will be appreciated by those of ordinary skill in the art, the large signal detection/fast recovery circuit 1100 may be used in various embodiments of other signal acquisition and processing systems to remove large signal voltage offsets from other types of electrical signals.

In some embodiments, the outputs In14, In24 of the block 9 large signal detection/fast recovery circuit 1100 (see fig. 4, 418) are fed back to the block 4, DC block (see fig. 4, 408a, and 408 b). The DC blocking capacitor (not shown) of block 4 adds an additional bias (e.g., a correction bias) back to the input signal. Thus, unless the signal fed into block 9 is large (e.g., having an amplitude on the order of about 100mV or greater), the signal from block 9 large signal detection/fast recovery circuit 1100 is not fed back into the block 4DC block. In other words, the output signal of block 9 is not passed to block 4 unless a large signal event occurs. The nodes In14 and In24 are normally disconnected.

Exemplary embodiments of the large signal detection/fast recovery circuit 1100 of fig. 11 are described in detail with respect to the signal diagrams of fig. 12, 13A-13C, 14A-14D, and 15A-15B. The sample signal is applied at the input to the EP system and is depicted at various points in the circuit. In this example, the signal shown to demonstrate the large signal detection/fast recovery circuit 1100 is generated by applying a 20mVpp signal at node In12 of fig. 6A and 7, and applying a zero input at node In22 (a symmetric negative node, not shown), specifically applying an input to the RF filter 702. At time 10 milliseconds, a 200mV step is added to the signal at node In 12. As the signal passes through the EP system, it becomes a 200mV differential signal, which can cause the signal to move out of the display range of most conventional monitoring devices. Such a 200mV signal should typically be removed so that the signal can be viewed in the EP environment.

Fig. 12 illustrates what happens to such an input signal if the large signal detection/fast recovery circuit 1100 is not connected. After the sampled input 20mVpp signal with the undesired 200mV step passes through the analog input protection/filtering stage 530, instrumentation amplifier 1001, and differential amplifier # 11017 to the large signal detection/fast recovery circuit 1100, the EP hardware system cannot recover quickly from the 200mV step signal if the large signal detection/fast recovery circuit 1100 is not connected. Such slow recovery complicates the identification of cardiac signals.

Resistors 1002 and 1004, located before instrumentation amplifier 1001 of fig. 10, eventually pull the offset signal back to ground, but a time constant of about 2.7 seconds is generated by the product of the DC blocking capacitor (not shown) of block 4 and resistor 1002. This introduced delay is too long to recover the off-screen or saturated signal. Fig. 12 illustrates that the signal at input node In14 does not move significantly downward In about 100 milliseconds, but only moves a few millivolts (not shown) In about 400 milliseconds. Without the large signal detection/fast recovery circuit 1100, such a large transient signal would likely adversely affect the operation of the EP system, as large transients would push the monitored signal into saturation and the waveform details of the signal would be lost.

Fig. 13A-13C illustrate the same 200mV large transient signal when using a connected large signal detection/fast recovery circuit 1100. In this example, as shown In fig. 13A and 13B, the two input nodes In14 and In24 (shown In fig. 11) of the large signal detection/fast recovery circuit 1100 are pulled (biased) toward the common mode signal v (cmb), which has an amplitude of about 100mV (see fig. 13C). In14 (the positive input node of large signal detection/fast recovery circuit 1100) is pulled down, and In24 (the negative input node of large signal detection/fast recovery circuit 1100) is pulled up. V (CMB) is the average of the voltages at nodes In14 and In22 (symmetrical negative inputs to the overall circuit). The actual common mode levels of nodes In14 and In24 have no effect because the required bias levels are applied directly to the differential amplifiers (1020 and 1034, respectively) of blocks 6 and 7, which will set the common mode voltages at those differential amplifiers 1020, 1034.

The graphs In fig. 13A and 13B illustrate that the voltages of nodes In14 and In24 were pulled into the monitoring range after about 50 milliseconds. The limiting or "soft clamping" is therefore performed gradually to avoid discontinuities in the signal acquisition and visualization. Other embodiments may allow for gradual "clamping" within about 100 milliseconds.

Fig. 14A-14D demonstrate how a large transient signal is conditioned as it passes through various internal nodes of the large signal detection/fast recovery circuit 1100. The signal curve v (a) of fig. 14A and v (B) of fig. 14B represent the output of the operational amplifier 1108 of the large signal detection/fast recovery circuit 1100 of fig. 11. In this example, operational amplifier 1108 has a gain of about 40 with respect to the input and produces a (40 × 200mV ═ 8 volt differential signal across nodes a and B in fig. 11.

As shown by curve v (C) of fig. 14C, after node B of fig. 11, the negative signal pulls down the voltage at node C of fig. 11. Here, the signal has been filtered to remove the in-band signal occurring at node B, leaving a low frequency control voltage at node C. The negative voltage at node C is connected to In14 through resistor 1140, diode 1150, and resistor 1144. This produces a current that pulls In14 down towards the common mode voltage, as shown In fig. 13A. Similarly, as shown by curve v (E) of fig. 14D, node a pulls In24 upward toward the common mode voltage through nodes E and J of fig. 11.

The diode in the large signal detection/fast recovery circuit 1100 of fig. 11 controls the direction of the current. The first pair of diode stages 1114, 1116 (current limiting diodes) allows for different time constants for charging and discharging nodes C, D, E and F. They also provide a non-operating range in which nodes C, D, E and F are not charged when outputs a and B are less than the diode forward voltage drop. The "clamping" diodes 1150, 1152, 1154, 1156 of the second pair of diode stages 1146, 1148 ensure that the input nodes In14 and In24 are pulled In the correct direction.

Fig. 15A-15B show signal diagrams of the current through the resistors 1144, 1142 at the outputs In14 and In24, respectively, of the large signal detection/fast recovery circuit 1100 of fig. 11. During normal operation, the current is 0 and the instrumentation amplifier/filter 410 circuit is unaffected. When the differential level is too high (i.e., when a large signal is detected, e.g., over 100mV in a few milliseconds), the current in the two resistors 1144, 1142 helps to pull the signal back to the common mode voltage v (cmb).

A/D converter

The a/D converter 416 (see fig. 4) is a fully differential a/D converter, block 8, designed to accept differential signals from the rest of the circuit. In some embodiments, each of the EP system circuit modules is repeated eight times to feed into eight separate channels of the a/D converter 416 as differential pairs. For example, TI ADS 127824 bit, 8 channel delta-sigma converters may be used. Other similar specifications of a/D converters may be selected by one of ordinary skill in the art.

In some embodiments, the a/D converter 416 is highly linear, which is a characteristic of a delta-sigma converter. As described below, high linearity allows accurate digital signal processing to be performed in software. This configuration minimizes hardware filtering, thereby facilitating RF attenuation and anti-aliasing, and allows greater flexibility in filtering and signal processing to be implemented in software. An advantage of selecting a fully differential a/D converter is that common mode noise signals (e.g., digital clock signals) from any digital circuitry can be rejected.

Wilson central terminal-right leg drive (WCT-RLD) circuit

Although the input common mode signal may be at any frequency, the dominant signal is typically at the power line frequency: for example 60Hz in the united states. In conventional EP environments, ECG (and similar) equipment mitigates a significant amount of 60Hz noise, which may be 100 times greater than the signal of interest. Additionally, due to distortion in the power line signal, there is typically a strong third harmonic at 180Hz, which is typically the noisiest harmonic. Higher harmonics and other common mode signals are typically smaller and/or higher than the frequency band of interest of the ECG and IC signals.

In some embodiments, wilson central termination-right leg drive (WCT-RLD) circuitry is used to specifically remove 60Hz and 180Hz noise by common mode rejection, i.e., by boosting the first and third harmonic frequencies of the power line signals and selectively feeding these signals back to the patient to cancel the signals. FIG. 23 illustrates a schematic diagram of an improved WCT-RLD circuit, in accordance with some embodiments.

For example, the WCT circuitry 2332 of fig. 23 provides a virtual ground by summing and averaging two or three limb electrodes (e.g., right arm 2304 and left arm 2306, or right arm 2304, left arm 2306 and left leg 2308) connected to a central terminal 2336 by two or three large resistors 2334 (e.g., 20kOhms on each electrode). One of ordinary skill in the art will appreciate that the average of the Right Arm (RA)2304, Left Arm (LA)2306, and left leg 2308 provides a more accurate estimate of the common mode signal on the patient 2302 compared to the average of the Right Arm (RA)2304 and Left Arm (LA) 2306. As understood by those of ordinary skill in the art, the RA and LA signals are alternative buffered (see buffer 2312) versions of the RL positive (RLP)2338 and RL negative (RLN)2340 signals. WCT is conventionally designed to reduce the overall 60Hz common mode noise signal by making the net potential difference of these limb leads close to zero.

Adding active current to WCT circuit 2332 via the right leg's "right leg drive" (RLD) circuit 2330 allows patient 2302 to be driven to the same voltage as the common amplifier, reducing the common mode voltage at the inputs of the ECG electrodes (LA, RA, LL, and V1-V6). This can be achieved by generating an inverse of the common mode signal and applying it as an output to the right leg. Specifically, the right leg drive is represented by limb electrode RL. Patient 2302 receives RLD output 2310, the summed and inverted versions of the other IC catheter signals or ECG electrode signals via RL electrodes to eliminate interference present in the patient's body. This, in combination with the common-mode rejection properties of the signal amplification stage 532, may reduce the common-mode low-frequency interference to an acceptable level (e.g. specified by the standard IEC 60601-2-25).

However, since the 60Hz and 180Hz noise are not equal in all parts of the body, all noise cannot be removed by common mode rejection alone. The WCT-RLD circuit 2300 of fig. 23 provides a reference signal that is approximately equal to the line frequency of the incoming system, which further reduces the overall common mode signal. Thus, the disclosed combination of the WCT-RLD circuit 2300 and conventional common mode rejection provides an advantageous improvement in the reduction of common mode signals.

In an exemplary embodiment using a WCT, the WCT input within the EP system may provide an optional unipolar input to replace the bipolar positive (+) or negative (-) conduit input to the block 3 snubber circuit (see fig. 4, 406a and 406 b). Specifically, WCT-RLD circuit 2300 averages the electrode signals of right arm 2304, left arm 2306, and left leg 2308. The result is buffered by the operational amplifier 2314 and the output WCTBuf 2316 is sent as a unipolar feedback signal to whatever location in the EP system it is needed, particularly for use in embodiments when the patient is connected. The WCT-RLD disclosed herein enhances the conventional unipolar WCT solution with a novel method for generating RLD signals.

In some embodiments, a novel approach in the WCT-RLD circuit 2300 is to provide additional filter circuitry, referred to as a "double T" feedback network 2440 (see fig. 23 and 24), which can produce a stronger RLD at either the power line frequency of 60Hz or the third harmonic frequency of 180 Hz. This is particularly useful during ablation. The dual T feedback network 2440 resonates at both 60Hz and 180Hz, but advantageously prevents phase oscillations by reducing feedback at other frequencies.

Fig. 24 illustrates a schematic diagram of a dual T feedback network 2440 interfacing with the RLD circuit 2330 of the WCT-RLD circuit 2300, according to some embodiments. The dual T feedback network 2440 of fig. 24 acts as an improved notch filter. Resistors 2406, 2407, 2408, 2409, 2410, 2411 and capacitors 2401, 2402, 2403, 2404 form a single double-T network that generates a notch at 60 Hz. In the next stage, resistors 2412, 2413, 2414, 2417, 2418, 2419 and capacitors 2415, 2416, 2420, 2421 similarly generate a notch at 180 Hz. However, when the network is in the operational amplifier feedback path, an inverse function is obtained.

For example, as shown in the plot 2500 of fig. 25, the RLD output of the dual T feedback network 2440 at the operational amplifier 2425 produces two peaks, one at 60Hz 2510 and one at 180Hz 2520. At higher frequencies (such as 10kHz or higher), the phase change approaches zero. This prevents phase changes in the RLD circuit 2330 at these higher frequencies that could cause oscillations. The minimal phase change at these higher frequencies may prevent oscillations near the ablation frequency, which would be more difficult to filter out.

Although dual T circuitry is used in electronic designs, it has not previously been used in the WCT-RLD circuits disclosed herein. When generating the RLD signal, the dual T feedback network 2440 removes the power line signal that is typically passed by known circuits so that the power line signal does not affect the phase response at higher frequencies. The dual T feedback network 2440 thus has advantageous use for generating RLD signals from electrode leads.

In the embodiment of fig. 23, the RLD circuit 2330 follows the power line by feeding the RLD output 2310 back to the patient 2302 as a separate signal. In the circuit, the right leg positive (+) (RLP)2338 and right leg negative (-) (RLN)2340 differential input signals (which may alternatively be RA and LA signals) are buffered 2312. The dual T feedback network 2440 then boosts/amplifies the buffered right leg signal at 60Hz and 180Hz, which is inverted and buffered again by the RLD circuit 2330. The RLD circuit 2330 includes an operational amplifier 2328, resistors 2320, 2324, 2326, and capacitors 2318, 2322. After passing through the RLD circuit 2330, the signal is output as RLD output 2310(RLDrv) at the surface lead of the patient's right leg. The effect is that the entire circuit tracks the power line and the common mode of the circuit rejects power line noise. Additionally, the right leg driven circuitry prevents any signal greater than about one (1) microampere from being returned to the patient.

In some embodiments, using the first derivative of the two unipolar signals allows the physician to know whether the signal of interest is from the distal or proximal electrode. The bipolar signal may be displayed in a color coded format to identify which components of the bipolar signal are from the cathode and which components are from the anode. The physician may then manually move to the proximal electrode if the primary signal of interest is generated therefrom. The system may also be automated in conjunction with a robotic system such that the movement is part of a closed feedback loop.

Case example

The following case illustrates how the disclosed hardware circuitry conditions the signal found in the EP environment, allowing improved cardiac monitoring in equipment and environmental noise, as well as during the introduction of large, potentially interfering signals into the monitoring environment.

Signal case # 1-common mode 60Hz and in-band 500Hz differential signals

Signal case 1# presents a typical common mode 60Hz noise signal, as well as the in-band (less than 1000Hz) differential signal found from conventional IC leads. In this example, a series of signal diagrams representing signals at exemplary nodes of the disclosed circuit are shown. The circuit amplifies the differential signal and rejects the common mode signal.

Fig. 17A to 17B illustrate input signals of 2Vpp 60Hz sinusoidal (power line) signals applied to input nodes In12 (see fig. 6A) and In22 (negative lower branch of the circuit, not shown), respectively. A 0.2Vpp, 500Hz sine wave signal (see curve V (In12) In fig. 17A) was superimposed on In12, and a-0.2V, 500Hz sine wave signal (see curve V (In22) In fig. 17B) was superimposed on In 22. This will produce a common mode signal of 2Vpp, 60Hz and a differential signal of 0.4V, 500 Hz. The frequencies of these signals may be too low to be affected by the RF filter 702 of block 2, so the same signals appear at the output of block 3 (buffers 406a, 406b) and after block 4(DC blocks 408a, 408 b).

Fig. 17C to 17D illustrate masked input signals (Shield1, Shield2) which are also the same as the corresponding input signals shown in fig. 17A to 17B. These signals are fed back from the block 10 (low frequency feedback circuit 1600) to the RF filter 702 to remove the load from the RF filter 702 (see Shield1, 728. Shield2, negative lower branch of circuit not shown in fig. 7). The voltage variations on the capacitors 714, 716, 706 of the upper branch of the RF filter 702 in fig. 7 and the corresponding capacitors (not shown) on the symmetrical lower branch of the RF filter are close to 0, effectively removing them from the circuit at low frequencies.

18A-18B illustrate the outputs of Out1 and Out2, block 5 (instrumentation amplifier 1001 of FIG. 10) with a differential gain of 20. The common mode signal has a gain of 1 and the differential signal has a gain of 20. At this time, the signal becomes a 2Vpp, 60Hz sine wave at each output with a 4Vpp, 500Hz signal superimposed at Out1 (see FIG. 18A) and a-4 Vpp, 500Hz signal superimposed at Out2 (see FIG. 18B), creating an 8Vpp differential signal.

Fig. 18C-18D illustrate the outputs B2OutP and B2OutN of fig. 10, respectively. At B2OutP and B2OutN, the signal has passed through the fully differential operational amplifier of fig. 10 (blocks 6 and 7, 1017, 1021), the common mode signal has been cancelled, and the output is referenced to the common mode output voltage VOCM (2.5V bias level). The 0.5 gain at amplifier 1034 of block 7 results in a final set of 500Hz signals at 2Vpp at B2OutP (see fig. 18C) and 500Hz signals at-2 Vpp at B2OutN (see fig. 18D), which is equivalent to a 4Vpp differential 500Hz signal. From input to output, the common mode gain is 0 and the differential gain is 10. The common mode signal can thus be cancelled by means of the combined response of the instrumentation amplifier (block 5) and the fully differential operational amplifier (blocks 6 and 7).

Signal case # 2-500 kHz ablation Signal

Signal case #2 presents a typical 500kHz ablation signal applied to the EP system input during an ablation procedure in which cardiac monitoring continues. The undesired ablation signal is filtered and attenuated before reaching the a/D converter (see fig. 4, block 8, 416) of the disclosed circuit.

As shown In fig. 19A-19B, the ablation signal inputs were a 0.2Vpp, 500kHz sine wave applied to In12 (fig. 19A) and a-0.2 Vpp, 500kHz sine wave applied to In22 (fig. 19B). This produced a differential signal of 0.4V, 500 kHz. The signal is in the frequency range to be attenuated by the RF filter 702 (fig. 4, 404a, and 404b) of block 2.

Fig. 19C-19D illustrate plots of the output In13 of the RF filter 702 (block 2) (and the symmetrical lower branch RF filter output In23) when the circuit receives an ablation signal. Curve V of fig. 19C (In13) and V of fig. 19D (In23) are shown In the same scale as the input. It can be seen that the signal is attenuated to a few millivolts.

The plots of V (Shield1) and V (Shield2) shown in fig. 20A and 20B, respectively, illustrate that the same signal on the Shield input (see Shield1 of fig. 7, for example) is also significantly attenuated, effectively grounding the lower plates of the capacitors 714, 716, 706 of the upper branch of the RF filter 702 of fig. 7 and the corresponding capacitors (not shown) on the symmetrical lower branch of the RF filter, so that the RF filter can attenuate a 500kHz ablation signal.

Fig. 21A and 21B illustrate graphs of signals V (Out1) and V (Out2), respectively, at the output of block 5 (instrumentation amplifier 1001 of fig. 10) with a gain of 20. The remaining 500kHz signal passes through the 20X gain stage, but the filtering (from capacitors 1010 and 1012) on this stage limits the 500kHz gain to about 1X.

As shown in fig. 21C-21D, successive fully differential operational amplifiers 1017, 1021 in blocks 6 and 7 of fig. 10 (and their negative, lower branch circuit equivalents) continue to filter the 500kHz signal until it is less than 0.5mV at B2OutP (fig. 21C) and B2OutN (fig. 21D). The remaining signal is removed by a filter (see fig. 4, 416) on the a/D converter of block 8, which provides 100dB of attenuation above 1000 Hz. The ablation signal is cancelled by the combined response of the RF filter (block 2), the instrumentation amplifier (block 5) and the fully differential operational amplifier (blocks 6 and 7).

Hardware/software interface

Fig. 5A illustrates a relationship between hardware and software of the disclosed EP recording system, in accordance with some embodiments. A Main System Unit (MSU)504 contains the hardware circuitry of the EP recording system. In fig. 5A, ECG board 506 with WCT 507 corresponds to ECG board 302 and WCT 314 shown in fig. 3. (for cross reference, the digital signal outputs of the ECG pads 302, 506 are V1-V6310 and I-II 312.) similarly, IC pad 508 corresponds to IC pad 316 in FIG. 3. (for cross reference, the digital signal outputs of IC boards 316, 508 are ICUniWCT1-ICUniWCT 2326, ICUniINDIF1-ICUniINDIF 2328, and ICDiff1. ICDiffN330.) for software 514 that communicates the digital signal outputs from ECG board 506 and IC board 508 to a Main Processing Unit (MPU), a communication module 510 and an optical fiber link 512 are provided.

According to some embodiments, the communication module 510 of the MSU 504 transmits separate digital signals from the a/D converters 416, 534 of the ECG board 506 and the IC board 508 to the MPU 514 over the fiber optic link 512 for digital signal processing. The communication module 510 samples the output channels from the a/D converters 416, 534, converts them to serial format, and transmits the data over the fiber optic link 512. The signal is converted back to parallel format at the receive end of the fiber link 512 in the MPU 514.

In this specification, the ECG boards 302, 506 and the IC boards 316, 508 are thus named for convenience. As one of ordinary skill in the art will appreciate, the circuitry of the ECG and IC boards 302, 506, 316, 508 may accept other physiological signals from various types of electrodes other than ECG and IC electrodes.

EP markRecording system software descriptions

System, apparatus, device, method, and/or computer program product embodiments and/or combinations and subcombinations thereof are provided for near real-time processing and display of multiple signals. For example, embodiments may relate to processing and displaying multiple biomedical signals (e.g., EP signals) in near real-time. Before describing further details of these embodiments, a brief overview of digital signal processing is provided.

At a high level, digital signal processing is the use of digital processing to identify particular features in a signal or to produce a signal of higher quality than the original signal (e.g., by removing noise from the signal). Digital signal processing may be performed on digitized Electrocardiogram (ECG) or Intracardiac (IC) signals representing electrical activity of the heart over a period of time.

In order to perform digital signal processing on an analog signal, the analog signal needs to be converted into a digital form. Analog-to-digital (AD) converters, such as a/D converter 416, may convert the analog signals to digital form, as is well known to those of ordinary skill in the art.

Digital signal processing may involve applying a digital signal processing function to one or more signal samples in a sequence of signal samples for a signal. The digital signal processing function may be a sequence of mathematical operations and computational algorithms. For example, the digital signal processing functions may measure, filter, compress, or optimize the signal samples.

Digital signal processing may use different digital signal processing functions depending on the type of analysis and the type of signal to be processed. For example, digital signal processing may use different digital signal processing functions to identify particular words in a speech signal or to remove motion blur from a video signal.

Digital signal processing systems have many applications such as audio signal processing, audio compression, digital image processing, video compression, speech processing, speech recognition, digital communications, digital synthesis, radar, sonar, financial signal processing, and seismology. Conventional digital signal processing systems are generally not useful in certain applications such as biomedical signal processing. This is because conventional digital signal processing systems (including current EP solutions) typically cannot display multiple signals simultaneously in near real-time. Moreover, conventional solutions do not enable a user to dynamically apply new digital signal processing functions to the underlying signal. Also, conventional solutions typically do not synchronize the processing and display of multiple signals in near real-time. This is often problematic in a clinical setting, as the ability of a physician to make an effective clinical diagnosis may depend on comparing multiple signals at the same point in time. Finally, conventional EP systems using analog filters often fail to take full advantage of digital signal processing. This is because the options are very limited when the functions are implemented in hardware. For example, the functionality cannot be removed and thus the full potential of digital signal processing cannot be obtained.

The Digital Signal Processing (DSP) system disclosed herein further addresses the problems of these conventional systems. In addition to using multiple DSP filters simultaneously to process, time align, and display multiple signals in near real-time, the system also clarifies the operational endpoints for biomedical procedures such as ablation, making the operator more work efficient. For example, the present disclosure provides a high fidelity surface ECG signal to automate and create signal averaged, late potential electrocardiograms. Ablation procedures use internal cardiac maps so that the operator can visualize the cardiac tissue for ablation. When an internal heart map is created, the sufficiency of the map is judged by the percentage map of late potential ECG averaged over the surface signal. In other words, if a complete map is created, all intracardiac signals with late potentials, when summed, should reproduce the timing and amplitude of the signal averaged late potential map from a high fidelity ECG. The score is displayed to represent the sufficiency of the graph. For example, a score of 50% means that the mapping catheter has not yet reached the site where some late signal is present because they must be present to interpret the high fidelity signal averaged late potential map data. Following the potential ablation, a determination is made as to whether the abnormal late potentials have indeed been alleviated via a real-time high fidelity signal averaged late potential ECG. If not, further ablation of the previously marked late potentials may be performed using a late potential filter and a dynamic window for guidance. The disclosed system provides data to guide the operator to the exact late potential region in the map to reduce the need for further ablation.

Fig. 26 is a block diagram of a system 2600 for processing and displaying multiple signals in near real time according to some embodiments. The system 2600 may represent the MPU (software) 514 in fig. 5A and implement the digital processing stage 528 of fig. 5B. The system 2600 includes a signal path module 2602, a configuration path module 2620, and a monitoring module 2622. The signal path module 2602, the configuration path module 2620, and the monitoring module 2622 may be software modules that are executable by a processor(s), such as the processor in fig. 85. Alternatively, multiple processors may be used.

The signal path module 2602 includes an input module 2604, a timer 2605, a packetizer 2606, a queuing module 2608, a packet distributor 2610, a global signal table 2612, and an output module 2616. The input module 2604, the timer 2605, the packetizer 2606, the queuing module 2608, the packet distributor 2610, the global signal table 2612, and the output module 2616 may be software modules capable of being executed by a processor(s), such as the processor 5004. The signal path module 2602 at least solves the technical problem of how to synchronize the near real-time processing and display of multiple signals. As described below, the signal path module 2602 solves this technical problem using a novel multi-stage process involving packet, queuing, and processing delay equalization.

In a first stage, input module 2604 may receive signal samples for one or more base signals. The base signal may be a signal before any digital signal processing is applied. For example, the underlying signal may be a biomedical signal, such as an ECG or IC signal. As one of ordinary skill in the art will appreciate, the underlying signal may be a variety of other types of signals. The input module 2604 may receive signal samples for a plurality of base signals. For example, input module 2604 may receive signal samples of an IC signal and signal samples of an ECG signal.

The input module 2604 may receive signal samples of the base signal from a hardware device associated with the MSU (hardware) 504 in fig. 5. For example, the input module 2604 may receive signal samples from a hardware device, such as the EGG board 302 or the IC board 316 in fig. 3. The input module 2604 may also receive signal samples from data stored in a computer file. For example, a computer file may contain previously recorded signal samples received from a hardware device.

Input module 2604 may receive signal samples from a hardware device via a/D converter stage 534. For example, input module 2604 may receive signal samples of a base signal from EGG board 302.

Input module 2604 may receive signal samples of the underlying signal from electrodes attached to the hardware device. For example, input module 2604 may receive signal samples for each of eight (8) electrodes attached to ECG board 302. One of ordinary skill in the art will appreciate that the input module 2604 may receive more or fewer signal samples depending on the number of hardware devices connected to the input module 2604 and the number of electrodes connected to each hardware device.

The input module 2604 may store one or more signal samples for each base signal in a computer storage device for later analysis by the review module 2624. For example, the input module 2604 may store one or more signal samples in the main memory 8508 or the hard disk drive 8512 in fig. 85. This enables a user (e.g., a physician) to review one or more signal samples for each underlying signal after the signal samples are acquired.

Input module 2604 may distribute one or more signal samples for each base signal to packetizer 2606. The packetizer 2606 may perform pre-processing on the received signal samples. The packetizer 2606 may perform pre-processing on the received signal samples to ensure that the resulting signal is compatible with subsequent stages in the signal path module 2602. One of ordinary skill in the art will appreciate that the type of pre-processing performed by packetizer 2606 may depend on the type of underlying signal. For example, the grouper 2606 may convert binary values of received signal samples into their corresponding physical values, e.g., for displaying the underlying signal.

After pre-processing the received signal samples, the packetizer 2606 may store one or more signal samples of the base signal into packets. The packet may be a continuous sequence of N signal samples belonging to the same underlying signal. The packetizer 2606 stores the signal samples into packets may cause the signal path module 2602 to synchronize the processing and display of multiple signals in near real-time (particularly on non-real-time operating systems). In other words, a packet is a unit of processing in the signal path module 2602.

The packetizer 2606 may store one or more signal samples in the packet based on the timer 2605. The timer 2605 may be a high resolution timer. For example, the timer 2605 may be Microsoft Windows with a resolution of 1 millisecondA high resolution timer. The timer 2605 may be set to an amount of time associated with receiving a fixed number of signal samples (e.g., N signal samples) from a hardware device or from a computer file. The fixed number of signal samples may correspond to the number of signal samples that can be stored in the packet.

The packetizer 2606 may use a timer 2605 to ensure that each packet contains the same number of signal samples. In particular, the packetizer 2606 may set the timer 2605 to an amount of time associated with receiving a given number of signal samples of the base signal. In other words, when the timer 2605 is triggered, the packetizer 2606 may expect to receive a certain number of signal samples.

The packetizer 2606 may start a timer 2605. The packetizer 2606 may then store the signal samples received from the input module 2604 into packets until the timer 2605 is triggered. The packetizer may then distribute the packets to the queuing module 2608. The packetizer 2606 may then restart the timer 2605. The packetizer 2606 may then store the new set of signal samples received from the input module 2604 into a new packet until the timer 2605 is triggered again.

The packetizer 2606 may assign a label to each packet. The packetizer 2606 may assign the same tag to each packet associated with a different base signal for the same period of time. This assignment may enable the signal path module 2602 to synchronize the processing and display of packets of different base signals for the same period. The assigned tags may be used by the display module 2618 to synchronize the output of the different signals. In other words, the display module 2618 may operate on the same tag at any given time.

The assigned tag may correspond to a time period in which the signal samples in the corresponding packet are received. In particular, the label may correspond to the sample number of the first signal sample in the corresponding packet. For example, the packetizer 2606 may store sixteen (16) signal samples in each packet. In this case, the packetizer 2606 may store the first set of signal samples in a packet labeled 0. The grouper 2606 may store the second set of signal samples in a group labeled 15. The grouper 2606 may store subsequent sets of signal samples in groups labeled 31, 47, 64, etc. One of ordinary skill in the art will appreciate that other label assignment conventions may be employed.

After grouping, the grouper 2606 may store each generated packet associated with a given base signal in the queuing module 2608. The queuing module 2608 is shown in fig. 27.

Fig. 27 is a block diagram of a queuing module 2608 for storing each packet generated in association with a different base signal, according to some embodiments. The queuing module 2608 at least solves the technical problem of how to dynamically apply multiple different digital signal processing functions to the same underlying signal. The queuing module 2608 solves this technical problem by storing the generated packets associated with each base signal in separate queues that can be dynamically processed by different signal modules 2614. Fig. 27 is discussed with reference to fig. 26.

The queuing module 2608 includes one or more queues 2702. For example, in FIG. 27, queuing module 2608 includes queue 2702-1, queue 2702-2, and queue 2702-N. Each queue 2702 may be associated with a given underlying signal. Queue 2702 may be a queue data structure that stores entries in the order in which they were inserted. For example, the first entry inserted into queue 2702 is the first entry removed from queue 2702. In other words, queue 2702 is a first-in-first-out (FIFO) data structure. As will be appreciated by one of ordinary skill in the art, the queue 2702 may be implemented using an array, a linked list, or various other data structures.

The packetizer 2606 can store each packet generated in association with a given base signal in a corresponding queue 2702. For example, packetizer 2606 may store generated packets associated with IC signals into queue 2702-1 and generate packets associated with ECG signals into queue 2702-2.

The packetizer 2606 can store each packet in the queue 2702 in the generated order. This ensures that the signal samples in the generated packet are processed in the order they were received from the hardware device or computer file.

Returning to fig. 26, the packet distributor 2610 may distribute the generated packets from the queues 2702 in fig. 27 to one or more signal modules 2614 in the global signal table 2612 for digital signal processing. The packet distributor 2610 at least solves the technical problem of how to dynamically apply multiple different digital signal processing functions to the same underlying signal. The packet distributor 2610 solves this technical problem by distributing the generated packets associated with each base signal to the appropriate signal module or modules 2614 for digital signal processing.

The packet distributor 2610 may continuously scan one or more queues 2702 in the queuing module 2608. Each time the packet distributor 2610 detects a new packet available in the queue 2702 in the queuing module 2608, the packet distributor 2610 may remove the new packet from the queue. The packet distributor 2610 may then distribute the new packets to one or more signal modules 2614 in the global signal table 2612 for digital signal processing. The packet distributor 2610 may distribute the same packet to multiple signal modules 2614 so that the underlying signals may be processed simultaneously using different digital processing functions. Furthermore, because the packet distributor 2610 may distribute packets from different queues 2702 to different signal modules 2614, different underlying signals may be processed simultaneously using different digital signal processing functions.

The packet distributor 2610 may distribute new packets from the queue 2702 to one or more signal modules 2614. The packet distributor 2610 may use the global signal table 2612 to distribute new packets to one or more signal modules 2614. The global signal table 2612 may be an array of fixed size. Each element of the array may be associated with a given base signal and thus a given queue 2702. For example, if there are 100 base signals, the global signal table 2612 may be a fixed-size array of 100 elements. Further, for each element of the array, there may be one or more signal modules 2614 designed to process the corresponding base signal. In some embodiments, each element of the array may itself be a fixed size array. Each element of the sub-array may be associated with a given signal module 2614. For example, if there are 10 signal modules 2614, the sub-array may contain 10 elements. Thus, by way of example and not limitation, global signal table 2612 may be a 100 x 10 array.

The packet distributor 2610 may distribute the new packet to the signal module 2614 by examining corresponding elements in the sub-array associated with the underlying signal of the new packet. In particular, the packet distributor 2610 may determine whether a corresponding element in the sub-array indicates that the signal module 2614 is assigned to the base signal associated with the packet.

In some embodiments, the global signal table 2612 may indicate whether a given signal module 2614 is assigned to a given base signal by storing a "0" or a "1" at a corresponding element in the sub-array associated with the given signal module 2614. For example, the global signal table 2612 may indicate that a given signal module 2614 is not assigned to a given base signal by storing a "0" at a corresponding element in the sub-array. In some other embodiments, the global signal table 2612 may indicate whether a given signal module 2614 is assigned to a given base signal by storing a reference to the given signal module 2614 at a corresponding element in the sub-array. As one of ordinary skill in the art will appreciate, the reference may be a memory pointer, flag, handle, or other type of identifier.

The packet distributor 2610 may also use a lookup table to distribute new packets to one or more signal modules 2614. A lookup table may map a given queue 2702 to one or more signal modules 2614. The packet distributor 2610 may use a lookup table to dynamically determine which one or more signal modules 2614 are associated with a given queue 2702. The packet distributor 2610 may then distribute the packets to the determined one or more signal modules 2614 for digital signal processing.

The configuration path module 2620 may configure the signal path module 2602 before the packet distributor 2610 can begin distributing packets to one or more signal modules 2614 for digital signal processing. Configuration path module 2620 may perform the configuration during initialization of system 2600 or when a user applies a new configuration to signal path module 2602. The configuration path module 2620 is shown in FIG. 28.

Fig. 28 is a block diagram of a configuration path module 2620 to configure the signal path module 2602 to synchronize the processing and display of multiple signals in near real-time, according to some embodiments. The configuration path module 2620 at least addresses the technical problem of how to synchronize the processing and display of multiple signals associated with one or more base signals in near real-time. The configuration path module 2620 solves this technical problem by equalizing the processing delay of each signal module 2614 such that each signal module 2614 completes the processing of the same corresponding packet at approximately the same time. Fig. 28 is discussed with reference to fig. 26.

The configuration path module 2620 includes a signal configuration module 2802, a signal factory module 2804, a Digital Signal Processor (DSP) equalizer 2806, and a DSP factory module 2808. The configuration path module 2620 is a software module that is executable by a processor(s), such as the processor 5004. The configuration path module 2620 controls the execution of the signal factory module 2804, the DSP equalizer 2806, and the DSP factory module 2808. Factory signal module 2804, DSP equalizer 2806, and factory DSP module 2808 may be software modules capable of being executed by a processor(s), such as processor 5004.

During initialization of system 2600, or in response to a user applying a new configuration to system 2600, configuration path module 2620 may generate and configure one or more signal modules 2614 in global signal table 2612. In some embodiments, execution of the signal path module 2602 and the monitoring module 2622 may be paused during execution of the configuration path module 2620.

The configuration path module 2620 includes a signal configuration module 2802. The signal configuration module 2802 can receive one or more signal processing specifications. Signal processing specifications may be used to generate and configure the signal module 2614. The signal processing specification may specify a base signal to be processed, the length of the input and output packet queues for the signal module 2614, and the digital signal processing functions to be used to process the base signal. The signal configuration module 2802 may receive one or more signal processing specifications from a computer file. The file may contain one or more signal processing specifications previously specified by the user. The signal configuration module 2802 may also receive signal processing specifications via a Graphical User Interface (GUI) where a user manually enters the signal processing specifications using a series of computer mice, touch, keyboard, and/or voice recognition data entry techniques, as will be understood by those of ordinary skill in the art.

In response to receiving the one or more signal processing specifications, signal configuration module 2802 may forward the one or more signal processing specifications to signal factory module 2804. The signal factory module 2804 can generate a signal module 2614 based on the signal processing specification. For example, the signal factory module 2804 can generate a signal module 2614 as shown in fig. 29.

Fig. 29 is a block diagram of a signal module 2614 generated by the signal factory module 2804, according to some embodiments. The signal module 2614 may generate a processed signal from the base signal. Signal module 2614 includes an input packet queue 2902, a Digital Signal Processor (DSP)2904, and an output packet queue 2906. Fig. 29 may be discussed with reference to fig. 26 and 28.

The signal module 2614 includes an input packet queue 2902, a DSP 2904, and an output packet queue 2906. The signal factory module 2804 may generate an input packet queue 2902, a DSP 2904, and an output packet queue 2906 based on signal processing specifications from the signal configuration module 2802. The input packet queue 2902 may store one or more packets from the packet distributor 2610 for processing by the DSP 2904. The input packet queue 2902 may be a queue data structure that stores entries in the order in which they were inserted. For example, the first entry inserted into the input packet queue 2902 is the first entry removed from the input packet queue 2902. In other words, the input packet queue 2902 may be a first-in-first-out (FIFO) data structure. As will be appreciated by one of ordinary skill in the art, the incoming packet queue 2902 may be implemented using a linked list, an array, or various other data structures.

The output packet queue 2906 may store one or more packets that are processed by the DSP 2904. The outgoing packet queue 2906 may be a queue data structure that stores entries in the order in which they were inserted. For example, the first entry inserted into the outgoing packet queue 2906 is the first entry removed from the outgoing packet queue 2906. In other words, the output packet queue 2906 may be a first-in-first-out (FIFO) data structure. As will be appreciated by one of ordinary skill in the art, the output packet queue 2906 may be implemented using a linked list, an array, or various other data structures.

The signal factory module 2804 can generate the DSP2904 based on signal processing specifications from the signal configuration module 2802. Specifically, the factory signal module 2804 can request the factory DSP module 2808 to generate the DSP 2904. The DSP factory module 2808 can generate the DSP2904 based on digital signal processing functions specified in the signal processing specification. The factory DSP module 2808 may also generate the DSP2904 based on one or more signal processing parameters associated with the digital processing function. For example, the DSP factory module 2808 can generate the DSP2904 based on a low pass filter function and a cutoff frequency specified in a signal processing specification.

The DSP 2904 is a software module that can be executed by a processor(s), such as the processor 8504 in fig. 85. DSP 2904 may apply digital processing functions to one or more packets and, thus, to one or more signal samples. As will be appreciated by one of ordinary skill in the art, a digital processing function may be a mathematical algorithm that takes one or more signal samples as input, processes them, and produces one or more potentially modified signal samples as output. The digital processing function may be implemented using one or more mathematical operations, such as a fast fourier transform. As will be appreciated by one of ordinary skill in the art, various types of digital processing functions may be applied by the DSP 2904. For example, the DSP 2904 may apply a low pass filter, a high pass filter, a band reject filter, a notch filter, a comb filter, an all pass filter, or various other filters as will be understood by one of ordinary skill in the art.

The DSP 2904 may also apply digital processing functions that analyze signals for various characteristics. For example, DSP 2904 may apply digital processing functions that determine whether a noise anomaly or signal pattern is present in the signal. The DSP 2904 may also analyze the signal by detecting repeating patterns in the signal. This may involve comparing the signal with previously detected (or recorded or synthesized) signal patterns.

For example, DSP 2904 may determine a late potential in the signal. In particular, DSP 2904 may determine a noise anomaly and then determine a subsequent noise anomaly that occurred contemporaneously with respect to the matched heart beat. Each subsequent noise anomaly at the same relative position may increase the confidence level at which the late potential is located. The display module 2618 may then display an indication of the late potential.

For example, the determination of late potentials by DSP 2904 may be used for a pulmonary vein potential filter. In particular, a combination of late mid-p-wave discrete electrograms with filtering for fast conduction may be used to identify pulmonary vein potentials that are discrete from adjacent atria and other structures. These signals may be used as endpoints of ablation ports to quickly identify delays and rejections. The system can be used for other thoracic veins, late electrocardiograms over the semilunar valve, late potentials for myocardial disease, and coronary sinus and Marshal veins.

Similarly, DSP 2904 may determine an early activation in the signal. In particular, DSP 2904 may determine the earliest sharp intracardiac signal above a selected threshold that occurs within a predetermined segment before the reference point of the matched heart beat. The display module 2618 may then display an indication of the early activation.

DSP2904 may use a correlation function to detect patterns in the signal. For example, DSP2904 may use a mean absolute deviation algorithm to detect patterns. As one of ordinary skill in the art will appreciate, the DSP2904 may use various other types of pattern matching algorithms.

The DSP2904 may detect patterns (also referred to as signal patterns) based on various signal characteristics. For example, DSP2904 may detect patterns based on shape, amplitude, and time characteristics. As one of ordinary skill in the art will appreciate, the DSP2904 may detect patterns based on various other types of signal characteristics.

The DSP2904 may also include one or more signal processing parameters. The signal processing parameters may control how the DSP2904 applies its digital processing functions. For example, DSP2904 may include one or more signal processing parameters that specify a threshold frequency or amplitude for filtering. DSP2904 may also include one or more signal processing parameters that specify signal patterns to be detected or noise thresholds.

The DSP2904 may apply its digital processing functions to packets in the input packet queue 2902. In some embodiments, DSP2904 may scan incoming packet queue 2902 for new packets to be processed. In some other embodiments, DSP2904 may be notified that a new packet is available in incoming packet queue 2902. The DSP2904 may then retrieve the packet from the input packet queue 2902.

DSP 2904 may apply its digital processing functions to the retrieved packets. In other words, DSP 2904 may apply its digital processing functions to one or more signal samples in a packet. DSP 2904 may control how its digital processing functions are applied to one or more signal samples in a packet based on one or more of its signal processing parameters. After processing the packets, DSP 2904 may store the packets in output packet queue 2906 for display by output module 2616.

As described below, each DSP 2904 may have an associated processing delay. The processing delay may represent an amount of time that processing of a packet is completed by digital processing functions of DSP 2904. Processing delays may vary between different DSPs 2904. As described below, this variation in processing delay between different DSPs 2904 may cause the DSPs 2904 to output packets for display at different times.

After the factory signal module 2804 completes generating the input packet queue 2902, DSP 2904, output packet queue 2906, the factory signal module 2804 may connect the output of the input packet queue 2902 to the input of the DSP 2904, and the output of the DSP 2904 to the input of the output packet queue 2906. Once the factory signal module 2804 completes the connection, the DSP 2904 may receive packets from the input packet queue 2902 that represent the raw underlying signal. The DSP 2904 may then use its digital processing functionality to process the packet. The DSP 2904 may output the processed packets to an output packet queue 2906. The signal factory module 2804 can further configure the incoming packet queue 2902 to receive packets from the underlying signal specified in the signal processing specification.

Once the signal module 2614 is created, the signal factory module 2804 may add it to the global signal table 2612. As described above, the global signal table 2612 may be an array of fixed size. Each element of the array may be associated with a given underlying signal. Furthermore, each element of the array may itself be a fixed size array. Each element of the sub-array may be associated with a given signal module 2614.

In some embodiments, the signal factory module 2804 may add the created signal module 2614 to the global signal table 2612 by adding a new array element to each sub-array associated with the base signal. The new array element may correspond to the newly created signal module 2614. For example, if the global signal table 2612 previously contained ten (10) signal modules 2614, then, for example, a newly created signal module 2614 may be added at element number 11 in each sub-array.

Once the created signal module 2614 is added to the global signal table 2612, a user (e.g., a physician) may assign the created signal module 2614 to a given base signal. In some embodiments, the global signal table 2612 may indicate whether the created signal module 2614 is assigned to a given base signal by storing a "0" or a "1" at a corresponding element in the sub-array associated with the created signal module 2614. In some other embodiments, the global signal table 2612 may indicate whether the created signal module 2614 is assigned to a given base signal by storing a reference to the created signal module 2614 at a corresponding element in the sub-array.

The signal factory module 2804 can generate a plurality of signal modules 2614. Each signal module 2614 may have a DSP 2904 that applies different digital signal processing functions. As a result, each signal module 2614 may generate a different processed version of the same base signal. This may enable a user to analyze the same underlying signal in a variety of ways. The user may also wish to analyze the time-aligned output of multiple versions of the same base signal. This may enable a user to compare different versions of the same signal at the same point in time or at different points in time.

As described above, conventional digital signal processing systems are generally unable to synchronize the display of the processed multiple signals in near real-time. This may be because different digital signal processing functions have different processing delays. For example, current EP systems may apply two different digital signal processing functions to the same underlying signal. The medical team may wish to synchronize the display of the two processed signals. For example, a medical team may wish to compare the IC signal and the ECG signal at the same point in time to determine a clinical diagnosis. In other words, the medical team may wish to align the display of the first processed signal with the display of the second processed signal in near real-time. However, if two different digital signal processing functions have different processing delays, this may not be possible. This is because one of the digital signal processing functions can complete the processing of the underlying signal faster than the other digital signal processing functions. As a result, one signal processed may be displayed before another signal processed.

The processing delay associated with digital processing functions may be related to the complexity of the function. For example, a digital processing function that performs low pass filtering on a signal may have less computational effort and use minimal memory. As a result, such digital processing functions may have short processing delays. Instead, another digital processing function may analyze the signal for particular signal characteristics. This type of digital processing function may require more computation and use more memory, and therefore have longer processing delays.

Due to the different processing delays, one processed signal may be displayed before the other processed signal. The synchronization gap may become larger as time passes. For example, the synchronization gap may be larger where multiple signals are processed and displayed in near real-time. This is because the difference in processing delay between the two digital signal processing functions may propagate to each new signal sample.

For example, for a given base signal, the first digital signal processing function may have a processing delay of 10 milliseconds. The second digital signal processing function may have a processing delay of 20 milliseconds for the same underlying signal. The first digital signal processing function may complete the processing of a first signal sample of the base signal at 10 milliseconds, while the second digital signal processing function may complete the processing of the same first signal sample at 20 milliseconds. Thus, the first signal samples processed by the first digital signal processing function may be displayed at 10 milliseconds, and the first signal samples processed by the second digital signal processing function may be displayed at 20 milliseconds. In other words, the first signal samples processed by the first digital signal processing function may be displayed 10 milliseconds before the first signal samples processed by the second digital signal processing function.

The synchronization gap may increase as the second signal samples are processed. For example, the second signal sample may be received at time 10 milliseconds for processing by the first digital signal processing function, and the second signal sample may be received at time 20 milliseconds for processing by the second digital signal processing function. As a result, the second signal samples processed by the first digital signal processing function may be displayed at 20 milliseconds, and the second signal samples processed by the second digital signal processing function may be displayed at 40 milliseconds. In other words, the synchronization gap for the second signal sample may be increased by 10 milliseconds; initially, the synchronization gap is 10 milliseconds, and then the synchronization gap is 20 milliseconds.

In the case where digital signal processing is performed on a non-real-time operating system, the synchronization gap may increase. Unlike non-real-time operating systems, real-time operating systems are time-limited systems with well-defined fixed time constraints. The real-time operating system may ensure that application tasks are accepted and completed within a certain amount of time. In other words, the real-time operating system may provide a consistent level of consistency with respect to the amount of time required to complete a task.

In contrast, a non-real-time operating system cannot provide any assurance that an application task is completed within a certain amount of time. For example, a non-real-time operating system may not guarantee that the execution of a particular digital signal processing function is completed within a certain amount of time. As a result, there may be a high degree of variability with respect to the amount of time it takes to complete a task. This can be problematic when attempting to synchronize the processing and display of the processed multiple signals. This is because the processing delay associated with digital processing functions may vary with each execution. For example, digital signal processing functions can typically be performed within 10 milliseconds. On non-real-time operating systems, however, there may be no guarantee that the digital signal processing functions will complete execution after 10 milliseconds. For example, the digital signal processing function may be performed within 30 milliseconds. This variability in processing delay may further increase the synchronization gap.

In some embodiments, the display synchronization problem is solved in a multi-factor manner using the input packet queue 2902 and the output packet queue 2906 of the signal module 2614, storing signal samples in packets with associated tags, and equalizing processing delays among the one or more DSPs 2904.

The input packet queue 2902 and the output packet queue 2906 may solve the display synchronization problem in three ways. First, they ensure that packets are processed and displayed in sequence and thus that signal samples are processed and displayed in sequence. Second, the output packet queue 2906 may synchronize the display of packets at the same point in time by blocking the processing of more packets until the existing packets are consumed by the output module 2616. In other words, the output packet queue 2906 may provide a feedback mechanism to the DSP 2904 that indicates when the DSP 2904 may stop processing more packets. Finally, the input packet queue 2902 ensures that the DSP 2904 has packets pending. For example, DSP 2904 may stop processing more packets when the incoming packet queue 2902 is empty. In other words, the input packet queue 2902 may provide a feedback mechanism to the DSP 2904 to indicate that no more packets are pending.

The DSP delay equalizer 2806 may also address display synchronization issues by equalizing the processing delay across one or more DSPs 2904. As described above, different digital signal processing functions have different processing delays, which may result in the processed signals being displayed asynchronously. Thus, if the configuration path module 2620 generates multiple signal modules 2614, each including a DSP 2904 with different digital signal processing functionality, each signal module 2614 may complete packet processing with different processing delays. Due to these different processing delays, the processed signals may be displayed asynchronously by the output module 2616. The DSP delay equalizer 2806 may solve this problem by equalizing the processing delay across the generated signal module 2614.

In some embodiments, after the configuration path module 2620 generates one or more signal modules 2614, the signal factory module 2804 may equalize the generated processing delay of each signal module 2614 using the DSP delay equalizer 2806 so that each signal module 2614 simultaneously outputs processed packets to its output packet queue 2906. For example, the DSP delay equalizer 2806 may determine the relative processing delay between the two signal modules 2614. The DSP delay equalizer 2806 may then use the determined relative delay to configure the DSP 2904 in the first signal module 2614 to complete processing of the packet at approximately the same time that the DSP 2904 in the second signal module 2614 is designed to complete processing of the packet.

In some embodiments, the DSP delay equalizer 2806 may perform equalization by scanning each generated signal module 2614. During the scan, the DSP delay equalizer 2806 may request a processing delay associated with the DSP 2904 in each signal module 2614. The DSP delay equalizer 2806 may request a processing delay using an Application Programming Interface (API) of each signal module 2614. In response, each signal module 2614 may return its associated processing delay.

The signal module 2614 may store the processing delay associated with its DSP 2904. The processing delay may be a predefined value specified in the signal processing specification used to generate DSP 2904. In some other embodiments, the DSP factory module 2808 may calculate the processing delay of the DSP 2904 based on various factors including the digital processing functions used by the DSP 2904, selected signal processing parameters, and hardware characteristics such as the speed of the processor (such as the processor 5004), the size of the memory, and the I/O latency.

After determining the processing delay associated with the DSP 2904 in each signal module 2614, the DSP delay equalizer 2806 may determine the maximum processing delay among the signal modules 2614. For example, DSP delay equalizer 2806 may determine that signal block 2614-1 has a processing delay of 10 milliseconds, signal block 2614-2 has a processing delay of 20 milliseconds, and signal block 2614-N has a processing delay of 50 milliseconds. Based on this, the DSP delay equalizer 2806 may determine that the maximum processing delay between signal blocks 2614 is 50 milliseconds.

After determining the maximum processing delay, the DSP delay equalizer 2806 may configure the DSP 2904 of each signal module 2614 to have the maximum processing delay. For example, the DSP delay equalizer 2806 may use an API to set the processing delay of the DSP 2904 for each signal module 2614. In response, each DSP 2904 may be designed to process packets using its digital processing functionality and output the processed packets to its associated output packet queue 2906 at the end of the maximum processing delay. For example, in some embodiments, if the DSP 2904 completes processing a packet before the maximum processing delay ends, it may block its output to its output packet queue 2906. In some other embodiments, DSP 2904 may insert idle computation periods during processing of packets. As will be appreciated by one of ordinary skill in the art, various other methods may be used to cause the DSP 2904 to output processed packets to its output packet queue 2906 at the end of the maximum processing delay.

Packetization and assignment of tags to packets may solve the display synchronization problem. As described above, each packet generated may include a fixed number of signal samples. Each packet may also contain a tag that indicates the relative position of the packet between the sequence of packets. To synchronize the display of multiple signals, the display module 2618 may display packets having the same label. In other words, the display module 2618 may use a tab to synchronize its display.

As shown in FIG. 26, the output module 2616 may include one or more display modules 2618-1 through 2618-N and a review module 2624. The review module 2624 may be a software module capable of being executed by a processor(s), such as the processor 5004. The review module 2624 may display the one or more signals processed by the one or more signal modules 2614 at a previous point in time. The display modules 2618 may each be a software module capable of being executed by a processor(s), such as the processor 5004. The display module 2618 may display one or more real-time signals processed by one or more signal modules 2614. Each display module 2618 may operate independently of the other display modules 2618. In other words, each display module 2618 may simultaneously display one or more signals on one or more display devices (such as input/output device 8503 in fig. 85). In some embodiments, each display module 2618 may display its associated signal or signals in a particular GUI window on a given display device.

Each display module 2618 may display one or more signals. Each display module 2618 may receive packets from an associated output packet queue 2906 in a signal module 2614 in the global signal table 2612. The display module 2618 may display the signals based on the grouping.

Fig. 30 is a block diagram of a display module 2618 according to some embodiments. The display module 2618 includes a local signal table 3002, a grouping index 3004, and a display setting 3006. Fig. 30 is discussed with reference to fig. 29.

As discussed, display module 2618 may receive packets from an associated output packet queue 2906 in signal module 2614. To receive packets, display module 2618 may maintain a reference to an associated output packet queue 2906 in signal module 2614. When the display module 2618 is designed to display multiple signals, the display module 2618 may maintain a reference to the output packet queue 2906 associated with each signal being displayed. The display module 2618 may store the reference in its local signal table 3002. The local signal table 3002 may contain a list of one or more references to the output packet queue 2906 associated with each signal being displayed. When the associated signal module 2614 is no longer active, the display module 2618 may remove the reference from its local signal table 3002.

In some embodiments, the display module 2618 may continuously scan its associated output packet queue or queues 2906 for new packets. Where the display module 2618 is associated with a single output packet queue 2906, it may display packets on the display device each time the display module 2618 detects a new packet. However, where the display module 2618 is associated with multiple output packet queues 2906, the display module 2618 may not immediately display new packets detected in a particular output packet queue 2906. This is because the display module 2618 may be designed to synchronize the display of multiple signals.

In some embodiments, given that the display module 2618 is designed to synchronize the display of multiple signals, the display module 2618 may detect a new packet in a particular output packet queue 2906. The display module 2618 may then determine the tag associated with the new grouping. The display module 2618 may use the determined tags to synchronously display new packets from other outgoing packet queues 2906. For example, the display module 2618 may wait to display any packets to the display device until a new packet having the determined same label is detected at other output packets. Once the display module 2618 detects new packets with the same tag at its other associated outgoing packet queue 2906, the display module 2618 may simultaneously display packets from its associated outgoing packet queue 2906. The display module 2618 may display multiple signals in a non-overlapping stackable format. Because the display module 2618 can display packets with the same label, the signals displayed as a result can be time aligned.

As previously described, the type of pre-processing that the packetizer 2606 may perform on any of the plurality of signals may be related to the type of signal. In some embodiments, the selection of the pre-processing of the signal by the packetizer 2606 may be automatic. This allows for the automatic deployment of appropriate filters with minimal filtering, based on adjacent signals and the ratio of far-field to near-field signals, for example to minimize noise and target the signal of interest. As will be appreciated by those of ordinary skill in the art, this type of automation may effectively minimize process time for small and medium-sized batch operators, for example. The display module 2618 may similarly synchronize and display multiple signals when a new packet is detected from an automated process.

The display module 2618 may maintain the current active tab to be displayed in the grouping index 3004. When a new packet is detected in a particular outgoing packet queue 2906, the display module 2618 may determine the label of the new packet. The display module 2618 may then set the grouping index 3004 to the determined tag.

In some embodiments, a high frequency fast conducting signal filter may be applied to multiple electrodes, such as with basket or balloon catheters, to identify conducting tissue (such as distal purkinje and annular fast conducting tissue). Such annular tissue can be rapidly targeted for ablation due to the protrusion of its signal. Based on the dynamic indicia from the grouping of the grouper 2606, the display module 2618 may continue to visualize the signals as a reference point to guide ablation catheter movement and may be used to terminate local energy delivery when the pathogenic signal of interest decays upon ablation. As shown in this example, the pre-processing and continued processing of the system may allow the physician to continue to see the signal even while ablating.

Display module 2618 can include display settings 3006. Display settings 3006 may include one or more parameters that control how display module 2618 displays its associated signal or signals. Display settings 3006 can specify colors to display one or more associated signals. The display settings 3006 may specify a view format (such as a waterfall view, a dynamic view, or a triggered view as described below). The display settings 3006 may specify a sweep speed for one or more signals. Display settings 3006 can contain various other types of display settings as will be understood by one of ordinary skill in the art. As described below, the display settings 3006 can be designed by a user.

The review module 2624 may display one or more signals processed by the one or more signal modules 2614 at a previous point in time. This may enable a user (e.g., a physician) to analyze one or more signals long after they have been generated and displayed. In some embodiments, the review module 2624 may capture a display of the one or more signals in the display module 2618 in response to the command. For example, the user may click a button in the GUI to capture the current display of the display module 2618. The captured display may include a previously displayed visualization of the one or more signals at the time of capture. In some embodiments, the display module 2618 may pause its display of the new grouping in response to its capture of the current display.

In some embodiments, the review module 2624 may capture the display of one or more signals in the display module 2618 by determining a capture configuration of the display module 2618. The capture configuration may include one or more active signal modules 2614 for display module 2618, a capture time, a selected view for display module 2618, a color scheme for one or more display signals, and various other settings as will be understood by one of ordinary skill in the art. After determining the capture configuration, review module 2624 may apply the capture configuration to the previously stored signal samples.

As described above, the input module 2604 may store one or more signal samples for each base signal in a storage device for later analysis by the review module 2624. The review module 2624 may capture a display of one or more signals in the display module 2618 by applying the determined capture configuration to the stored signal samples. In particular, the review module 2624 may select the stored signal samples at the capture time in the capture configuration. The review module 2624 may then process the selected signal samples using the active signal module 2614 in the capture configuration. The review module 2624 may also display the selected signal samples using the selected view, the color scheme, and various other settings in the capture configuration. Thus, the review module 2624 may enable the user to review the one or more processed signals for the display module 2618 at a particular point in time and subject to a particular configuration.

In some embodiments, the review module 2624 may enable the user to change the review interval for the display module 2618. For example, the user may "rewind" to a different point in time in the past (e.g., 5 minutes ago). After the capture time is changed, the review module 2624 may display the one or more processed signals for the display module 2618 at the new review time index.

Fig. 31 is a block diagram of a monitoring module 2622 according to some embodiments. Monitoring module 2622 includes queue monitor 3102 and reporting module 3104. Queue monitor 3102 and reporting module 3104 may be software modules executable by processor(s), such as processor 5004.

The monitoring module 2622 may be executed continuously while the signal path module 2602 is being executed. For example, the monitoring module 2622 may be executed by a processor as a separate thread of execution. The monitoring module 2622 may determine whether there is a problem with the execution of the signal path module 2602.

In some embodiments, queue monitor 3102 may periodically scan the queues in signal path module 2602. For example, queue monitor 3102 may scan queue 2702 in queuing module 2608. Queue monitor 3102 may also scan input packet queues 2902 and output packet queues 2906 in one or more signal modules 2614. Queue monitor 3102 may determine the status of each queue during scanning. For example, queue monitor 3102 may determine the length of each queue during the scan. In some embodiments, if queue monitor 3102 determines that the queue has an error status, queue monitor 3102 may request reporting module 3104 to display the error status on a display device. For example, queue monitor 3102 may determine that the length of the queue is continuously increasing. In response, queue monitor 3102 may request reporting module 3104 to display an error indicating that a particular queue has an incorrect length.

Fig. 32 illustrates an example adjustment of the sweep speed of the display module 2618, according to some embodiments. Fig. 32 includes a real-time viewing area 3202 and a sweep speed 3204. Fig. 32 is discussed with reference to fig. 26.

The real-time viewing area 3202 may contain a near real-time display of the display module 2618. In fig. 32, the real-time viewing area 3202 includes a near real-time display of fourteen (14) different signals (e.g., processed signals or underlying signals).

The sweep speed 3204 may be a GUI widget that allows the user to select a sweep speed for the real-time viewing area 3202. The sweep speed may represent a time scale of one or more signals displayed in the real-time viewing area 3202. The sweep speed may range from 10 millimeters per second to 1000 millimeters per second. In fig. 32, the sweep speed 3204 is shown as being selected to be 50mm per second. As will be appreciated by those of ordinary skill in the art, the selection of the sweep speed may affect the level of detail displayed, and thus may be set based on the size of the display screen.

Fig. 33 illustrates signal management for a display module 2618 according to some embodiments. Fig. 33 includes a signal management window 3302. Fig. 33 is discussed with reference to fig. 26.

The signal management window 3302 may include available signals 3304 and signal settings 3306. The available signals 3304 may contain one or more signals that may be selected for display by the display module 2618. For example, in fig. 33, the available signals 3304 include fourteen (14) signals that may be selected for display by the display module 2618. The available signals 3304 may display various information about each signal. For example, the available signals 3304 may show the name of the signal and whether the signal is processed by a particular signal module 2614.

Signal settings 3306 may display various settings that may be set for each signal. For example, in fig. 33, signal settings 3306 enable a user to change the name of each signal or assign a particular color to each signal. These settings may be stored in display settings 3006 in display module 2618. Signal settings 3306 may also enable a user to change various processing parameters associated with each signal. These processing parameters may be stored in one or more signal processing parameters of the DSP 2904 of the signal module 2614 associated with a given signal.

Fig. 34 illustrates an example adjustment of the zoom and clip (clip) factor for a display module 2618, according to some embodiments. Fig. 34 includes a real-time viewing area 3402 and a display settings window 3404. Fig. 34 is discussed with reference to fig. 26.

The real-time viewing region 3402 may contain a near real-time display of the display module 2618. In fig. 34, the real-time viewing area 3402 includes a near real-time display of fourteen (14) different signals (e.g., processed signals or underlying signals).

The display settings window 3404 may include a zoom factor 3406 and a clipping factor 3408. The zoom factor 3406 may be a GUI widget to select a zoom factor for a particular signal in the real-time viewing area 3402. The selected scaling factor may increase or decrease the size of a particular signal. For example, the scaling factor 3406 may multiply the magnitude of a particular signal from 0.02 to 40 times.

The clipping factor 3408 may be a GUI widget, allowing a user to select a clipping factor for viewing a particular signal in the area 3402 in real time. The selected clipping factor may control the amount by which the signal overshoots the display screen. For example, the user may adjust the clipping factor to reduce the actual area of a particular signal being displayed so that if the particular signal is large, it does not extend beyond the entire display screen, thereby not rendering portions invisible.

FIG. 35 illustrates schema search management for a display module 2618 in accordance with some embodiments. Fig. 35 includes a real-time viewing area 3502 and a pattern search window 3504. Fig. 35 is discussed with reference to fig. 26.

The real-time viewing region 3502 may include a near real-time display of the display module 2618. The pattern search window 3504 may be a GUI window that enables a user to load or specify a signal pattern to be searched. For example, in fig. 35, a user may create or load a search for late potentials or early activations in one or more signals. The user may also specify various parameters for the search, such as a search interval, a heart beat detection confidence percentage, a detection confidence percentage, or other parameters as will be understood by those of ordinary skill in the art. The signal pattern to be searched may be stored in one or more signal processing parameters of DSP 2904 of signal module 2614 associated with a given signal.

Fig. 36 illustrates a highlighted late potential search result in the display of display module 2618 according to some embodiments. Fig. 36 includes a real-time viewing area 3602. Fig. 36 is discussed with reference to fig. 26.

The real-time viewing area 3602 may include a near real-time display of the display module 2618 subject to a late potential search. As shown in fig. 35, the user may create or load a search for late potentials. Once the search is initiated, the real-time viewing region 3602 may display late potentials found in one or more signals. The real-time viewing area 3602 may display the late potentials found and the detection confidence percentage. For example, in fig. 36, the found late potential 3604 is displayed with a detection confidence of 83%. The real-time viewing area 3602 may also display a total count of late potentials found.

FIG. 37A illustrates a display module 3618 configured as a waterfall view (waterfall view) for use in accordance with some embodiments. Fig. 37A includes a real-time viewing area 3702. Fig. 37A is discussed with reference to fig. 26.

The real-time viewing area 3702 can include a near real-time display of the display module 2618. The real-time viewing area 3702 may display a near real-time display of the display module 2618 using a waterfall view. In the waterfall view, the signals may be displayed side-by-side and vertically stacked upon each other when the patterns are matched. In particular, the user may select a pattern (e.g., a particular heart beat pattern) to match the first signal. When a pattern is detected in the first signal, the display module 2618 may display a portion of the first signal that matches the pattern near a corresponding portion of the second signal (e.g., an IC signal). The user may select the size of the portion of the first signal and the size of the portion of the second signal to be displayed. For example, the user may use a time interval (e.g., 150 milliseconds) to select the size of the portion of the first signal.

In the waterfall view, each new portion of the first signal that matches the pattern and the corresponding portion of the second signal may be displayed vertically by the display module 2618 whenever the pattern is detected in the first signal. In other words, in the waterfall view, the display module 2618 may display signals along a vertical time axis.

In fig. 37A, a real-time viewing area 3702 illustrates a near real-time display of two different signals (e.g., V2P 1 and ab1.d) in a waterfall view. In FIG. 37A, signals V2[ P1] and AB1.d are shown side-by-side stacked on top of each other. For example, at about 10 seconds, signal portion 3704 is displayed alongside signal portion 3706. Signal portion 3704 may represent a portion of signal V2P 1 that matches a given pattern (e.g., heart beat P1, lead V2) at a time of approximately 10 seconds. Signal portion 3706 may represent the corresponding portion of signal AB1.d when a given pattern matches signal V2[ P1 ].

A user (e.g., a physician) may find a waterfall view to be advantageous. First, the waterfall view allows the user to compare corresponding portions of two signals side-by-side. Second, because the signals are vertically stacked, the waterfall view may display the signals on the display screen for a longer period of time. Conversely, when signals are displayed from left to right, it is often difficult for a user to analyze the signals because they are no longer displayed on the display screen after a short time.

Fig. 37B illustrates a correspondence between signals in a conventional display module 2618 and a display module 2618 configured as a waterfall view, according to some embodiments. Fig. 37B includes a real-time viewing area 3708 and a waterfall view 3710. Fig. 37B is discussed with reference to fig. 26.

In fig. 37B, the real-time viewing area 3708 illustrates a near real-time display of two different signals (e.g., V2[ P1] and ab1. d). Waterfall view 3710 illustrates a near real-time display of the same two signals, except that signals V2P 1 and ab1.d are displayed side-by-side to appear stacked on top of each other. In the waterfall view 3710, each time a signal pattern in the signal is detected, the display module 2618 may vertically display a portion of the signal matching the signal pattern and a corresponding portion of the second signal.

For example, in FIG. 37B, signal portion 3712 of signal V2[ P1] includes a signal pattern. The corresponding signal portion 3714 of signal AB1.d corresponds to signal portion 3712 at the time of detection. In fig. 37B, waterfall view 3710 displays signal portion 3712 and corresponding signal portion 3714 side-by-side (e.g., together) each time a signal pattern is detected in signal V2P 1. In fig. 37B, waterfall view 3710 shows a portion of signal V2P 1 from oldest to newest that matches the signal pattern and a corresponding portion of signal ab1. d. In other words, in fig. 37B, waterfall view 3710 scrolls upward over time to display heart beats with the oldest heart beat at the top and the newest heart beat at the bottom. As one of ordinary skill in the art will appreciate, waterfall view 3710 may display heart beats in various other ways, such as, for example, with the newest heart beat at the top and the oldest heart beat at the bottom.

Fig. 37C illustrates the use of a display module 2618 configured as a dynamic view in accordance with some embodiments. Fig. 37C includes a real-time viewing area 3716. Fig. 37C is discussed with reference to fig. 26.

The real-time viewing region 3716 may contain a near real-time display of the display module 2618. The real-time viewing region 3716 may use a dynamic view to display a near real-time display of the display module 2618. In a dynamic view, the user may select a trigger (e.g., associated with a stored heart beat) for the signal. The user may select a trigger from a variety of trigger types. The trigger type may be a signal of interest characteristic associated with a secondary event of interest. When a trigger occurs, the display module 2618 may dynamically adjust the offset of the signal so that it is fixed to the baseline. This prevents the signal from advancing and moving away from the display screen. This is often important in a clinical setting, for example, in which case, for example, the height of a signal peak may indicate a particular type of lesion, while a signal plateau may indicate the effectiveness of ablating the lesion.

In fig. 37C, real-time viewing region 3716 illustrates a reference heart beat measured at a reference time (e.g., reference time 3724) for a unipolar signal (e.g., Uni 1). This may occur, for example, during ablation. In fig. 37C, because signal Uni1 was captured at reference time 3724, signal 3718 may be the initial heart beat, signal 3720 may be the current heart beat, and signal 3722 may be the maximum recorded heart beat. As discussed, in a dynamic view, a user may specify a reference location that determines a signal point that is fixed to a baseline. In FIG. 37C, this point is at fixed location 3726 (e.g., 0.0mV) of signal Uni1 on the screen. This may cause signal Uni1 to deflect such that it is fixed at fixed position 3726.

Fig. 37D illustrates the use of a display module 2618 configured as a trigger view in accordance with some embodiments. Fig. 37D includes a real-time viewing region 3728 and a trigger view 3730. Fig. 37D is discussed with reference to fig. 26.

The real-time viewing region 3728 may include a near real-time display of the display module 2618. In fig. 37D, the trigger view 3730 illustrates the display of the live view region 3728 using the trigger view. In trigger view 3730, the user may select a first signal (e.g., pacing signal 3732) that triggers the display of other signals (e.g., II signal 3734, Uni Dist signal 3736, and Uni Prox signal 3738). The user may select a particular trigger for the first signal. The user may select a trigger from a plurality of trigger types. The trigger type may be a signal of interest characteristic associated with a secondary event of interest. For example, the user may select a particular voltage (e.g., 60 millivolts) for the first signal. One of ordinary skill in the art will appreciate that other signal characteristics may be selected. When a trigger occurs, the display module 2618 may display a designated one or more signals that are synchronized in time and vertically stacked in the display. The user (e.g., physician) may find it advantageous to trigger the view. As it may make it easier for a user to view events that occur relative to an event (e.g., the beginning of pacing signal 3732).

In the trigger view 3730, the user may also specify the time after the trigger occurs when the data is pinned to baseline. For example, in fig. 37D, the user sets the time to about 70 milliseconds after the trigger occurs. In FIG. 37D, the UniDist signal 3736 and UniProx signal 3738 are fixed and always in the trigger view 3730 in response to the user setting the time to approximately 70ms after the trigger occurs. In contrast, in FIG. 37D, the UniDist signal 3736 and the UniProx signal 3738 are not seen in the real-time viewing region 3728 because they are not fixed to the baseline.

Fig. 38 illustrates signal capture in a display of a display module 2618 configured as a review window in accordance with some embodiments. Fig 38 includes a real-time viewing area 3802 and a review window 3804. Fig. 38 is discussed with reference to fig. 26.

The real-time viewing region 3802 may include a near real-time display of the display module 2618. The review window 3804 may contain the previous display shown in the real-time viewing area 3802. To capture the display of the real-time viewing area 3802, the user may submit a capture request. For example, in fig. 38, the user may click on the review button 3806. In response, the review module 2624 may determine a capture configuration for the display module 2618. The capture configuration may include one or more active signal modules 2614 for the display module 2618, a capture time, a selected view of the display module 2618, a color scheme for the one or more signals displayed, and various other settings as will be understood by those of ordinary skill in the art. After determining the capture configuration, the review module 2624 may apply the capture configuration to the previously stored signal samples and display the output in the review window 3802.

Fig. 39 illustrates amplitude measurements performed in a display of a display module 2618 configured as a review window in accordance with some embodiments. Fig. 39 includes a live view region 3902 and a review window 3904. Fig. 39 is discussed with reference to fig. 26.

The real-time viewing region 3902 can include a near real-time display of the display module 2618. The review window 3904 may contain a previously captured display shown in the real-time viewing area 3802. The user may analyze the previously captured output in the review window 3904 using vertical and horizontal calipers. The horizontal caliper may be a GUI selection widget. The user may measure the amplitude of a particular signal in millivolts (mV) using a horizontal caliper. For example, as shown in fig. 39, the user may click on the top and bottom of the V1 signal to generate two horizontal lines (e.g., caliper lines 3908 and 3910). The user may then hover the cursor along the V1 signal to display the measured amplitude (e.g., measurement 3906) at a particular point in time. Similarly, the vertical caliper may also be a GUI selection widget. The user can use a vertical caliper to measure time (in milliseconds) or Beats Per Minute (BPM). As shown in fig. 65, the user may click along the signal at the left and right points to generate two vertical lines and display the measured time or heart beats per minute between the two vertical lines. For example, as shown in pop-up box 6506, the time between vertical calipers 6502 and 6504 is 464 milliseconds or 129 BPM.

For embodiments related to ECG and IC signal visualization, the following method description is provided for near real-time processing and display of multiple signals. One of ordinary skill in the art will appreciate that these methods can be equally applied to the visualization of other small physiological signals.

Fig. 40 is a flow diagram of a method 4000 for processing and displaying multiple signals in near real-time according to some embodiments.

The method 4000 will be described with reference to fig. 26. Method 4000 is not limited to this example embodiment, however.

In 4002, a configuration path module 2620 configures one or more signal modules 2614. 4002 may be performed by method 4100 in fig. 41.

In 4004, an input module 2604 receives one or more signal samples for one or more signals. For example, input module 2604 may receive one or more signal samples for an IC signal and one or more signal samples for an ECG signal. 4004 may be performed by method 4400 in fig. 44.

In 4006, input module 2604 distributes one or more signal samples to packetizer 2606.

In 4008, a packetizer 2606 converts the one or more signal samples into one or more packets. 4008 may be performed by method 4500 in fig. 45.

In 4010, the packetizer 2606 distributes one or more packets to the queuing module 2608. 4010 can be performed by method 4600 in fig. 46.

In 4012, the packet distributor 2610 distributes the packet from the queuing module 2608 to the signal module 2614 associated with the packet. 4012 can be performed by method 4700 in fig. 47.

In 4014, signal module 2614 of 4012 processes the packet using DSP 2904. 4014 can be performed by method 4800 in FIG. 48.

In 4016, a display module 2618 associated with signal module 2614 of 4012 displays the processed packets to a display screen. 4016 can be performed by method 4900 in fig. 49.

Fig. 41 is a flow diagram of a method 4100 for configuring one or more signal modules 2614, according to some embodiments.

The method 4100 will be described with reference to fig. 26. However, method 4100 is not limited to this example embodiment.

In 4102, the signal configuration module 2802 can receive one or more signal processing specifications. The signal processing specification may specify a base signal to be processed, the length of input and output packet queues for the signal module 2614, a digital signal processing function for processing the base signal, and one or more associated parameters for the digital signal processing function. In some embodiments, the signal configuration module 2802 may receive the signal processing specification from a file stored in memory. In some other embodiments, the signal configuration module 2802 may receive the signal processing specification from a GUI that enables a user to manually input the signal processing specification.

In 4104, the signal configuration module 2802 distributes one or more signal processing specifications to the signal factory module 2804.

In 4106, the signal factory module 2804 generates a signal module 2614 for each signal processing specification. 4106 may be performed by method 4200 in fig. 42.

Fig. 42 is a flow diagram of a method 4200 for generating a signal module 2614 according to a signal processing specification, according to some embodiments.

The method 4200 will be described with reference to fig. 26. However, method 4200 is not limited to this example embodiment.

In 4202, the signal factory module 2804 generates an input packet queue 2902 of the signal module 2614 based on the signal processing specification in 4106 of fig. 41. For example, the signal factory module 2804 generates the input packet queue 2902 by creating a queue data structure of a length specified in the signal processing specification.

In 4204, the signal factory module 2804 generates an output packet queue 2906 for the signal module 2614 based on the signal processing specification. For example, the signal factory module 2804 generates the output packet queue 2806 by creating a queue data structure of a length specified in the signal processing specification.

In 4206, factory signal module 2804 generates DSP 2904 for signal module 2614 using factory DSP module 2808 based on signal processing specifications. In particular, factory signal module 2804 can request factory DSP module 2808 to generate DSP 2904 based on a digital processing function and one or more signal processing parameters specified in a signal processing specification. For example, the DSP factory module 2808 can generate the DSP 2904 based on a low pass filter function and a particular cutoff frequency specified in a signal processing specification.

In 4207, the factory signal module 2804 connects the generated input packet queue 2902, the generated DSP 2904 and the generated output packet queue 2906 in the signal module 2614. Specifically, the factory signal module 2804 connects the output of the input packet queue 2902 to the input of the DSP 2904. The factory signal module 2804 further couples the output of the DSP 2904 to the input of the output packet queue 2906.

In 4210, the factory signal module 2804 configures the incoming packet queue 2902 to receive packets distributed from the packet distributor 2610. In some embodiments, the signal factory module 2804 can add rules to a lookup table associated with the packet distributor 2610. A rule may specify that packets associated with a given signal may be processed by a given signal module 2614.

In 4212, the signal factory module 2804 equalizes the associated processing delay for each signal module 2614 generated using the DSP delay equalizer 2806 so that each signal module 2614 simultaneously outputs processed packets to its output packet queue 2906. 4210 may be performed by the method 4300 in fig. 43.

Fig. 43 is a flow diagram of a method 4300 for equalizing processing delays associated with each DSP 2904 of one or more signal modules 2614, according to some embodiments.

The method 4300 will be described with reference to fig. 26. However, the method 4300 is not limited to this example embodiment.

In 4302, the DSP delay equalizer 2806 requests a processing delay associated with each DSP 2904 of the one or more signal modules 2614. The DSP delay equalizer 2806 may request the processing delay of the DSP 2904 using an API of its associated signal module 2614.

In 4304, the DSP delay equalizer 2806 receives the processing delay of the DSP 2904 from each of one or more signal modules 2614.

In 4306, the DSP delay equalizer 2806 determines a maximum processing delay among the received one or more processing delays.

In 4308, the DSP delay equalizer 2806 sets the DSP 2904 for each of the one or more signal modules 2614 to a maximum processing delay. For example, the DSP delay equalizer 2806 may use an API to set the processing delay of the DSP 2904 for each signal module 2614. In response, each DSP 2904 may be designed to process packets using its digital processing functionality and output the processed packets to the output packet queue 2906 at the end of the maximum processing delay. In some embodiments, if the DSP 2904 completes processing the packet using its digital processing functionality before the maximum processing delay ends, the DSP 2904 may block its output to the output packet queue 2906.

Fig. 44 is a flowchart of a method 4400 for receiving one or more signal samples for one or more signals using an input module 2604, according to some embodiments.

The method 4400 will be described with reference to fig. 26. However, method 4400 is not limited to this example embodiment.

In 4402, the input module 2604 receives signal samples for the underlying signal from data stored in a hardware device (e.g., electrodes connected to the patient) or a computer file. For example, a computer file may contain a previously recorded session of signal samples received from a hardware device. As one of ordinary skill in the art will appreciate, the input module 2604 may receive signal samples for multiple base signals simultaneously.

In 4404, the input module 2604 distributes the received signal samples to the packetizer 2606.

Fig. 45 is a flow diagram of a method 4500 for converting one or more signal samples to one or more packets using a packetizer 2606, in accordance with some embodiments.

The method 4500 will be described with reference to fig. 26. However, method 4500 is not limited to this example embodiment.

In 4502, a packetizer 2606 receives one or more signal samples from an input module 2604.

In 4504, the packetizer 2606 can optionally pre-process one or more signal samples. For example, the grouper 2606 may convert binary values of one or more signal samples into their corresponding physical values. As one of ordinary skill in the art will appreciate, the packetizer 2606 may perform various other types of pre-processing.

In 4506, packetizer 2606 generates a packet containing one or more signal samples for a given base signal. The packetizer 2606 may store a predetermined number of signal samples in the packets. In some embodiments, the packetizer 2606 may use a timer 2605 to ensure that each packet contains the same number of signal samples. Specifically, the packetizer 2606 may store signal samples received from the input module 2604 into packets until the timer 2605 is triggered.

In 4508, the packetizer 2606 assigns a label to the generated packet. The tag may correspond to a time period in which one or more signal samples in the packet are received. The packetizer 2606 can assign a new label to each subsequent packet. For example, the packetizer 2606 may first generate a packet containing sixteen (16) signal samples of a given base signal. In this case, the packetizer 2606 may store the first set of signal samples in a packet labeled 0. The grouper 2606 may store the second set of signal samples in a group labeled 15. The grouper may store subsequent sets of signal samples in groups labeled 31, 47, 64, etc.

Fig. 46 is a flow diagram of a method 4600 for distributing a packet containing one or more signal samples to a queuing module 2608, according to some embodiments.

The method 4600 will be described with reference to fig. 26. However, method 4600 is not limited to this example embodiment.

In 4602, the packetizer 2606 determines the base signal associated with the newly generated packet.

In 4604, the packetizer 2606 determines the queue 2702 in the queuing module 2608 associated with the determined base signal. The packetizer 2606 may use a lookup table to determine that the queue 2702 is associated with the determined base signal.

In 4606, the packetizer 2606 distributes packets containing one or more signal samples to the determined queue 2702.

Fig. 47 is a flow diagram of a method 4700 for distributing a packet from a queuing module 2608 to a signaling module 2614 associated with the packet, according to some embodiments.

Method 4700 will be described with reference to fig. 26. Method 4700 is not limited to this example embodiment, however.

In 4702, the packet distributor 2610 continuously scans the queue 2702 in the queuing module 2608.

In 4704, the packet distributor 2610 detects a new packet in the queue 2702.

In 4706, the packet distributor 2610 determines one or more signal modules 2614 in the global signal table 2612 that are designed to process the new packet. Because a new packet (e.g., multiple copies or "instances" of a packet) may be distributed to multiple signal modules 2614, the underlying signals associated with the packet may be processed simultaneously using different digital processing functions of the signal modules 2614.

In some embodiments, the packet distributor 2610 may use the global signal table 2612 to determine one or more signal modules 2614 designed to process instances of new packets. For example, the global signal table 2612 may be an array of fixed size. Each element of the array may be associated with a given base signal and, thus, a given queue 2702. Furthermore, each element of the array may itself be a fixed size array. Each element of the sub-array may be associated with a given signal module 2614. Accordingly, the packet distributor 2610 may determine one or more signal modules 2614 designed to process the new packet by examining corresponding elements in the sub-array associated with the underlying signal of the new packet.

In some other embodiments, the packet distributor 2610 may use a lookup table to determine one or more signal modules 2614 designed to process the new packet. In particular, the lookup table may map queue 2702 to one or more signal modules 2614.

In 4706, the packet distributor 2610 distributes the new packet to one or more signal modules 2614 determined in the global signal table 2612 for processing. In particular, the packet distributor 2610 inserts new packets into the input packet queue 2902 of the determined one or more signal modules 2614.

Fig. 48 is a flow diagram of a method 4800 for processing a packet using a signal module 2614 associated with the packet, in accordance with some embodiments.

The method 4800 will be described with reference to fig. 26. However, method 4800 is not limited to this example embodiment.

In 4802 DSP 2904 detects whether a new packet is available in incoming packet queue 2902 of signal module 2614. In some embodiments, the DSP 2904 may scan the incoming packet queue 2902 for new packets to be processed. In some other embodiments, the DSP 2904 may obtain notification that new packets are available in the input packet queue 2902.

In 4804, DSP 2904 retrieves new packets from incoming packet queue 2902 of signal module 2614.

In 4806 DSP 2904 processes the new packet using its associated digital signal processing function. In particular, DSP 2904 may apply its digital processing functions to one or more signal samples in a packet. In some embodiments, DSP 2904 may use its digital processing functionality to control how it processes packets based on one or more signal processing parameters designed for DSP 2904.

In 4808, DSP 2904 outputs the processed packet to output packet queue 2906. In some embodiments, the DSP 2904 may output processed packets to the output packet queue 2906 based on its designed maximum processing delay.

Fig. 49 is a flowchart of a method 4900 for displaying processed packets to a display screen using a display module 2618, according to some embodiments.

The method 4900 will be described with reference to fig. 26. However, method 4900 is not limited to this example embodiment.

In 4902, display module 2618 determines from which one or more signal modules 2614 the processed packet is displayed. In some embodiments, the display module 2618 may determine from which one or more signal modules 2614 to display the processed packets by maintaining a reference to the output packet queue 2906 of one or more signal modules 2614. The display module 2618 may store the reference in the local signal table 3002.

At 4904, the display module 2618 detects that a new packet is available in the output packet queue 2906 of one of the determined signal modules 2614.

In 4906, display module 2618 receives a new packet from the output packet queue 2906 of the determined one of signal modules 2614.

In 4908, display module 2618 determines the tag associated with the new packet.

In 4910, the display module 2618 receives new packets from the other output packet queue 2906 that match the determined tag.

In 4912, display module 2618 displays the received new grouping of one or more signal modules to a display screen. Because the display module 2618 displays the new packet with the same label, the display module 2618 synchronizes the display of the signal associated with the new packet.

Methods 4000, 4100, 4200, 4300, 4400, 4500, 4600, 4700, 4800, 4900 may be performed by processing logic that may include hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions executed on a processing device), or a combination thereof. It should be understood that not all steps may be required to implement the disclosure provided herein. Further, as one of ordinary skill in the art will appreciate, some steps may be performed simultaneously, or in a different order than shown in fig. 40-49.

In some embodiments, DSP 2904 may be based on a notch filter. Electrophysiology laboratories with many devices may tend to have a large number of line frequencies and harmonics (e.g., noise) that interfere with cardiac recordings. In north america, this is primarily 60Hz plus harmonics. Figure 50 illustrates an example of a signal (e.g., triangular spikes 5002) with superimposed 60Hz noise 5004, according to some embodiments.

In order to obtain accurate cardiac recordings, it is often desirable to remove noise while preserving the signal of interest. Conventional methods of removing 60Hz noise include the use of notch filters, which have zero transmission at 60 Hz. FIG. 51 illustrates an example of a conventional method of removing 60Hz noise using a notch filter with zero transmission (single notch) at 60Hz, according to some embodiments.

Fig. 52 illustrates an example of the result of applying the conventional filter of fig. 51, in accordance with some embodiments. As shown in fig. 52, the 60Hz signal is removed from the input signal 5202 to produce a filtered signal 5204. However, conventional filters may encounter a number of problems. For example, after a large spike 5206, a conventional filter may introduce overshoot and ringing (e.g., transient response) 5208 into the signal. The overshoot and ringing may be artifacts of the filter rather than a portion of the original input signal. This can result in a reduced accuracy of the cardiac recording.

Additionally, a conventional 60Hz notch filter may not reduce any harmonics of 60 Hz. For example, as shown in fig. 53, if the interference in the input signal 5302 is evaluated at both 60Hz and 180Hz, then 180Hz harmonics are still present at the output of the conventional filter. Fig. 53 illustrates an example of the 180Hz harmonic still present in filtered signal 5304 at the output of the conventional filter of fig. 51, in accordance with some embodiments.

Thus, as shown in fig. 53, the conventional notch filter may suffer from two problems. First, conventional notch filters may introduce overshoot and ringing 5306 into the signal. Second, conventional notch filters may not be able to reduce any higher order harmonics.

In some embodiments, DSP 2904 may apply a notch filter that does not introduce overshoot and ringing in the signal and reduces not only the first harmonics, but also higher order harmonics. The notch filter of DSP 2904 may solve the above technical problem of the conventional notch filter by extracting the interference noise and subtracting it from the noisy signal. This can remove interference without creating artifacts (e.g., overshoot and ringing) associated with conventional notch filters. The notch filter of DSP 2904 may reproduce one cycle of the interfering signal in a separate buffer (also referred to as a circular buffer, noise buffer, or data buffer) and subtract it from the noisy signal to extract the original data. Since the line frequency noise may be constant or nearly constant, the notch filter of DSP 2904 may use some variation in the average to improve the estimate over time. Since the frequency may be known, the size of the buffer may be predetermined. Additionally, a buffer that stores only one cycle may also store integer sub-harmonics of higher frequencies that may be subtracted from noisy data. Fig. 54 illustrates an example of notch filtering of a DSP 2904 for signals with 60Hz and 180Hz noise, according to some embodiments. Because the line frequency noise is constant, one interference cycle 5402 can be reproduced in the input signal and subtracted from each cycle 5404 of the successive cycles.

With 60Hz noise and a sample rate of 2000 samples per second, 33 1/3 samples are stored in the buffer. Since there may be an integer number of samples in the buffer, the notch filter of DSP 2904 may choose to use 100 samples and store exactly 3 cycles of 60 Hz. Figure 55 illustrates an example of a notch filter of DSP 2904 using 100 samples of input signal 5502 and storing exactly 3 cycles of 60Hz 5504, according to some embodiments.

To accumulate steady-state noise in the buffer, data may be collected during "quiet times" of the waveform. As one of ordinary skill in the art will appreciate, the silent period may be a period of time when no large spikes or edges are present in the input signal. The silent period can be determined by calculating the slope of the signal. Fig. 56 illustrates an example of a notch filter of DSP 2904 calculating a silence time in input signal 5602 according to some embodiments. Three cycles of noise data (interference) 5604 may be collected in a buffer during a silence time 5606. Subsequent cycles 5608, 5610, 5612 are averaged to create an accurate copy of interference 5604. Because the cycle time is constant for cycles 5606, 5608, 5610, 5612, only cycles of fundamental and harmonic frequencies accumulate. The cycles of the other frequencies are averaged to zero.

For each new point sampled from the incoming data, it can be determined whether it is in a "quiet time" of the signal. The silent period can be determined by calculating the slope of the signal. If the slope is above the threshold, the silence time may be determined to have started. If the new point is in the quiet time, it can be averaged with the previously stored data at that location in the buffer. Over time, this averaging process may accumulate copies of the noise that may be subtracted from the noisy signal. For those locations that are not in the quiet time, the buffer may not be updated, but the accumulated signal may still be subtracted. Fig. 57 illustrates an example of the notch filter of DSP 2904 accumulating 3 cycles of noise copies in the buffer per silence time 5702, 5704, 5706, 5708 and subtracting noise from a noisy signal, according to some embodiments. Since the buffer contents 5710, 5712, 5714, 5716 match the noise data in the silence times 5702, 5704, 5706, 5708, respectively, the noise can be modeled more accurately and the noise content of the displayed signal can be significantly reduced when subtracted.

Averaging results in a filter that peaks at line frequency 5802 and all harmonics (5804, 5806, etc.) as each sample is added to the buffer. This can selectively accumulate line frequencies and all harmonics and reject all other frequencies so that the notch filter of DSP 2904 only subtracts the additional noise at a fixed frequency. Figure 58 illustrates an example of the results of a notch filter or a buffer filter of DSP 2904 according to some embodiments. To produce the buffer filter shown in fig. 58, for example, 5% of the new samples are added to 95% of the accumulated values to update the buffer. In implementation specific cases, each new sample and other combined percentages of the accumulated values may be combined.

Fig. 59 is a flow diagram of a method 5900 for notch filtering noise from an input signal, in accordance with some embodiments. The method 5900 will be described with reference to fig. 29. However, method 5900 is not limited to this example embodiment.

In 5902, the DSP 2904 accesses an input signal that includes noise having a first harmonic frequency and that has noise. The frequency of the noise in the input signal may be substantially constant.

In 5904, DSP 2904 determines a period of silence in the input signal. The DSP 2904 can determine the silence period by calculating the slope of the input signal. The DSP 2904 may then determine the existence of a silence period based on the calculated slope being below a threshold.

In 5906, DSP 2904 stores noise samples of the input signal during the silence period in a buffer. The size of the buffer may be based on the frequency of noise in the input signal.

As part of the storage, DSP 2904 may average samples of the input signal with corresponding noise samples in a buffer to create average samples. DSP 2904 may then replace the corresponding noise samples in the buffer with the averaged samples.

In 5908, DSP 2904 subtracts samples in a single cycle of noise in a buffer from the input signal to create a filtered signal. The subtraction may remove the first and second harmonic frequencies from the input signal while avoiding the introduction of transient responses (e.g., ringing) in the filtered signal. The first harmonic frequency may be 60Hz and the second harmonic frequency may be 120Hz or 180 Hz.

In 5910, DSP 2904 repeats 5904 through 5908 to refine the filtered signal. As one of ordinary skill in the art will appreciate, the sample may be anywhere in the cycle. Moreover, the samples do not necessarily constitute a single cycle. In other words, the DSP 2904 may store multiple cycles of noise of the input signal in the buffer.

In some embodiments, DSP 2904 may be based on a high pass filter. Certain regions of the heart generate high frequency signals of very low amplitude that may be of interest during cardiac surgery. Physicians often wish to highlight noise and other large cardiac signals for review in the presence of these signals.

This can be achieved using a high pass filter. Fig. 60 illustrates an example of a conventional high pass filter 6002 in accordance with some embodiments. In this case, the 3db frequency 6004 of a conventional high pass filter may be about 200Hz to reject low frequencies. Additionally, since the frequencies of interest are typically higher than the line frequency (e.g., 60Hz), conventional high-pass filtering methods may include placing notches 6006 therein to eliminate interference from potentially large power line interference.

However, typical signals from intracardiac catheters may contain high frequency signals from conductive regions of the heart as well as sharp local spikes from various sources. Fig. 61 illustrates an example of a signal containing high frequency signals from conductive regions of the heart and sharp local spikes from various sources, in accordance with some embodiments. As shown in fig. 61, there are spikes 6102 similar to local near-field pulses (e.g., QRS, local spikes, transients, etc.) and short bursts of high frequency (e.g., 300Hz) cardiac signals 6104.

Fig. 62 illustrates an example of a resulting output of filtering the signal of fig. 61 using the high pass filter of fig. 60, in accordance with some embodiments. As shown in fig. 62, the low frequency components (e.g., baseline wander) are removed and, as needed, a high frequency cardiac signal 6202 is highlighted. However, the transient response of the high pass filter may leave an undesirable impulse (e.g., artifact) 6204 and some ringing at the output. In complex and larger waveforms, the physician can easily confuse the pulse 6204 with the high frequency cardiac signal 6202. This is problematic for accurate diagnosis and treatment.

In some embodiments, DSP 2904 may be based on a high pass filter that removes pulses while allowing high frequency signals of interest to pass. To remove the pulse, the input signal may be monitored for large drift and high signal slope (e.g., derivative). When these conditions are present, the output may be blanked for a fixed period before and after the occurrence of the condition, so that transient conditions are not shown on the displayed waveform. Fig. 63 illustrates an example of a resulting output of filtering the signal of fig. 61 using a high pass filter that removes pulses 6302, while allowing high frequency cardiac signals of interest 6304 to pass, in accordance with some embodiments.

Fig. 64 is a flow diagram of a method 6400 for high-pass filtering noise from an input signal, according to some embodiments. The method 6400 will be described with reference to fig. 29. However, method 6400 is not limited to this example embodiment.

In 6402, DSP 2904 accesses an input signal that includes noise and the high frequency signal of interest. For example, in applications of DSP 2904, fast conduction tissue recognition filtering may be performed to identify purkinje fibers, highly isotropic/low-anisotropic segments in myocardial architecture, and preferential conduction pathways in diseased tissue. In such applications, the DSP 2904 may access purkinje signals, such as high frequency signals of interest, in the presence of noise. DSP 2904 may use a notch filter to filter the input signal.

Artifacts may be specifically introduced and characterized when identified in the signal of interest, and then direct automation of filtering may be applied such that these diagnosed signals are used as templates to subtract/filter or otherwise process the signals from the retrieved full electrogram. For example, the system may record signals with and without irrigation through the catheter with the catheter in contact and the catheter stabilized. The differences may represent artifacts that may then be automatically characterized, templates created, and templates used to allow filtering and summing techniques of the system to remove the artifacts. As will be appreciated by those of ordinary skill in the art, such a system would be beneficial when used in existing defibrillators, as well as subcutaneously Implantable Cardioverter Defibrillators (ICDs).

In 6404, DSP 2904 high-pass filters the input signal to create a filtered signal.

In 6406, DSP 2904 isolates artifacts associated with noise in the filtered signal from the high frequency signal of interest. For example, DSP 2904 may isolate the impulse response.

DSP 2904 may isolate artifacts by calculating the slope of the filtered input signal. DSP 2904 may then determine that an artifact exists based on the calculated slope being above a threshold. The DSP may characterize the artifact in the artifact template. DSP 2904 may select a filter based on the isolated artifacts so that an artifact template may be used as a filter.

In 6408, DSP 2904 blanks the filtered signal for a fixed period before and after the isolated artifact. DSP 2904 may optionally use selected filters to perform blanking. This blanking may remove isolated artifacts and allow the high frequency signals of interest to pass through. DSP 2904 may buffer the filtered signal for a fixed period of time before and after the isolated artifact.

In some embodiments, DSP 2904 may perform pattern (or signal characteristic) matching. Pattern matching of cardiac signals may be based on some correlation. For example, the correlation may be a statistical correlation function or a mean absolute deviation.

The Correlation Function (CF) may be specified by equation 1.

Equation 1: correlation function

The mean absolute deviation function (MAD) can be specified by equation 2.

Equation 2: correlation function

For a surface ECG, there may typically be 12 leads in the set. In a pacing (pace) matching application, it may be desirable to correlate all 12 leads with all 12 leads of a reference heart beat. The reference heart beat may be a heart beat taken from the patient at a time when an abnormal heart beat is present, and may be compared to a paced heart beat from a catheter during electrophysiology. In other cases, only a subset of the leads may need to be correlated. In the case of a correlation function, the perfect match of the shape may be +1, while the directly opposite shape may be-1, and the amplitude similarity cannot be measured. For the MAD function, the perfect match may be 0, and directly opposite may be 1, and the amplitude difference may result in a worse matching effect.

For multiple lead comparisons, some similarity measure may need to be established. This may be the mean, median or extension of equation 1 or equation 2 that sums the numerator and denominator of all leads in the set. Additionally, leads with larger amplitudes or particular heart beat ranges representing features to be emphasized (e.g., Q-waves) may be given more weight.

In all comparisons, the leads can be normalized to have a 0DC offset. This may be because only the shape (and amplitude) is important in the comparison.

In some embodiments, the mode (or signal characteristic) may be selected using a vertical caliper. The vertical caliper may be a GUI selection widget. Fig. 65 illustrates an example of a review window 6500 for selecting a data range (typically one heart beat) using vertical calipers 6502, 6504, according to some embodiments.

The selected pattern may then be saved as a reference heart beat (or known signal pattern). Fig. 66 illustrates an example of saving a selected pattern as a reference heart beat, according to some embodiments. A "save new mode" window 6600 shown in fig. 66 can allow a user to view a previously saved heart beat (e.g., a known signal pattern) 6602 to decide whether a newly identified heart beat is sufficiently unique relative to the previously saved heart beat to merit separate saving. When a heart beat is stored, it may be assigned a unique name 6604, color 6606, and/or description (i.e., note) 6608.

When the user wants to initiate a search, the user can open a selectable mode window for searching by clicking on the select mode button 6510 in the review window 6500 of FIG. 65. Fig. 67 illustrates an example of a "select mode to search" window 6700 of selectable modes according to some embodiments. A window 6700 selecting a mode to search for may display a scrollable list 6710 of all stored modes. A checkbox 6720 on the left side of each list item may allow the user to select the associated mode. The selections may remain active until the user decides to change them. When the user clicks on each mode on the list 6710, a corresponding signal may be displayed in a window 6730 below the list box. The window 6730 may also display fields that allow the user to enter a confidence factor threshold (also referred to as a mode detection threshold 6740) that may be used to detect a mode. For example, the mode detection threshold 6740 is set to 80% in fig. 67.

After the user selects the mode to search and clicks "OK" 6750, the user may initiate a search by clicking on the "enable/disable mode" search button 6512, which may turn into an active state in the review window 6500 as shown in fig. 65. After clicking the button, a pattern search may begin and a heart beat matching the reference heart beat (e.g., a confidence level equal to or greater than a selected confidence factor threshold) is displayed on the review window 6500. The found modes may be displayed in two different modes (summary view and detailed view) of the review window 6500 of fig. 65. As shown in a review window 6800 of fig. 68, the user can use the button summary 6802 and details 6804 to switch between these two modes.

In the summary view, the pattern-matching signal segments displayed in the review window may be highlighted using the color associated with each pattern. Multiple patterns may overlap on the same segment of the signal. In the summary view, the overlapping sections may be displayed using different colors so that the pattern is more clearly visible in each segment.

FIG. 68 illustrates an example of a pattern search summary view in the review window of FIG. 65 in which multiple matching patterns are displayed, in accordance with some embodiments. As shown in fig. 68, four segments 6806, 6808, 6810, 6812 of the surface ECG signal are highlighted in a review window 6800. In this example, the two segments 6806, 6808 on the left side are displayed in two colors (or line patterns), which means that the patterns of these segments overlap. The two sections 6810, 6812 on the right are displayed in the color assigned to the pattern P1, indicating that only the P1 pattern was found in these sections.

FIG. 69 illustrates an example of the pattern search summary view 6900 in the review window of FIG. 68 in which a single matching pattern is displayed and other patterns are hidden, in accordance with some embodiments. The widget 6910 may be displayed on the right side when the matched mode segment is displayed. The window may allow the user to show or hide the matching sections associated with each pattern found. In its initial state, all found patterns can be checked. When the user unchecks the checkboxes 6912, 6914 next to each mode name, the corresponding highlighted section is hidden. As shown in fig. 69, the matching sections 6810, 6812 associated with the pattern P1916 are hidden. Thus, the monochrome sections 6810, 6812 in fig. 68 are not shown in fig. 69, and the monochrome sections 6810, 6812 are on the right side and only match the pattern P1. However, the left hand segments 6806, 6808 where patterns P1 and P4 overlap are now shown in FIG. 69 in the color associated with pattern P46918.

In the detail view, the mode details may be displayed one segment at a time. The detail view may be enabled by selecting detail 6804 in review window 6800 of fig. 68. In the detail view, the actual pattern may be displayed at the top of the matching segment using the color assigned to the pattern. Fig. 70 illustrates an example of a detail view for a signal in the review window of fig. 65, in accordance with some embodiments.

As shown in FIG. 70, detail view 7000 may display the schema details one at a time. For each section, if multiple patterns overlap, the pattern with the highest confidence factor may be shown first. However, the user may choose to view other overlapping patterns (e.g., with a lower confidence value) by checking their associated check boxes 7002, 7004 in the detailed view list 7006. In this case, the signal displayed in detail view 7000 may be automatically altered to reflect the newly selected mode. For example, as shown in fig. 70, pattern P17008 has the highest confidence value (e.g., 87.0%), and is therefore shown first.

In the detail view, the confidence value for each lead may be displayed using horizontal bars in the "confidence factor for each lead" table 7010, and the actual confidence values may be provided on top of those bars as shown in fig. 70. For example, lead I7012 indicates a confidence value of 79.6%. Confidence values above the user-set confidence level (e.g., when the search mode is selected) may be displayed as green and values below the threshold may be displayed as orange, e.g., visually indicating whether the confidence level of each individual lead meets the user-desired threshold. When the user clicks on any lead name in the "confidence factor for each lead" table 7010, the matching segment on the corresponding pattern and signal may be displayed in the "pattern and signal tracking" window 7014 below the "confidence factor for each lead" table 7010. Two buttons may be below the window, allowing the user to alter the time 7016 and amplitude scale 7018 on the displayed signal to accurately view the shape details of the signal. If the selected time 7016 or amplitude scale 7018 makes the signal portion visible, a scroll bar may be automatically displayed to allow the user to access any portion of the signal.

The detail view 7000 may also highlight the signal segments and associated matching patterns shown using bracket 7020. This may allow a user to easily identify the signal sections shown in detail view 7000. A match confidence factor 7022 for the pattern may also be indicated next to one of the brackets.

FIG. 71 illustrates an example window 7100 with a pattern matching confidence value provided by the leads (confidence factor 7102 for each lead), according to some embodiments. As shown in fig. 71, leads V17104 and V27106 are below the confidence threshold and are shown as orange.

The concept of creating templates for specific artifact-generating events may also be used by the disclosed system in pattern matching, as described for the method of fig. 64. For example, patterns of valve motion artifacts related to unipolar signals collected above and below the valve and within the coronary arteries can be used to create pattern templates so that the operator knows immediately whether the catheter is above the valve, below the valve, or in the coronary arteries. If the coronary contours within the pattern template are satisfied, the system may respond by not allowing energy delivery, for example, during an ablation procedure.

Fig. 72 is a flow diagram of a method 7200 for pattern matching according to some embodiments. The method 7200 will be described with reference to fig. 29. However, method 7200 is not limited to this example embodiment.

In 7202, DSP 2904 accesses the input cardiac signal.

In 7204, DSP 2904 matches a portion of the input cardiac signal to a known signal pattern. Known signal patterns may be captured during a previous patient procedure or a current patient procedure and stored in a pattern template. Known signal patterns may also be stored in a database.

DSP 2904 may match a portion of the input cardiac signal to a known signal pattern based on a correlation function. For example, DSP 2904 may match a portion of the input cardiac signal to a known signal pattern based on a Mean Absolute Deviation (MAD) function. DSP 2904 may also match a portion of the input cardiac signal to a known signal pattern based on the confidence value.

In 7206, a display module 2618 displays an indication of the degree of match. The indication of the degree of match may specify a location of cardiac pacing.

Fig. 73 is a flow diagram of a method 7300 for pattern matching according to some embodiments. The method 7300 will be described with reference to fig. 29. However, method 7300 is not limited to this example embodiment.

At 7302, DSP 2904 accesses the input cardiac signal.

At 7304, DSP 2904 accesses a detection threshold.

At 7306, DSP 2906 matches a portion of the input cardiac signal to a known signal pattern based on a detection threshold. The known signal pattern may be captured during a previous patient procedure or a current patient procedure. The known signal patterns may be stored in a database.

DSP 2904 may match a portion of the input cardiac signal to a known signal pattern based on a correlation function. For example, DSP 2904 may match a portion of the input cardiac signal to a known signal pattern based on a Mean Absolute Deviation (MAD) function.

DSP 2904 may match a portion of the input cardiac signal to a known signal pattern based on a weighted particular region of the known signal pattern. DSP 2904 may first match a portion of the input cardiac signal to a known signal pattern. The DSP 2904 may determine a first confidence value based on the first match. DSP 2904 may then match a portion of the second input signal to a known signal pattern. The DSP 2904 may determine a second confidence value based on the second match. The DSP 2904 may average the first confidence value and the second confidence value to create an average confidence value. DSP 2904 may then determine that the average confidence value is above the detection threshold.

At 7308, display module 2618 displays the highlighted portion of the input cardiac signal based on the matching. For example, the display module 2618 may display a highlighted portion of the input cardiac signal based on a color associated with the known signal pattern.

In some embodiments, DSP 2904 may perform late potential and early activation detection. By interpolating (interplate) the signal data displayed independently using a conventional late potential filter from early sites of activation to late sites of detected activation, the system can infer sites of conduction delay. The site (or region) may be highlighted using any compatible three-dimensional mapping system, which may allow the physician to guide catheter placement, record slow conduction at the site, and target ablation to the site. These features are difficult or even impossible to accomplish using a system where the region saturates when applying gain to small signals and thus slowly conducts may otherwise remain invisible to the physician.

Embodiments herein benefit from the high dynamic range of the system to interpolate data from early sites of activation to late sites of detected activation and display the data independently using a conventional late potential filter. Such an embodiment enables detection of late potentials and early activations in the main signal display window in real time (e.g., live) and during conversational playback. By clicking the "create and manage search" button in the main signal display window, the user can create search conditions for late or early activation, activate searches, and manage existing searches.

Fig. 74 illustrates an example of a search definition window 7400, according to some embodiments, the search definition window 7400 is used to create and manage searches for late potentials and early activations. To add the late potential search to the main signal display window, the user may click an "add late potential search" button 7402 within a search definition window (e.g., search definition window 7400 of fig. 74). In response, a late potential detection configuration window may be displayed and various search parameters may be defined by the user. Fig. 75 illustrates an example of a late potential detection configuration window 7500 for various search parameters that define a late potential, according to some embodiments.

The user may create at least one pattern to perform a late potential search. The user may specify various late potential search parameters that allow various types of searches. As shown in fig. 75, the user may define one or more of the following parameters: name of search (7502), selection of heart beat pattern for search (7504), reference point for search start (7506), which ECG lead is selected for heart beat detection (7508), which intracardiac lead is selected for late potential detection (7510), use of search interval and length from pattern reference (7512), heart beat detection confidence threshold percentage (e.g., 80%) (7514), selection of late potential detection confidence threshold percentage (e.g., 80%) (7516), and selection of late potential amplitude threshold (e.g., 0.015mV) (7518). As one of ordinary skill in the art will appreciate, various other parameters may be defined by the user.

Once all parameters are defined, a search may be activated. When a late potential is detected, the signal display window may display the position of the late potential and its confidence of detection. Figure 76 illustrates an example signal display window 7600 showing the location of late potentials 7602, 7604, 7606, 7608, 7610 and their confidence of detection, according to some embodiments. The review window may also display all late potentials detected under the search results tab. The newly created late potential search may be listed within a search definition window (e.g., search definition window 7400 of fig. 74). The newly created late potential search may be listed under the currently defined search field in the search definition window.

The user may add an early activation search in a similar manner to a late potential search. The user may specify various early activation search parameters to conduct various types of searches. The parameter may be equivalent to a late potential search parameter. The difference is that the search may take place in a search interval defined before the reference line. Fig. 77 illustrates an example of an early activation detection configuration window 7700 used to define various search parameters for early activation (similar to those described for fig. 75), in accordance with some embodiments.

Once all parameters are defined in the early activation detection configuration window 7700, a search may be activated. When an early activation is detected, the signal display window may show the location of the early activation along with its confidence and length of detection. Fig. 78 illustrates an example signal display window 7800, the example signal display window 7800 showing the location of the early activations 7802, 7804, 7806 and their confidence of detection, according to some embodiments. The review window may also display all early activations detected under the search results tab. The newly created early activation search may be listed within a search definition window (e.g., search definition window 7400 of fig. 74). The newly created early activation search may be listed under the currently defined search field in the search definition window.

The user may use the search definition window to manage defined late potentials and early activation searches. Fig. 79 illustrates an example of a search definition window 7900 for managing defined late potential searches and early activation searches, according to some embodiments.

In search definition window 7900, all active searches may be listed in "currently defined searches" window 7902, and the user may run, stop, delete, or modify the search. If the search is stopped, the user may resume running the search by clicking on the "run" button 7904. For example, as shown in FIG. 79, search EA1 is stopped 7906 and search LP1 is running 7908. In this case, the user may resume running the EA1 search and stop 7910 running the LP1 search or use other options (e.g., delete 7912 and modify 7914).

Fig. 80 is a flow diagram of a method 8000 for detecting early activation or late potentials according to some embodiments. Method 8000 will be described with reference to fig. 29. Method 8000, however, is not limited to this example embodiment.

In 8002, the first DSP 2904 accesses a first cardiac signal associated with the surface lead.

In 8004, the first DSP 2904 matches the heart beat of the first cardiac signal to a known signal pattern. The first DSP 2904 may match the heart beats of the first cardiac signal to a known signal pattern based on a correlation function. For example, the first DSP 2904 may match the heart beats of the first cardiac signal to a known signal pattern based on a Mean Absolute Deviation (MAD) function. The first DSP 2904 may match the heart beat of the first cardiac signal to a known signal pattern based on the confidence value. The confidence value may be user defined.

In 8006, the second DSP 2904 searches for early activation or late potentials in the second cardiac signal during the periods before and after the matched heart beat. The period may be a user defined period.

The second DSP 2904 may search for an early activation or late potential in a buffer that includes a portion of the second cardiac signal. The second DSP 2904 may search for early activation based on an amplitude threshold.

Using early activation or late potentials, the system can interpolate signal data from the catheter at the site of early activation to the site of late potential. The system can use a conventional late potential filter to independently display signal data. Using the interpolated signal data, the system can infer the location of the conduction delay. The system may also use interpolated signal data at a site in combination with a three-dimensional mapping system to guide further catheter placement, record slow conduction at the site, or target ablation of the site.

In some embodiments, the display module 2618 may display one or more signals using a waterfall view (e.g., the waterfall view in fig. 37A and 37B). The waterfall view window may vertically stack heart beats matching a selected pattern on a particular ECG lead and may display user-selected intracardiac signals alongside each detected heart beat. The latter may be shown in relation to a user defined interval of reference points within the heart beat pattern.

To set parameters for the waterfall view, the user may click on a "create waterfall view window" button located in the primary signal display toolbar. In response, a waterfall display configuration window may be displayed. Figure 81 illustrates an example of a waterfall display configuration window 8100 according to some embodiments.

As shown in fig. 81, the user may define one or more of the following parameters. The user may select a heart beat pattern 8102 to be searched (e.g., may select from saved heart beat patterns to be used in the waterfall view). The user may define a reference point 8104 on the heart beat pattern that will be used to display the interval. If the reference point has not been selected, the user may add the reference point by clicking on a heart beat pattern display window located below the heart beat pattern list. Similarly, the location of the existing reference point may be altered by clicking on the heart beat mode display window. The user may select the surface ECG lead 8106 for heart beat detection. The user may define a display interval 8108 (e.g., a starting point and length relative to a mode reference point) for the ECG leads. The user may select an intracardiac channel 8110 to search. The user may define a display interval 8112 (e.g., a starting point and length relative to a mode reference point) for the intracardiac leads. The user may also select a vertical scroll mode 8114 such as time or heart beat.

Figure 82 illustrates an example of a waterfall view 8200 using a time pattern in accordance with some embodiments. When the vertical scroll mode 8114 is set to the time mode, the matching signal may continuously scroll upward over time. Thus, when no heart beat matching the selected pattern is detected, the temporal pattern may show a gap 8202 between heart beats. In time mode, the last heart beat timestamp 8204 may be shown on the lower left corner of the window.

When the vertical scroll mode 8114 is set to the heartbeat mode, vertical auto-scrolling of the waterfall view window may be disabled and heartbeats may scroll up only when a new heartbeat is detected that matches the selected mode. Figure 83 illustrates an example of a waterfall view 8300 using a heart beat pattern, in accordance with some embodiments. In heart beat mode, each individual heart beat may carry a time stamp 8302.

Once all the parameters of the waterfall view are defined by the user, the waterfall view window may display two signals side by side as shown in fig. 82 and 83. The waterfall view window may display signals using a time pattern or a heartbeat pattern. The names of leads 8304, 8306 may be shown at the top of the window. The heart beat mode name 8208 may also be shown next to the ECG lead name 8206.

There may be buttons within the toolbar of the waterfall view window, such as waterfall parameter button 8210 and display parameter button 8212. The waterfall parameter button 8210 may allow a user to adjust display parameters while opening a waterfall view window. For example, the user may change the display interval, the vertical scroll mode, or any parameter as will be understood by one of ordinary skill in the art.

The user may disable this feature. FIG. 84 illustrates an example of a display parameter window 8400 according to some embodiments. The display parameter window 8400 may allow a user to change various display parameters. For example, the user may adjust the scaling 8402, 8404 of each lead using the option of resetting 8416, 8418 to a default value. The user can add 8406 or remove 8408 clipping. The user may alter the colors 8410, 8412 for each lead or subset of leads. The user may disable the displayed gradual change of heart beat (fading) 8414. In some embodiments, the displayed heart beats may fade as they move toward the upper portion of the waterfall view window.

In some embodiments, the EP hardware system may generate a clean unipolar signal according to some embodiments. The EP hardware system can generate a clean unipolar signal based on its having an ECG circuit board that processes the ECG signal using substantially the same path as each IC circuit board used to process its corresponding IC signal and a plurality of IC circuit boards that share substantially the same circuit configuration and components. A single Wilson Center Terminal (WCT) signal may be used for both the ECG circuit board and the multiple IC circuit boards.

In some embodiments, the EP hardware system may act as a central processing system for all other systems. The EP hardware system may include: an ECG circuit board configured to receive an ECG signal; a plurality of IC circuit boards each configured to receive an IC signal; a communication interface communicatively coupled to a remote device; and a processor coupled to the ECG circuit board, the plurality of IC circuit boards, and the communication interface. The EP hardware system may act as a central processing system by having its processor receive feedback from a remote device via a communication interface and control the remote device based on the ECG signal, the IC signal and the feedback from the remote device via the communication interface.

The EP hardware system may receive feedback from and control remote devices including, but not limited to, ultrasound machines, Radio Frequency (RF) generators, stimulators, three-dimensional imaging devices, intracardiac echocardiography (ICE) machines, fluoroscopy machines, and defibrillators. The remote device may be a variety of other types of devices, as will be appreciated by one of ordinary skill in the art. The EP hardware system may communicate with the remote device through a communication interface coupled to the remote device using communication protocols including, but not limited to, digital imaging and communications in medicine (DICOM), ethernet, Universal Serial Bus (USB), and Institute of Electrical and Electronics Engineers (IEEE) 802.11. As will be appreciated by those of ordinary skill in the art, the EP hardware system may use various other communication protocols to communicate with the remote device.

Implementation of computer system

Various embodiments may be implemented, for example, using one or more well-known computer systems, such as computer system 8500 shown in FIG. 85. One or more computer systems 8500 can be used, for example, to implement any of the embodiments discussed herein, as well as combinations and subcombinations thereof.

The computer system 8500 may include one or more processors (also referred to as central processing units, or CPUs), such as a processor 8504. The processor 8504 may be connected to a communication infrastructure or bus 8506.

Computer system 8500 can also include user input/output device(s) 8503 such as a monitor, keyboard, pointing device, etc., and computer system 8500 can communicate with communication infrastructure 8506 via user input/output interface(s) 8502.

One or more of the processors 8504 may be a Graphics Processing Unit (GPU). In one embodiment, the GPU may be a processor, which is a special-purpose electronic circuit designed to process mathematically intensive applications. GPUs can have a parallel structure that is effective for parallel processing of large blocks of data, such as the common mathematically intensive data of computer graphics applications, images, videos, and the like.

Computer system 8500 may also include a main or primary memory 8508, such as Random Access Memory (RAM). The main memory 8508 may include one or more levels of cache. The main memory 8508 may store control logic (e.g., computer software) and/or data therein.

Computer system 8500 may also include one or more secondary storage devices or memories 8510. The secondary memory 8510 may include, for example, a hard disk drive 8512 or a removable storage device or drive 8514. The removable storage drive 8514 may be a floppy disk drive, a magnetic disk drive, a tape drive, an optical disk drive, an optical storage device, a tape backup device, or any other storage device/drive.

Removable storage drive 8514 may interact with a removable storage unit 8518. The removable storage unit 8518 may comprise a computer usable or readable storage device having stored thereon computer software (control logic) or data. Removable storage unit 8518 may be a floppy disk, magnetic tape, optical disk, DVD, optical storage disk, or any other computer data storage device. Removable storage drive 8514 may read from or write to a removable storage unit 8518.

Secondary memory 8510 may include other components, devices, components, tools, or other methods that allow computer programs or other instructions or data to be accessed by computer system 8500. Such components, devices, assemblies, tools, or other methods may include, for example, a removable storage unit 8522 and an interface 8520. Examples of a removable storage unit 8522 and interface 8520 may include a program cartridge and cartridge interface (such as that found in video game devices), a removable memory chip (such as an EPROM, or PROM) and associated socket, a memory stick and USB port, a memory card and associated memory card socket, or any other removable storage unit and associated interface.

The computer system 8500 may further include a communications or network interface 8524. The communication interface 8524 may enable the computer system 8500 to communicate and interact with any combination of external devices, external networks, external entities, etc. (referred to individually and collectively by the reference 8528). For example, communication interface 8524 may allow computer system 8500 to communicate with external or remote devices 8528 over a communication path 8526, which may be wired or wireless (or a combination thereof) and may include any combination of a LAN, a WAN, the Internet. Control logic or data may be transferred to computer system 8500 and from computer system 8500 via communications path 8526.

Computer system 8500 can also be any of a Personal Digital Assistant (PDA), a desktop workstation, a portable or notebook computer, a netbook, a tablet, a smartphone, a smartwatch, or other wearable device, a part of the internet of things, or an embedded system, or any combination thereof, to name a few non-limiting examples.

Computer system 8500 can be a client or server that accesses or hosts any application or data via any delivery paradigm, including but not limited to remote or distributed cloud computing solutions; local or built-in software (cloud-based "built-in" solutions); "as-a-service" models (e.g., content as a service (CaaS), digital content as a service (DCaaS), software as a service (SaaS), managed software as a service (MSaaS), platform as a service (PaaS), desktop as a service (DaaS), framework as a service (FaaS), backend as a service (BaaS), mobile backend as a service (MBaaS), infrastructure as a service (IaaS), etc.); or a hybrid model containing any combination of the above examples or other service or delivery paradigms.

Any suitable data structures, file formats, and schemes in computer system 8500 can be derived from standards including, but not limited to, JavaScript object notation (JSON), extensible markup language (XML), another markup language (YAML), extensible hypertext markup language (XHTML), Wireless Markup Language (WML), MessagePack, XML user interface language (XUL), or any other functionally similar representation used alone or in combination. Alternatively, proprietary data structures, formats or schemes may be used exclusively or in combination with known or open standards.

In some embodiments, a tangible, non-transitory apparatus or article of manufacture comprising a tangible, non-transitory computer usable or readable medium having control logic (software) stored thereon may also be referred to herein as a computer program product or program storage device. This includes, but is not limited to, computer system 8500, main memory 8508, secondary memory 8510, and removable storage units 8518 and 8522, as well as tangible articles of manufacture embodying any combination of the foregoing. Such control logic, when executed by one or more data processing devices (such as computer system 8500), may cause such data processing devices to operate as described herein.

Based on the teachings contained in this disclosure, it will be apparent to a person skilled in the relevant art how to make and use embodiments of this disclosure in other ways than the data processing apparatus, computer system, or computer architecture shown in FIG. 85. In particular, embodiments may operate with software, hardware, and/or operating system implementations other than those described herein.

Conclusion

The EP recording system disclosed herein effectively removes noise and removes or isolates unwanted large signals while preserving the relevant components of the original small signals, i.e., while preserving the integrity of the original information in the EP environment. Conventional EP systems can successfully filter out noise, but can also filter out signal components having noise that a medical team wishes to see. Conventional EP systems may also use good software filtering algorithms to generate and introduce additional noise and undesirable artifacts that are not present in the original noise. Even when the conventional EP system employs the latest noise reduction method, the conventional EP system cannot effectively collect a clean small signal with high confidence in the presence of a large signal process such as defibrillation and ablation at the same time. This is because conventional EP systems do not have comprehensive signal acquisition and filtering solutions across the relevant frequency range (low (e.g., 0 to 100Hz), medium (e.g., above 100Hz to below 300kHz) and high (e.g., above 300kHz (including 300kHz)) and are unable to effectively process synchronous signals that differ by an order of 100s or 1000 s.

The disclosed EP system does not have to make compromises that conventional EP systems have to make. Rather, the disclosed EP system allows aspects of hardware and software to be executed in tandem to simultaneously: (1) operating the amplifier at high gain to see small signals; (2) preventing clipping and saturation by minimizing destructive large signal filtering in hardware to see large signals simultaneously, (3) processing the signals, separating them from each other in separate displays, removing any residual noise and synchronizing the separated signals, and finally (4) enabling the user to manipulate and analyze both large and small signals so that signal artifacts and events can be precisely time-event correlated.

The exemplary signal 2200 of fig. 22A-22B illustrates these concepts showing improvements in visualization of ECG or IC cardiac signals in the presence of large transients, ablation signals, defibrillation signals, and EP ambient noise after acquisition, filtering, and processing by the disclosed EP system. Fig. 22A illustrates the removal of noise from both small and large signals, and the avoidance of clipping when processing large signals. Conventional EP systems may provide a noisy cardiac signal 2203 and artificially clip the signal 2202 to limit the amplitude of the displayed signal to avoid the effects of saturation. The disclosed EP system acquires and clearly displays the weak signal 2214 and the strong signal 2205. With the disclosed EP system, no manual clipping is required, and the strong signal 2204 is fully qualified (not clipped).

Fig. 22B illustrates that in the presence of noise and large signal processes, the EP system can reveal the differential amounts of low amplitude cardiac signals and EP signal-related random artifacts. Window 2216 illustrates noisy signal 2208 with high amplitude and low amplitude differential 2206 of the desired signal as revealed by the disclosed EP system. In contrast, as shown in window 2218, conventional EP systems may not be successful in revealing both low amplitude and high amplitude differentials of the desired signal. In the case of a noisier signal, a low amplitude differential 2210 of the desired signal may be revealed, but in conventional EP systems, is more easily lost in the noise 2212. The high amplitude differential 2211 of the desired signal may be lost in conventional EP systems by artificial clipping.

Fig. 22C illustrates that the disclosed EP system is capable of removing 60Hz noise 2220 without saturation or delayed recovery, while retaining the component 2222 of the 60Hz signal that belongs to the original waveform 2224. In particular, component 2222, where original waveform 2224 coincided with artifact 2220, is not lost. In other words, when a large signal overlaps a small signal at the same time, the disclosed EP system can cleanly identify, acquire, and process both.

It should be understood that the detailed description section, and not any other sections, is intended to be used to interpret the claims. Other sections may set forth one or more, but not all exemplary embodiments contemplated by the inventor(s), and therefore, are not intended to limit the disclosure or the appended claims in any way.

While the present disclosure describes exemplary embodiments of exemplary fields and applications, it should be understood that the present disclosure is not limited thereto. Other embodiments and modifications thereof are possible and are within the scope and spirit of the disclosure. For example, and without limiting the generality of the paragraphs, the embodiments are not limited to the software, hardware, firmware, or entities illustrated in the figures or described herein. Furthermore, the embodiments (whether explicitly described herein or not) have significant utility for fields and applications other than the examples described herein.

Embodiments have been described herein with the aid of functional building blocks illustrating the implementation of specific functions and relationships thereof. Boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries may be defined so long as the specified functions and relationships (or equivalents thereof) are appropriately performed. Moreover, alternative embodiments may perform the functional blocks, steps, operations, methods, etc. in a different order than described herein. The present disclosure also extends to methods associated with using or otherwise implementing the features of the hardware and systems disclosed herein.

References herein to "one embodiment," "an example embodiment," or similar phrases, indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is within the knowledge of one skilled in the art to incorporate such feature, structure, or characteristic into other embodiments whether or not explicitly mentioned or described herein. Additionally, some embodiments may be described using the expression "coupled" and "connected" along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, some embodiments may be described using the terms "connected" or "coupled" to indicate that two or more elements are in direct physical or electrical contact with each other. The term "coupled," however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims appended hereto and their equivalents.