阅读说明：本技术 针对污染控制进行改进的光掩模及其形成方法 (Photomask with improved contamination control and method of forming the same ) 是由 赖建宏 张浩铭 林佳仕 王宣文 许有心 石志聪 吴于勋 于 2020-08-26 设计创作，主要内容包括：本发明实施例涉及针对污染控制进行改进的光掩模及其形成方法。本发明实施例涉及一种光掩模,其包含：衬底；多层堆叠,其安置在所述衬底上方且经配置以反射辐射；罩盖层,其在所述多层堆叠上方；及抗反射层,其在所述罩盖层上方。所述抗反射层包括第一图案,其中所述第一图案暴露所述罩盖层且配置为可印刷特征。所述光掩模还包含从俯视视角来看与所述可印刷特征隔开的吸收体。(Embodiments of the present invention relate to a photomask and a method of forming the same that are improved with respect to contamination control. An embodiment of the present invention relates to a photomask, which includes: a substrate; a multilayer stack disposed over the substrate and configured to reflect radiation; a cap layer over the multi-layer stack; and an anti-reflective layer over the cap layer. The antireflective layer includes a first pattern, wherein the first pattern exposes the capping layer and is configured as a printable feature. The photomask also includes an absorber spaced from the printable feature from a top-down perspective.)

1. A photomask, comprising:

a substrate;

a multilayer stack disposed over the substrate and configured to reflect radiation;

a cap layer over the multi-layer stack;

an antireflective layer over the cap layer, the antireflective layer comprising a first pattern, wherein the first pattern exposes the cap layer and is configured as a printable feature; and

an absorbent body separated from the printable features from a top view.

2. The photomask of claim 1, wherein the absorber is configured as a portion of the capping layer exposed by a second pattern of the antireflective layer, the second pattern being separate from the first pattern.

3. The photomask of claim 2, wherein the second pattern is a nonprintable feature.

4. The photomask of claim 1, wherein the cap layer comprises Ru or RuO₂。

5. The photomask of claim 1, wherein the absorber is disposed between the substrate and the multilayer stack, wherein the photomask further comprises a trench extending through the antireflective layer, the capping layer, and the multilayer stack, wherein the absorber is exposed through the trench.

6. The photomask of claim 5, wherein the trench is between an imaging region and a periphery of the photomask, further comprising a bridge portion spanning the trench and connecting the imaging region to the periphery.

7. A photomask, comprising:

a substrate;

a first absorber layer over the substrate;

a multilayer stack disposed over the first absorber layer and comprising alternating layers of molybdenum and silicon;

a cap layer over the multi-layer stack;

a second absorber layer over the cap layer; and

a trench extending through the first absorber layer, the cap layer, and the multi-layer stack and exposing a portion of the second absorber layer.

8. The photomask of claim 7, wherein the second absorption layer comprises an opening exposing a portion of the cap layer, wherein the opening is in the shape of a strip having a width of less than about 6 nm.

9. A method of forming a photomask, the method comprising:

depositing a first absorber layer over a substrate;

forming a multilayer stack over the first absorption layer, the multilayer stack configured to reflect a radiation beam;

depositing a cap layer over the multi-layer stack;

depositing a second absorber layer over the cap layer; and

etching the second absorber layer to form a first pattern and a second pattern, wherein the first pattern is to be transferred to a workpiece during a lithographic operation, and wherein the second pattern is configured as a non-printable feature for the workpiece.

10. The method of claim 9, further comprising etching a trench extending through the first absorber layer, the cap layer, and the multi-layer stack and exposing the second absorber layer.

Technical Field

Embodiments of the present invention relate to a photomask and a method of forming the same that are improved with respect to contamination control.

Background

In advanced semiconductor technology, the continuing shrinkage of device sizes and increasingly complex circuit arrangements have made the design and manufacture of Integrated Circuits (ICs) more challenging and expensive. In order to pursue better device performance with smaller footprint and less power, advanced lithography techniques, such as Extreme Ultraviolet (EUV) lithography, have been investigated as methods for manufacturing semiconductor devices having relatively small line widths (e.g., 30nm or less). EUV lithography employs a photomask to control the exposure of a substrate to EUV radiation to form a pattern on the substrate.

Although existing lithographic techniques have been improved, they have not been satisfactory in many respects. For example, contamination by foreign particles during an EUV lithographic process continues to cause significant problems.

Disclosure of Invention

An embodiment of the present invention relates to a photomask, comprising: a substrate; a multilayer stack disposed over the substrate and configured to reflect radiation; a cap layer over the multi-layer stack; an anti-reflective layer over the cap layer, the anti-reflective layer comprising a first pattern, wherein the first pattern exposes the cap layer and is configured as a printable feature (printable feature); and an absorber separated from the printable feature from a top view.

An embodiment of the present invention relates to a photomask, comprising: a substrate; a first absorber layer over the substrate; a multilayer stack disposed over the first absorber layer and comprising alternating layers of molybdenum and silicon; a cap layer over the multi-layer stack; a second absorber layer over the cap layer; and a trench extending through the first absorber layer, the cap layer, and the multi-layer stack and exposing a portion of the second absorber layer.

An embodiment of the invention relates to a method of forming a photomask, the method comprising: depositing a first absorber layer over a substrate; forming a multilayer stack over the first absorption layer, the multilayer stack configured to reflect a radiation beam; depositing a cap layer over the multi-layer stack; depositing a second absorber layer over the cap layer; and etching the second absorber layer to form a first pattern and a second pattern, wherein the first pattern is to be transferred to a workpiece during a lithographic operation, and wherein the second pattern is configured as a non-printable (non-printable) feature for the workpiece.

Drawings

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that the various components are not drawn to scale in accordance with standard practice in the industry. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

FIG. 1 is a block diagram of a lithography system according to some embodiments.

Figure 2A is a schematic cross-sectional view of a photomask according to some embodiments.

Fig. 2B and 2C are schematic top views of the photomask shown in fig. 2A, according to various embodiments.

Figures 3A through 3F are cross-sectional views of intermediate stages of a method of fabricating a photomask according to some embodiments.

FIG. 4 is a flow chart of a method of fabricating a photomask according to some embodiments.

Fig. 5 is a flow chart of a method of manufacturing a semiconductor device according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first member over or on a second member may include embodiments in which the first and second members are formed in direct contact, and may also include embodiments in which additional members may be formed between the first and second members, such that the first and second members may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as "below …," "below …," "below," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element(s) or component, as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 70 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the variations typically found in their respective testing measurements. Also, as used herein, the terms "about," "substantially," and "substantially" generally mean within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, the terms "about", "substantially" and "substantially" when considered by one of ordinary skill in the art mean within an acceptable standard error of the mean. Except in the operating/working examples, or unless otherwise expressly specified, all numerical ranges, amounts, values and percentages disclosed herein (e.g., numerical ranges, amounts, values and percentages of amounts of materials), durations, temperatures, operating conditions, quantitative ratios, and the like, are to be understood as being modified in all instances by the terms "about", "substantially" and "essentially". Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that may vary depending upon the desired properties. At the very least, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges may be expressed herein as from one end point to another end point or between two end points. All ranges disclosed herein are inclusive of the endpoints unless otherwise specified.

Extreme Ultraviolet (EUV) photomasks are typically reflective masks that contain a circuit pattern and transfer patterned EUV radiation to a wafer by reflection of incident EUV radiation during a lithographic operation. The layout of an EUV photomask includes an imaging region in which a circuit pattern is disposed. The photomask includes at least a light absorbing layer over the light reflecting layer, wherein the light absorbing layer is patterned to form a circuit pattern thereon. The photomask typically includes a cap layer between the light absorbing layer and the light reflecting layer. The patterned EUV light is reflected from the light reflecting layer, passes through the cap layer and the patterned light absorbing layer, and is radiated onto the wafer. The lithographic performance of EUV photomasks is sensitive to contamination, since contaminant particles may adhere to the surface of the cap layer or the light reflecting layer and form an additional material layer on the cap layer or the light reflecting layer. The light propagation path of EUV light may be altered by the added material layer and may adversely affect the fidelity (e.g., boundary definition) of the circuit pattern.

The present disclosure provides a photomask and a method of manufacturing the same. In the proposed photomask, a contaminant absorber is formed on one or more layers of the photomask and is used to reduce or eliminate the effects of the accumulation of contaminants on the light reflecting layer or the cap layer, for example, in an ultra-high vacuum (UHV) environment. A first type of contaminant absorber is provided in a border region of the photomask with a contaminant absorbing material to increase the area of contaminant absorption. A second type of contaminant absorber is formed in the cap layer, wherein absorber features are formed in the light absorbing layer to expose portions of the cap layer for absorbing contaminants. The first type and second type contaminant absorbers may be utilized alone or in combination. With the above-mentioned contaminant absorber, the effective thickness of the material above the capping layer or the light reflecting layer due to accumulated contaminants is reduced, and thus the idle time and cost for cleaning the photomask are reduced. Thus, the life span and the operation cycle of the photomask are improved.

FIG. 1 is a block diagram of a lithography system 100 according to some embodiments. The lithography system 100 is an EUV lithography system in the depicted example, but it may be other types of lithography systems, such as a Deep Ultraviolet (DUV) lithography system or a transmissive lithography system. Lithography system 100 includes an illumination source 102, an illumination optics module 104, a photomask module 106, projection optics module 108, and a wafer stage 110. It should be understood that other modules may be incorporated into the lithography system 100, but for simplicity they are not shown in FIG. 1.

The illumination source 102 is operable to generate a radiation beam having a wavelength suitable for lithography (e.g., a wavelength of less than about 50 nanometers (nm), and in some cases even as small as about 10nm to 15 nm). In particular, the wavelength of the radiation beam may be set to about 13.5nm for an EUV lithography system. In some embodiments, the illumination source 102 produces a radiation beam in a Laser Produced Plasma (LPP) or Discharge Produced Plasma (DPP) system, wherein a high power laser is used to produce a high energy plasma to form the radiation beam therefrom. In some embodiments, the illumination source 102 includes a vacuum chamber for generating a beam of radiation. Accordingly, the lithography system 100 may achieve improved resolution of the circuit pattern due to the small wavelength of the radiation beam.

Illumination optics module 104 is formed from one or more optical components for collecting, directing, or shaping incoming light from illumination source 102 to photomask module 106. For example, the illumination optics module 104 may include a collector for collecting the radiation beam generated by the illumination source 102. The illumination optics module 104 may also include a plurality of mirrors for reflecting radiation. The material of the mirror is selected to minimize radiation absorption by the radiation beam. In some embodiments, the mirror may include a stack of alternating molybdenum (Mo) and silicon (Si) layers to reduce absorption of the radiation beam. In some cases, additional anti-absorption coatings may also be utilized to further reduce radiation absorption. In some embodiments, illumination optics module 104 is enclosed in a vacuum chamber to reduce the effects of radiation absorption by ambient gases.

Photomask module 106 includes a photomask stage configured to hold a photomask that transfers a circuit pattern thereon to a target, such as a wafer on wafer stage 110, by patterning an incident beam of radiation from illumination optics module 104. In some embodiments, the photomask comprises a multilayer structure. The photomask is a reflective photomask (e.g., a phase shift mask) in this embodiment, but may be a transmissive photomask in other embodiments. The phase shift mask may be an attenuated phase shift mask (AttPSM) or an alternating phase shift mask (AltPSM). The structure of the photomask is described in more detail in subsequent paragraphs.

The radiation beam is directed from illumination optics module 104 to a photomask in photomask module 106 and then emitted to projection optics module 108. The projection optics module 108 may include one or more mirrors, lenses, condensers, and the like. In some embodiments, the projection optics module 108 may include a ring-field optical component. In some embodiments, projection optics module 108 includes an aperture (or slit) shaped like an arc to allow the patterned beam of radiation to pass through to the wafer on wafer stage 110. In various embodiments, the photomask module 106 is disposed above the projection optics module 108.

The wafer stage 110 is configured to hold a wafer to be patterned. In some embodiments, wafer stage 110 includes an electronic chuck (E-chuck) for holding the wafer using an electronic force. In other embodiments, wafer stage 110 comprises a clamp for mechanically securing the wafer. Wafer stage 110 may include a positioning device for moving the wafer during a lithography operation so that various regions of the wafer may be continuously stepped and scanned. In some embodiments, wafer stage 110 is positioned below projection optics module 108.

Fig. 2A is a schematic cross-sectional view of a photomask 200 according to some embodiments. The photomask 200 may be used as a photomask for performing EUV lithography operations in the photomask module 106 depicted in fig. 1, i.e., it is compatible with a radiation source having a wavelength between about 1nm and 100nm (e.g., 13.5 nm). However, the photomask 200 may also be suitable for Deep UV (DUV) or other suitable wavelengths. In embodiments in which photomask 200 is configured as a reflective mask, the patterned radiation for the wafer is formed by reflection of incident radiation through photomask 200. Referring to FIG. 2A, the structure of the photomask 200 includes a substrate 201, a contaminant absorbing layer 202, a multi-layer stack 204, a cap layer 206, and a light absorbing layer 208.

The substrate 201 is formed of a Low Thermal Expansion (LTE) material such as fused silica, fused quartz, silicon carbide, black diamond, and other low thermal expansion substances. In some embodiments, the substrate 201 is used to reduce image distortion due to mask heating. In the present embodiment, the substrate 201 includes a low defect level and smooth surface material properties. In some embodiments, the substrate 201 transmits a predetermined spectrum of light, such as visible wavelengths, infrared wavelengths near the visible spectrum (near infrared), and ultraviolet wavelengths. In some embodiments, the substrate 201 absorbs EUV wavelengths and DUV wavelengths.

The photomask 200 is partitioned into an imaging region 210 and a rim region 220, wherein the rim region 220 laterally surrounds and defines the imaging region 210. In some embodiments, the bezel area 220 includes a trench 220R that bounds the imaging area 210. The border region 220 also serves to prevent excess radiation around the boundaries of the imaging region 210 from leaking into the adjacent die field of the wafer. For this reason, the ratio of the reflectivity between the imaging area 210 and the bezel area 220 should be made as large as possible. In an embodiment, the bezel area 220 has a reflectivity of less than about 0.1%. In an embodiment, the bezel area 220 has a reflectivity of less than about 0.05% (e.g., 0.01%).

A contaminant absorber layer 202 is formed over the substrate 201. In some embodiments, the trench 220R of the bezel region 220 extends through the light absorbing layer 208, the cap layer 206, and the multi-layer stack 204. Portions of contaminant absorber layer 202 are exposed through trenches 220R. The exposed portions of the contaminant absorber layer 202 serve to absorb residual contaminants that adhere to the photomask 200. For example, the contaminant absorber layer 202 and hydrocarbon particles (e.g., CO)₂、CO、C₂H₄And CH₄) React to form a carbon-based layer thereon. The carbon-based layer tends to absorb the illuminating radiation beam, especially high-energy EUV light, and thus reduces the intensity of the patterned radiation beam. The attenuated patterned beam of radiation may result in underexposure and produce a pattern having a smaller width than intended. In some embodiments, the accumulated thickness of the carbon-based layer on cap layer 206 relative to the isolation pattern is greater thanThe accumulated thickness of the carbon-based layer on cap layer 206 relative to the densely packed pattern because the densely packed pattern spreads the same amount of contaminants over a contact area that is larger than the contact area of the isolation pattern. With the aid of contaminant absorber layer 202, hydrocarbon particles that would otherwise be absorbed by cap layer 206 in imaging region 210 are captured by contaminant absorber layer 202 through a process of physisorption or chemisorption. Accordingly, the adverse effects of contaminants on the imaging area 210 may be reduced. The contaminant absorber layer 202 is referred to as a first type contaminant absorber. The contaminant absorber layer 202 may have a thickness between about 0.05nm and about 20nm, between about 0.1nm and about 10nm, or between about 0.5nm and about 5 nm.

In some embodiments, contaminant absorbing layer 202 is formed of a material having strong catalytic properties to promote absorption of gaseous contaminants. In some embodiments, the material of the contaminant absorber layer 202 includes ruthenium (Ru), platinum (Pt), rhodium (Rh), palladium (Pd), iridium (Ir), and the like. In other embodiments, contaminant absorber layer 202 is composed of an oxide of Ru, Ti, Ce, Zr, or Al (e.g., RuO)₂、TiO₂、CeO₂、ZrO₂、Al₂O₃Etc.).

Further, the contaminant absorber layer 202 has a low reflectivity with respect to EUV radiation to prevent the radiation beam from leaking out of the trench 220R. In an embodiment, the contaminant absorber layer 202 has a reflectivity of less than about 0.1%. In an embodiment, the contaminant absorber layer 202 has a reflectivity of less than about 0.05% (e.g., 0.01%).

A multi-layer stack 204 is formed over the front side 201f of the contaminant absorber layer 202. The multi-layer stack 204 serves as a radiation reflective layer for the photomask 200. The multi-layer stack 204 may include pairs, where each pair is formed of a molybdenum (Mo) layer and a silicon (Si) layer. The number of alternating Mo and Si layers (i.e., the number of Mo/Si pairs) and the thicknesses of the Mo and Si layers are determined to facilitate constructive interference (e.g., Bragg reflection) of the individual reflected rays, and thus increase the reflectivity of the multilayer stack 204. In some embodiments, the reflectivity of the multilayer stack 204 is greater than about 60% for the wavelength of interest (e.g., 13.5 nm). In some embodiments, the number of Mo/Si pairs in the multi-layer stack 204 is between about 20 and about 80, e.g., 40. Further, in some embodiments, each of the Mo layers or each of the Si layers has a thickness between about 2nm and about 10nm (e.g., 7 nm). In some embodiments, the Si layer and the Mo layer have substantially the same thickness. In an alternative embodiment, the Si layer and the Mo layer have different thicknesses. The Si layer and the Mo layer may be formed by Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), plasma-enhanced CVD (PECVD), Atomic Layer Deposition (ALD), or any other suitable process.

A cap layer 206 is disposed over the multi-layer stack 204. In some embodiments, cap layer 206 is used to prevent oxidation of multi-layer stack 204 during the mask patterning process. In some embodiments, cap layer 206 is made of ruthenium (Ru) or ruthenium oxide (RuO)₂) And (4) preparing. Other cap layer materials (e.g., silicon dioxide (SiO)₂) Amorphous carbon, or other suitable composition) may also be used in the capping layer 206. Capping layer 206 may have a thickness between about 1nm and about 10 nm. In certain embodiments, the thickness of cap layer 206 is between about 2nm and about 4 nm. In some embodiments, cap layer 206 is formed by PVD, CVD, low temperature CVD (ltcvd), ALD, or any other suitable film forming method.

A light absorbing layer 208 is disposed over the cap layer 206. In some embodiments, the light absorbing layer 208 is an antireflective layer that absorbs radiation in the EUV wavelength range that impinges on the photomask 200. The light absorbing layer 208 may comprise chromium, chromium oxide, titanium nitride, tantalum oxide, tantalum boron nitride, tantalum, titanium, aluminum copper, combinations thereof, and the like. The light absorbing layer 208 may be formed from a single layer or multiple layers. For example, the light absorbing layer 208 includes a chromium layer and a tantalum nitride layer. In some embodiments, the light absorbing layer 208 has a thickness in a range between about 10nm and about 100nm, or between about 40nm and about 80nm (e.g., 70 nm). In some embodiments, the light absorbing layer 208 is formed by PVD, CVD, LTCVD, ALD, or any other suitable film forming method.

In some embodiments, an antireflective layer (not shown) is disposed over the light absorbing layer 208. The anti-reflective layer may reduce illuminating radiation having a wavelength shorter than the DUV rangeThe reflection of the light absorbing layer 208, and may comprise the same pattern as the underlying light absorbing layer 208. The anti-reflective layer may be a TaBO layer having a thickness between about 12nm and about 18 nm. Other materials may also be used, such as Cr₂O₃ITO, SiN and TaO₅. In other embodiments, a silicon dioxide film having a thickness between about 2nm and about 10nm is employed as the antireflective layer. In some embodiments, the antireflective layer is formed by PVD, CVD, LTCVD, ALD, or any other suitable film forming method.

In some embodiments, photomask 200 further includes conductive layer 212 on backside 201b of substrate 201. The conductive layer 212 may assist in engaging the photomask 200 with an electrical chuck mechanism (not separately shown) in a lithography system. In some embodiments, conductive layer 212 comprises chromium nitride (CrN), chromium oxynitride (CrON), or another suitable conductive material. In some embodiments, the conductive layer 212 comprises a thickness in a range from about 50nm to about 400 nm. The conductive layer 212 may have a surface area that is less than the surface area of the substrate 201. In some embodiments, the conductive layer 212 has a length or width in a range between 70% and 95% of the length or width, respectively, of the substrate 201. Conductive layer 212 may be formed by CVD, ALD, Molecular Beam Epitaxy (MBE), PVD, pulsed laser deposition, electron beam evaporation, ion beam assisted evaporation, or any other suitable film formation method.

Figure 2B is a schematic top view of the photomask 200 shown in figure 2A, according to various embodiments. Fig. 2A is a view along a section line AA in fig. 2B. Referring to fig. 2A and 2B, the bezel region 220 may be separated from the edge of the photomask 200 by a gap. Alternatively, in other embodiments, the bezel area 220 may extend to the edge of the photomask 200. The frame area 220 has a rectangular ring shape from a top view and surrounds the imaging area 210; however, other rim region shapes (e.g., annular rings or other suitable shapes) are also possible.

The light absorbing layer 208 includes a circuit pattern to be transferred to a wafer. Some portions of the light absorbing layer 208 cover the cap layer 206, while some other portions of the light absorbing layer 208 expose the cap layer 206. During a lithographic operation, portions of the radiation beam impinging on the photomask 200 are shielded by the light-absorbing layer 208 to form a patterned radiation beam, thus causing component layers of the correspondingly patterned wafer. In other words, the radiation beam is used to print a pattern on a wafer. Throughout this disclosure, the pattern 222 to be transferred into the light absorbing layer 208 of the wafer is referred to as a printable pattern or printable feature. The minimum width of the printable pattern 222 is determined by the resolution of the lithography system 100 and is typically governed by the Numerical Aperture (NA) and wavelength of the optics. The minimum width of the printable pattern 222 may be equal to or greater than the resolution of the lithography system 100. A printable pattern 222 having a width W1 less than the resolution will result in degraded image quality of the pattern, such as a polygon or circle with blurred edges. In some embodiments, the width W1 of the printable pattern 222 is greater than about 6 nm. In some embodiments, the width W1 of the printable pattern 222 is greater than about 4.75 nm.

The light absorbing layer 208 also includes another type of pattern 224 configured not to be transferred to the wafer. Instead, pattern 224 is formed as an opening that exposes underlying cap layer 206 to increase the area of contaminant absorption. In this regard, in addition to contaminant absorber layer 202, portions of cap layer 206 also serve as another contaminant absorber layer. The portion or surface of the cap layer 206 having the shape of the pattern 224 and exposed through the openings of the pattern 224 of the light absorbing layer 208 is referred to as a second type contaminant absorber. A contaminant absorbing pattern 224 is formed in the light absorbing layer 208 adjacent to or remote from the printable pattern 222. This type of pattern is referred to throughout this disclosure as a non-printable pattern or non-printable feature because it does not contribute to the circuit pattern formed on the wafer. The maximum width of the nonprintable pattern 224 is determined by the resolution of the lithography system 100 and is typically governed by the Numerical Aperture (NA) and wavelength of the optics. A nonprintable pattern 224 having a width greater than the resolution may result in the nonprintable pattern 224 being accidentally transferred onto the wafer. In some embodiments, the width of the non-printable pattern 224 is between 1nm and about 6nm given a lithographic radiation beam (i.e., EUV light) having a wavelength of about 13.5 nm. In some embodiments, the width of the nonprintable pattern 224 is between about 1nm and about 4.75nm given a lithographic radiation beam (i.e., EUV light) having a wavelength of about 13.5 nm. A non-printable pattern 224 having a width less than about 1nm may not result in a discernible performance improvement of contaminant absorption. In some embodiments, the non-printable pattern 224 is in the shape of a strip or slit having long sides and short sides, where the short sides have a second width W2 that is less than the length of the long sides. The maximum value of the second width W2 is less than the resolution of the lithography system 100, e.g., less than about 6nm or between about 1nm and about 6 nm. In some embodiments, if the second width W2 is greater than about 6nm, the likelihood of incorrectly transferring the unprintable pattern 224 increases. In some embodiments, if the second width W2 is less than about 1nm, it may not be sufficient to maintain the desired lithographic resolution of the nearby and isolated printable pattern or to function as contaminant absorption. In some embodiments, the non-printable pattern 224 is in a curved or serpentine shape to increase the absorbent area of the non-printable pattern 224 while maintaining its non-printability. Given a lithographic radiation beam (i.e., EUV light) having a wavelength of about 13.5nm, the curved or meandering shape of the nonprintable pattern 224 may have a width W2 of between about 1nm and about 6 nm.

In some embodiments, the non-printable pattern 224 is formed in a manner and shape similar to that of sub-resolution assist features (SRAFs) or scattering bars typically used in lithographic systems that apply non-EUV radiation beams. SRAFs may assist in forming printable patterns 222 having pattern images with higher contrast while achieving smaller line widths. In some embodiments, under an EUV lithography system, the printable pattern 222 alone is sufficient to produce a circuit pattern with a desired line width without the aid of SRAF. In some embodiments, the non-printable pattern 224 functions to improve the image quality of the printable pattern 222 as well as to absorb gaseous contaminants. In some embodiments, the non-printable pattern 224 includes separate scattering bars and laterally surrounds the printable pattern 222. In some embodiments, the non-printable pattern 224 is spaced from the printable features 222 by a distance of between 1nm and about 100nm, between about 5nm and 70nm, or between about 10nm and about 50 nm.

In some embodiments, the printable and non-printable patterns 222 and 224 have respective areas a1 and a 2. The non-printable pattern 224 may have a maximum value of area a2 that is less than about 80% of the minimum value of area a1 of the printable pattern 222. If the maximum value of area A2 exceeds about 80% of the minimum value of area A1, at least a portion of non-printable pattern 224 will likely be transferred to the wafer and adversely affect the layout of the circuit pattern. In some embodiments, the non-printable pattern 224 may have a maximum value of area a2 that is less than about 70% less than the minimum value of area a1 of the printable pattern 222.

Still referring to FIG. 2B, the rim region 220 forms a closed loop separating the imaging region 210 from the periphery of the photomask 200. The photomask 200 is typically secured to the photomask stage via an electrical chuck, and thus, the electric field may cause problems with electrostatic discharge (ESD) of the photomask 200. ESD is often found during lithographic operations, particularly under high power radiation beams (e.g., EUV light), and can cause damage to the photomask 200 if not properly handled. To this end, the contaminant absorption layer 202 may be selected to include a material having a low resistance to facilitate the conduction and distribution of electrostatic discharge (ESD) across the frame region 220 and the photomask 200 to reduce the likelihood of ESD damage. In some embodiments, the contaminant absorber layer 202 comprises a conductive material having a resistivity of less than about 12 μ Ω -cm, such as ruthenium (Ru), platinum (Pt), rhodium (Rh), palladium (Pd), iridium (Ir), combinations thereof, and the like.

Fig. 2C is a schematic top view of the photomask 240 shown in fig. 2A, according to another embodiment. Photomask 240 is similar to photomask 200 shown in FIG. 2B, except for the configuration of frame region 220. The photo mask 240 includes bridge portions in the bezel area 220 for connecting the periphery of the photo mask 240 to the imaging area 210. In other words, the bridge portion 230 extends across the groove 220R and interrupts the ring shape of the connected groove 220R in fig. 2B into an interrupted groove 220R. From the cross-sectional view, the bridge portion 230 may include at least one of the light absorbing layer 208, the cap layer 206, and the multi-layer stack 204. With the aid of bridge portion 230, imaging region 210 is electrically coupled to the periphery of photomask 240, thereby facilitating the distribution of ESD and reducing damage from ESD. In some embodiments, bridge portions 230 have a thickness between about 1 μm and about 30 μm or between about 5 μm and 20 μm measured along a direction parallel to the sides of photomask 200 of trenches 220RLength L of (a). In this scenario, the material of the contaminant absorber layer 202 may have a medium to high resistivity without adversely affecting the performance of the photomask 240. In some embodiments, the contaminant absorber layer 202 comprises ruthenium (Ru), platinum (Pt), rhodium (Rh), palladium (Pd), iridium (Ir), combinations thereof, or the like. In some other embodiments, the contaminant absorber layer 202 is made of a material having a resistivity above about 30 μ Ω -cm (e.g., an oxide of Ru, Ti, Ce, Zr, or Al (i.e., RuO)₂、TiO₂、CeO₂、ZrO₂、Al₂O₃) Combinations thereof, and the like). The contaminant absorber layer 202 in the configuration of the bezel area 220 shown in fig. 2B allows for a larger absorption area, while the contaminant absorber layer 202 having the configuration of the bezel area 220 shown in fig. 2C allows for more choices of materials for forming the contaminant absorber layer 202.

Although the two types of contaminant absorbers discussed above are shown to be advantageous in reducing contaminant accumulation on the capping layer of a reflective photomask, they are also applicable to other configurations of photomasks and lithography systems. For example, a lithography system using a transmissive photomask or a radiation beam having other wavelengths may also be susceptible to gaseous contaminants during a lithography operation, and a contaminant-absorbing layer or feature formed from the material of contaminant-absorbing layer 202 or cap layer 206 discussed above will effectively absorb contaminants and improve lithography performance.

Figures 3A through 3F are cross-sectional views of intermediate stages of a method of fabricating a photomask 300 according to some embodiments.

The completed photomask 300 may be similar to the photomask 200 in figure 2A. It should be understood that additional operations may be provided before, during, and after the processes shown in fig. 3A-3F, and that some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of operations/processes may be changed. Materials, configurations, dimensions, processes, and/or operations that may be employed in the following embodiments and detailed description thereof that are the same as or similar to materials, configurations, dimensions, processes, and/or operations described with respect to the preceding embodiments may be omitted.

Referring to fig. 3A, a stack of layers including a conductive layer 212, a substrate 201, a contaminant absorbing layer 202, a multi-layer stack 204, a cap layer 206, and a light absorbing layer 208 is provided. In some embodiments, the substrate 201 is initially provided or formed. A contaminant absorber layer 202 is deposited over the substrate 201.

The multi-layer stack 204 is deposited over the contaminant absorber layer 202 by alternately forming a single Mo layer 204A and a single Si layer 204B over each other or vice versa until a predetermined number of Mo/Si layer pairs is reached. In an embodiment, the multilayer stack 204 comprises a silicon layer as a bottom layer contacting the substrate 201. Subsequently, a cap layer 206 is deposited over the as-formed multi-layer stack 204. A light absorbing layer 208 is deposited over the cap layer 206. Each of the foregoing layers may be formed over each other in a blanket fashion.

In some embodiments, an antireflective layer is formed over the light absorbing layer 208. A conductive layer 212 may be formed on the backside of the substrate 201. In an embodiment, an etching operation is performed to remove a peripheral portion of the conductive layer 212, such that recession (indentation) of the conductive layer 212 with respect to the substrate 201 is formed.

In some embodiments, a mask layer 232 is disposed over the light absorbing layer 208. In embodiments in which an anti-reflective layer is present over the light absorbing layer 208, the mask layer 232 is formed over the anti-reflective layer. In some embodiments, the mask layer 232 is a hard mask layer and may be made of silicon, silicon-based compounds, chromium-based compounds, combinations thereof, and the like. In some embodiments, the chromium-based compound comprises chromium oxide, chromium nitride, chromium oxynitride, or the like. In other embodiments, TaO, TaN, Ru, RuB, TaB, TaBN, or TaBO is used as the mask layer 232. In some embodiments, the mask layer 232 has a thickness between about 4nm and about 20 nm.

The formation method of the foregoing layer may include CVD, ALD, PVD, sputtering, thermal oxidation, atmospheric pressure CVD (apcvd), low pressure CVD (lpcvd), low temperature CVD (ltcvd), laser-enhanced CVD (lecvd), plasma-enhanced CVD (pecvd), thermal evaporation, pulsed laser evaporation, electron beam evaporation, molecular beam epitaxy, ion beam-assisted evaporation, and the like.

A photoresist layer 234 is deposited over the mask layer 232. The photoresist layer 234 may be made of a photosensitive material or other suitable resist material. A photoresist layer 234 may be deposited over the mask layer 232 by CVD, ALD, PVD, spin coating, or other suitable film formation methods. The photoresist layer 234 is patterned according to a predetermined circuit pattern. The patterning of photoresist layer 234 may include maskless exposure such as electron beam writing, ion beam writing, developing photoresist layer 234, and etching unwanted portions of photoresist layer 204. The opening 234R is formed by a patterning operation.

Fig. 3B shows the patterning of the mask layer 232 from the patterned photoresist layer 234. The patterning of the mask layer 232 may include performing photolithography and etching steps on the mask layer 232 to form the opening 232R using the patterned photoresist layer 234 as an etch mask. The opening 232R is formed as a downward extension of an opening 234R that runs through the mask layer 232 and exposes the light absorbing layer 208. Exemplary patterning processes include photomask alignment, exposing and developing the mask layer 232, and etching the mask layer 232. The photoresist layer 234 is then removed as depicted in fig. 3C. The removal operation may include an etching or ashing operation.

In fig. 3D, the light absorbing layer 208 is patterned according to the patterned mask layer 232. The patterning operation of the light-absorbing layer 208 may include performing photolithography and etching steps on the light-absorbing layer 208 to form the openings 208R using the mask layer 232 as an etch mask. The opening 208R is formed as a downward extension of the opening 232R that extends through the light absorbing layer 208 and exposes the cap layer 206. Exemplary patterning processes include photomask alignment, exposing and developing the light absorbing layer 208, and etching the light absorbing layer 208. In some embodiments, the patterning of the light absorbing layer 208 forms printable and non-printable patterns during the same patterning operation using the same mask layer 232 as an etch mask. In some embodiments, the mask layer 232 is removed after the light absorbing layer 208 has been patterned. The removal operation may include an etching or ashing operation. The pattern in the light absorbing layer 208 (i.e., the openings 208R) is formed within an imaging region, such as the imaging region 210 shown in fig. 1.

Fig. 3E to 3F illustrate the formation of the frame region 220. Initially, a photoresist layer 236 is deposited over the patterned light absorbing layer 208 as shown in fig. 3E. The photoresist layer 236 may be formed of a photosensitive material or other suitable resist material. The photoresist layer 236 may comprise the same or different material as the photoresist layer 234. A photoresist layer 236 may be deposited over the light absorbing layer 208 by CVD, ALD, PVD, spin coating, or other suitable film forming method. The photoresist layer 236 may fill the opening 208R. As formed, a photoresist layer 236 is patterned where the border region 220 is located. The patterning of the photoresist layer 236 may include mask-based exposure or maskless exposure, developing the photoresist layer 236 and etching unwanted portions of the photoresist layer 236. The opening 236R is formed by a patterning operation.

An etching operation is performed according to the opening 236R to form the trench 220R of the bezel region 220. The etching operation may include dry etching, wet etching, combinations thereof, and the like. By the etching operation, the trench 236R extends through the light absorbing layer 208, the cap layer 206, and the multi-layer stack 204, and exposes the upper surface of the contaminant absorbing layer 202. In some embodiments, bridge portions 230 are left in the rim area 220 for connecting the imaging area 210 to the periphery of the photomask 200. In some embodiments, one or more layers of the bezel area 220 at the bridge portions 230 are removed, e.g., in a particular bridge portion 230, the light absorbing layer 208 is removed while leaving the cap layer and the multi-layer stack 204. By patterning the bridge portion, a plurality of divided trenches 236R are formed accordingly.

Referring to fig. 3F, after the trenches 236R are formed, the photoresist layer 236 is removed, and the trench (es) 220R are left in place. The removal operation may include an etching or ashing operation. Thus, the photomask 200 is completed. In some embodiments, the order of the steps for patterning the light absorbing layer 208 in fig. 3A-3D and the steps for forming the border region 220 in fig. 3E-3F may be changed.

FIG. 4 is a flow chart of a method 400 of fabricating a photomask according to some embodiments. At step 402, a first absorber layer is deposited over a substrate. In some embodiments, the first absorbent layer is a contaminant absorbent layer. At step 404, a multi-layer stack is formed over the first absorber layer. In some embodiments, the multilayer stack is configured to reflect a radiation beam of a wavelength of, for example, about 13.5 nm.

At step 406, a cap layer is deposited over the multi-layer stack. In some embodiments, the cap layer serves as another contaminant absorber layer. At step 408, a second absorber layer is deposited over the cap layer. In some embodiments, the second absorbing layer functions as a radiation absorbing layer.

At step 410, the second absorber layer is etched to form a first pattern and a second pattern different from the first pattern, wherein the first pattern is configured to be transferred to a workpiece during a lithography operation and the second pattern is configured as a non-printable feature for the workpiece.

Fig. 5 is a flow chart 500 of a method of manufacturing a semiconductor device according to some embodiments. Semiconductor devices may be fabricated using EUV masks, such as photomask 200 described with respect to fig. 2A-2C and 3A-3F. The method 500 begins at step 502, wherein a semiconductor substrate having a material layer is provided. The semiconductor substrate comprises a semiconductor material such as silicon. In some embodiments, the semiconductor substrate may comprise other semiconductor materials, such as silicon germanium, silicon carbide, gallium arsenide, and the like. In some embodiments, the semiconductor substrate is a p-type semiconductor substrate (acceptor type) or an n-type semiconductor substrate (donor type). Alternatively, the semiconductor substrate comprises another elemental semiconductor, such as germanium; a compound semiconductor comprising silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP; or a combination thereof. In yet another alternative, the semiconductor substrate is a semiconductor-on-insulator (SOI) substrate. In other alternatives, the semiconductor substrate may include a doped epitaxial layer, a graded semiconductor layer, and/or a semiconductor layer overlying another semiconductor layer of a different type (e.g., a silicon layer on a silicon germanium layer).

In some embodiments, the material layer may be a semiconductor layer, a dielectric layer, or a conductive layer. In some embodiments, the layer of material may be embedded in or deposited over the semiconductor substrate. The material layer may be formed from a single layer or may comprise a multi-layer structure.

At step 504, a photoresist layer is formed over the material layer. A photoresist layer may be formed over the material layer by CVD, PVD, ALD, spin coating, or other suitable film formation methods. The method 500 then continues with step 506, where the photoresist layer is patterned in a lithography operation using a photomask (e.g., the EUV photomask 200 as described above). In an embodiment, the photomask 200 may be disposed on a photomask stage of a lithography system and the semiconductor substrate is disposed on a wafer stage. The lithography operation may involve projecting patterned exposure radiation onto the photoresist layer through transmission or reflection by the photomask 200. Portions of the photoresist layer may be removed after the photolithography operation.

The method 500 continues with step 508 to pattern the material layer using the patterned photoresist layer as an etch mask. Then, the photoresist layer is removed. The removal operation may include an etching or ashing operation.

The advanced photolithography processes, methods, and materials described above may be used in many applications, including fin field effect transistors (finfets). For example, the fins may be patterned to produce the relatively close spacing between features disclosed above as being very suitable. Additionally, the spacers (also referred to as mandrels) used in forming the fins of the FinFET may be processed in accordance with the disclosure above.

According to an embodiment, a photomask comprises: a substrate; a multilayer stack disposed over the substrate and configured to reflect radiation; a cap layer over the multi-layer stack; and an anti-reflective layer over the cap layer. The antireflective layer includes a first pattern, wherein the first pattern exposes the capping layer and is configured as a printable feature. The photomask also includes an absorber separated from the printable feature from a top-down perspective.

According to an embodiment, a photomask comprises: a substrate; a first absorber layer over the substrate; a multilayer stack disposed over the first absorber layer and comprising alternating layers of molybdenum and silicon; a cap layer over the multi-layer stack; a second absorber layer over the cap layer; and a trench extending through the first absorber layer, the cap layer, and the multi-layer stack and exposing a portion of the second absorber layer.

According to an embodiment, a method of forming a photomask comprises: depositing a first absorber layer over a substrate; forming a multilayer stack over the first absorption layer, wherein the multilayer stack is configured to reflect a radiation beam; depositing a cap layer over the multi-layer stack; depositing a second absorber layer over the cap layer; and etching the second absorber layer to form a first pattern and a second pattern, wherein the first pattern is to be transferred to a workpiece during a lithographic operation, and wherein the second pattern is configured as a non-printable feature for the workpiece.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Description of the symbols

100 lithography System

102 illumination source

104 illumination optical module

106 photomask Module

108 projection optical module

110 wafer stage

200 photo mask

201 substrate

201b back side

201f front side

202 contaminant absorber layer

204 multilayer Stack

204A Mo layer

204B-Si layer

206 cover layer

208 light-absorbing layer

208R: opening

210 imaging zone

212 conductive layer

220 frame area

220R groove

Pattern/printable feature 222

224 pattern/contaminant absorbing pattern/non-printable pattern

230 bridge part

232 mask layer

232R opening

234 photoresist layer

234R opening

236 photoresist layer

236R opening/trench

240 photo mask

300 photo mask

400 method

402 step of

404 step of

406 step (c)

408 step of

410 step of

500 flow chart/method

502 step (step A)

504 step of

506 step of

508 step of

L is length

W1 width

W2 second Width