阅读说明：本技术 一种磁保持继电器掉电复位的电路 (Circuit for power-down reset of magnetic latching relay ) 是由 陈舒畅 何振良 于 2020-08-17 设计创作，主要内容包括：本发明公开了一种磁保持继电器掉电复位的电路,包括场效应管Q1、场效应管Q2、三极管Q3、场效应管Q4、场效应管Q5和继电器K,场效应管Q2和场效应管Q5的型号为AO3401,场效应管Q1的G极连接到二极管D2输出端,并连接到电容C1的输入端和电阻R2的输入端,场效应管Q1的S极与电容C1的输出端以及电阻R2的输出端相连后接地。本磁保持继电器掉电复位的电路,响应速度快,经济简单成本低,容易调试,无需人工干涉,使用灵活性高可以移植到不同的应用场合。(The invention discloses a circuit for resetting a magnetic latching relay in a power failure mode, which comprises a field effect transistor Q1, a field effect transistor Q2, a triode Q3, a field effect transistor Q4, a field effect transistor Q5 and a relay K, wherein the type of the field effect transistor Q2 and the type of the field effect transistor Q5 are AO3401, the G pole of the field effect transistor Q1 is connected to the output end of a diode D2 and connected to the input end of a capacitor C1 and the input end of a resistor R2, and the S pole of the field effect transistor Q1 is connected with the output end of the capacitor C1 and the output end of the resistor R2 and then grounded. The circuit for resetting the magnetic latching relay in the power failure mode is high in response speed, economical, simple, low in cost, easy to debug, free of manual interference and high in use flexibility, and can be transplanted to different application occasions.)

1. A circuit for resetting a magnetic latching relay in a power-down mode comprises a field effect transistor Q1, a field effect transistor Q2, a triode Q3, a field effect transistor Q4, a field effect transistor Q5 and a relay K, wherein a G pole of the field effect transistor Q1 is connected to an output end of a diode D2 and an input end of a capacitor C1 and an input end of a resistor R2, and an S pole of a field effect transistor Q1 is connected with an output end of the capacitor C1 and an output end of the resistor R2 and then grounded; the input end of the diode D2 is connected to the output end of the diode D1, the input end of the diode D1 is connected to the output end of the resistor R1, and the input end of the resistor R1 is connected to a Vin power supply end; the Vin power supply end is connected to the input end of a diode D3, the input end of a diode D4, the input end of a resistor R9 and the input end of a capacitor CE1, the output end of the capacitor CE1 is grounded, the output end of a diode D3 is connected to the S pole of a triode Q2, the input end of the resistor R3 and the input end of the resistor R4, the G pole of a triode Q2 is connected with the output end of the resistor R3 and then connected to the collector of a triode Q3 and the input end of the resistor R6, the D pole of a triode Q2 is connected to the input end of the capacitor CE2 and connected to the S pole of a field effect transistor Q5 and a pin; the output end of the diode D4 is connected to the input end of the resistor R5, the output end of the resistor R5 is connected to the base electrode of the triode Q3 and the input end of the resistor R7, and the emitter of the triode Q3 is connected with the output end of the resistor R7, the output end of the resistor R6 and the output end of the capacitor CE2 and then grounded; the input end of the resistor R9 is connected to the output end of the diode D8, the input end of the diode D8 is connected to the G pole of the triode Q5 and to the input end of the R10, and the output end of the resistor R10 is grounded.

2. The circuit for power-down reset of a magnetic latching relay of claim 1, wherein: the diode D7 is model IN 4148.

3. The circuit for power-down reset of a magnetic latching relay of claim 1, wherein: the type of the field effect transistor Q2 and the type of the field effect transistor Q5 are AO 3401.

4. The circuit for power-down reset of a magnetic latching relay of claim 1, wherein: the S pole of the field effect transistor Q5 is connected to the input end of the diode D7, the output end of the diode D7 is connected to the G pole of the field effect transistor Q4, and is connected to the input end of the capacitor C2 and the input end of the resistor R8, and the S pole of the field effect transistor Q4 is connected to the output end of the resistor R2 and the output end of the resistor R8 and then is grounded.

5. The circuit for power-down reset of a magnetic latching relay of claim 1, wherein: the D pole of the fet Q1 is connected to the input of the diode D5 and to pin 1 of the relay K1, and the output of the diode D5 is connected to the output of the diode D6 and to pin 2 of the relay K.

6. The circuit for power-down reset of a magnetic latching relay of claim 1, wherein: the input end of the diode D6 is connected to the D pole of the field effect transistor Q4 and to the pin 3 of the relay K, the pin 4 of the relay K is connected with the terminal output of K1, and the pin 5 of the relay K is connected with the terminal output of K2.

Technical Field

The invention relates to the technical field of magnetic latching relays, in particular to a circuit for resetting a magnetic latching relay in a power-down mode.

Background

Once the magnetic latching relay is closed, the power failure is not reset, the next time the power is on, the relay is mistakenly operated to influence loads and equipment connected to the relay, the existing magnetic latching relay is reset in a grounding mode by using an MCU (microprogrammed control unit) or manually, so that the cost and complexity are increased, and the use flexibility is not good.

The magnetic latching relay is widely used in a large-current application occasion, the drive is simple, the magnetic latching relay can be opened or closed only by giving corresponding pulses, the attraction state is still kept under the action of residual magnetism after the magnetic latching relay is powered off, if the magnetic latching relay is not reset, the attraction state can be still kept after the magnetic latching relay is powered on next time, the load and equipment which need time initialization cause misoperation, permanent damage can be caused to the equipment, the MCU reset circuit can not normally work in a severe environment, and a program runs out and crashes and the like.

The existing MCU needs additional cost for detecting power failure reset, program debugging is complex, software codes with poor anti-interference capability are too complex to facilitate debugging and maintenance, and redundancy of the codes influences program execution efficiency. Manual reset is inflexible, operation is not simple and troublesome enough, manual interference is needed, cost is high, circuit complexity and debugging are also complex, transplanting and changing are inflexible, and the like.

Based on the defects, the circuit for resetting the magnetic latching relay in the power-off state is provided.

Disclosure of Invention

The invention aims to provide a circuit for resetting a magnetic latching relay in a power-off state, which has the advantages of high response speed, economy, simplicity, low cost, easiness in debugging, no need of manual interference and high use flexibility, can be transplanted to different application occasions, and solves the problems of manual resetting, inflexibility, inconvenience in operation, manual interference, high cost, complex debugging of a circuit and inflexibility in transplanting and changing in the prior art.

In order to achieve the purpose, the invention provides the following technical scheme: a circuit for resetting a magnetic latching relay in a power-down mode comprises a field effect transistor Q1, a field effect transistor Q2, a triode Q3, a field effect transistor Q4, a field effect transistor Q5 and a relay K, wherein a G pole of the field effect transistor Q1 is connected to an output end of a diode D2 and an input end of a capacitor C1 and an input end of a resistor R2, and an S pole of a field effect transistor Q1 is connected with an output end of the capacitor C1 and an output end of the resistor R2 and then grounded; the input end of the diode D2 is connected to the output end of the diode D1, the input end of the diode D1 is connected to the output end of the resistor R1, and the input end of the resistor R1 is connected to a Vin power supply end; the Vin power supply end is connected to the input end of a diode D3, the input end of a diode D4, the input end of a resistor R9 and the input end of a capacitor CE1, the output end of the capacitor CE1 is grounded, the output end of a diode D3 is connected to the S pole of a triode Q2, the input end of the resistor R3 and the input end of the resistor R4, the G pole of a triode Q2 is connected with the output end of the resistor R3 and then connected to the collector of a triode Q3 and the input end of the resistor R6, the D pole of a triode Q2 is connected to the input end of the capacitor CE2 and connected to the S pole of a field effect transistor Q5 and a pin; the output end of the diode D4 is connected to the input end of the resistor R5, the output end of the resistor R5 is connected to the base electrode of the triode Q3 and the input end of the resistor R7, and the emitter of the triode Q3 is connected with the output end of the resistor R7, the output end of the resistor R6 and the output end of the capacitor CE2 and then grounded; the input end of the resistor R9 is connected to the output end of the diode D8, the input end of the diode D8 is connected to the G pole of the triode Q5 and to the input end of the R10, and the output end of the resistor R10 is grounded; the S pole of the field effect transistor Q5 is connected to the input end of the diode D7, the output end of the diode D7 is connected to the G pole of the field effect transistor Q4, and is connected to the input end of the capacitor C2 and the input end of the resistor R8, and the S pole of the field effect transistor Q4 is connected with the output end of the resistor R2 and the output end of the resistor R8 and then is grounded; the D pole of the field effect transistor Q1 is connected to the input end of the diode D5 and connected to the pin 1 of the relay K1, the output end of the diode D5 is connected to the output end of the diode D6 and connected to the pin 2 of the relay K, the input end of the diode D6 is connected to the D pole of the field effect transistor Q4 and connected to the pin 3 of the relay K, the pin 4 of the relay K is connected with the terminal K1 for output, and the pin 5 of the relay K is connected with the terminal K2 for output.

Preferably, the diode D7 has a model number IN 4148.

Preferably, the type of the field effect transistor Q2 and the type of the field effect transistor Q5 are AO 3401.

Compared with the prior art, the invention has the following beneficial effects:

the circuit for resetting the magnetic latching relay in the power failure mode is high in response speed, economical, simple, low in cost, easy to debug, free of manual interference and high in use flexibility, and can be transplanted to different application occasions.

Drawings

Fig. 1 is a schematic circuit diagram of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, a circuit for resetting a magnetic latching relay in a power failure mode includes a field effect transistor Q1, a field effect transistor Q2, a triode Q3, a field effect transistor Q4, a field effect transistor Q5 and a relay K, wherein the types of the field effect transistor Q2 and the field effect transistor Q5 are AO3401, the G pole of the field effect transistor Q1 is connected to the output end of a diode D2 and is connected to the input end of a capacitor C1 and the input end of a resistor R2, and the S pole of the field effect transistor Q1 is connected to the output end of a capacitor C1 and the output end of a resistor R2 and then is grounded; the input end of the diode D2 is connected to the output end of the diode D1, the input end of the diode D1 is connected to the output end of the resistor R1, and the input end of the resistor R1 is connected to a Vin power supply end; a Vin power supply terminal is connected to an input terminal of a diode D3, an input terminal of a diode D4, an input terminal of a resistor R9 and an input terminal of a capacitor CE1, an output terminal of the capacitor CE1 is grounded, an output terminal of a diode D3 is connected to an S pole of a transistor Q2, the S pole of the transistor R3 and the input terminal of the resistor R4, a G pole of a transistor Q2 is connected with an output terminal of the resistor R3 and then connected to a collector of a transistor Q3 and the input terminal of the resistor R6, and a D pole of a transistor Q2 is connected to the input terminal of the capacitor CE2 and connected to an S pole of a field effect transistor Q5 and; the output end of the diode D4 is connected to the input end of the resistor R5, the output end of the resistor R5 is connected to the base of the triode Q3 and the input end of the resistor R7, and the emitter of the triode Q3 is connected with the output end of the resistor R7, the output end of the resistor R6 and the output end of the capacitor CE2 and then grounded; the input end of the resistor R9 is connected to the output end of the diode D8, the input end of the diode D8 is connected to the G pole of the triode Q5 and to the input end of the R10, and the output end of the resistor R10 is grounded; the S pole of the field effect transistor Q5 is connected to the input end of the diode D7, the output end of the diode D7 is connected to the G pole of the field effect transistor Q4 and to the input end of the capacitor C2 and the input end of the resistor R8, wherein the model of the diode D7 is IN4148, and the S pole of the field effect transistor Q4 is connected to the output end of the resistor R2 and the output end of the resistor R8 and then grounded; the D pole of the field effect transistor Q1 is connected to the input end of the diode D5 and connected to the pin 1 of the relay K1, the output end of the diode D5 is connected to the output end of the diode D6 and connected to the pin 2 of the relay K, the input end of the diode D6 is connected to the D pole of the field effect transistor Q4 and connected to the pin 3 of the relay K, the pin 4 of the relay K is connected with the output end of the K1 terminal, and the pin 5 of the relay K is connected with the output end of the K2 terminal.

The magnetic latching relay power-down reset circuit has the following principle:

when the input voltage of the external Vin is normal, the field effect transistor Q1 and the field effect transistor Q2 are in forward bias conduction, the current flows through the K _ ON terminal of the relay K, the K1 terminal of the relay K and the K2 terminal of the relay K are closed, when the input voltage of the external Vin is in power failure, the voltage of the field effect transistor Q1 and the voltage of the field effect transistor Q2 are not maintained continuously, the field effect transistor Q1 and the field effect transistor Q2 are turned OFF, the current flows through the K _ ON terminal of the relay K, under the action of residual magnetism of the relay K, the K1 terminal of the relay K and the K2 terminal of the relay K are still closed, the grid of the field effect transistor Q5 is in reverse bias conduction, the field effect transistor Q4 is in forward bias conduction, the K _ OFF terminal of the relay K has the current which flows through the K1 terminal of the relay K and the K2 terminal of the.

The working process is as follows:

when Vin has normal working voltage, the diode D1 turns on the field-effect transistor Q1, the triode Q3 and the field-effect transistor Q2 are turned on, the diode D8 is turned on, the field-effect transistor Q5 is turned off, and the relay K is closed. When Vin is powered down and has no voltage, the diode D1 is not enough to break down and conduct, the field effect transistor Q1 is cut off, the triode Q3 is cut off without forward bias voltage, the field effect transistor Q2 is cut off without forward bias voltage, the diode D8 is cut off, and the field effect transistor Q5 is conducted in a reverse bias mode. When Vin is powered OFF, a reset power supply is provided by a capacitor CE2, according to different occasions, a capacitor CE2 can be formed by connecting a plurality of capacitors in parallel, a discharge loop formed by a field effect transistor Q4 and a relay K _ OFF is used for providing reset current of the relay K, and the relay K is reset and disconnected; the capacitor C2 needs to be adjusted according to the reset delay, so that the conflict between the K _ ON terminal of the relay K and the K _ OFF terminal of the relay K is avoided.

In summary, the following steps: the circuit for resetting the magnetic latching relay in the power failure mode is high in response speed, economical, simple, low in cost, easy to debug, free of manual interference and high in use flexibility, and can be transplanted to different application occasions.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.