阅读说明：本技术 半导体模块及其制造方法 (Semiconductor module and method for manufacturing the same ) 是由 G·特里奇伦加拉詹 于 2020-04-24 设计创作，主要内容包括：一种用于制造功率半导体模块装置(100)的方法包括：使无机填充物(81)与浇注材料(5)混合,由此制备包括第一浓度的无机填充物(81)的混合物,其中,所述无机填充物(81)具有高于浇注材料(5)的密度(ρ<Sub>cc</Sub>)的密度(ρ<Sub>f</Sub>)。所述方法还包括：将包括无机填充物(81)和浇注材料(5)的混合物填充到外壳(7)中,其中,半导体衬底(10)被布置在外壳(7)内,并且其中,至少一个半导体主体(20)被布置在半导体衬底(10)的顶表面上；执行沉淀步骤,在沉淀步骤期间,无机填充物(81)沉淀到半导体衬底(10)和所述至少一个半导体主体(20)上,由此形成包括浇注材料(5)的部分和无机填充物(81)的第一层(800)以及包括浇注材料(5)的剩余部分但没有无机填充物(81)的第二层(801)；以及使浇注材料(5)硬化。(A method for manufacturing a power semiconductor module arrangement (100) comprises: mixing an inorganic filler (81) with a casting material (5), thereby preparing a mixture comprising a first concentration of the inorganic filler (81), wherein the inorganic filler (81) has a density (ρ) higher than the casting material (5) cc ) Density (p) f ). The method further comprises the following steps: filling a mixture comprising an inorganic filler (81) and a casting material (5) into a housing (7), wherein a semiconductor substrate (10) is arranged within the housing (7), and wherein at least one semiconductor body (20) is arranged on a top surface of the semiconductor substrate (10); performing a precipitation step during which an inorganic filler (81) is precipitated onto the semiconductor substrate (10) and-on said at least one semiconductor body (20), thereby forming a first layer (800) comprising portions of the casting material (5) and the inorganic filler (81) and a second layer (801) comprising the remaining portions of the casting material (5) but without the inorganic filler (81); and hardening the casting material (5).)

1. A method for manufacturing a power semiconductor module arrangement (100), comprising:

mixing an inorganic filler (81) with a casting material (5), thereby preparing a mixture comprising a first concentration of the inorganic filler (81), wherein the inorganic filler (81) has a higher concentration than the casting material (5)) Density (p)_cc) Density (p)_f)；

-filling the mixture comprising the inorganic filler (81) and the casting material (5) into a housing (7), wherein a semiconductor substrate (10) is arranged within the housing (7), and wherein at least one semiconductor body (20) is arranged on a top surface of the semiconductor substrate (10);

Performing a precipitation step during which the inorganic filler (81) is precipitated down onto the semiconductor substrate (10) and the at least one semiconductor body (20), thereby forming a first layer (800) comprising a portion of the casting material (5) and the inorganic filler (81) and a second layer (801) comprising a remaining portion of the casting material (5) but without the inorganic filler (81); and

hardening the casting material (5).

2. The method according to claim 1, wherein the inorganic filler (81) has a molecular weight at 0.9g/cm³And 5.0g/cm³Density (p) between_f) And wherein the casting material (5) has a melt flow rate of at 0.2g/cm³And 0.9g/cm³Density (p) between_cc)。

3. The method according to claim 1 or 2, wherein the amount of inorganic filler (81) in the first layer (800) is between about 20 vol% and 90 vol%, or between about 60 vol% and 80 vol%.

4. Method according to any one of claims 1 to 3, wherein the casting material (5) comprises a non-reactive crosslinkable or non-crosslinkable polymer.

5. The method of claim 4, wherein the polymer comprises a silicone gel, a silicone rubber, or an epoxy.

6. The method according to any one of the preceding claims, wherein the inorganic filler (81) comprises at least one of silica, fused silica, crystalline silica, precipitated silica, alumina, beryllium, boron nitride, aluminum nitride, silicon carbide, boron carbide, titanium carbide, magnesium oxide, zinc oxide, or glass fibers.

7. The method according to any one of the preceding claims, wherein the inorganic filler (81) comprises particles having a diameter between 1 μm and 400 μm or between about 4 μm and 20 μm.

8. The method according to any of the preceding claims, wherein the first layer (800) is arranged between the second layer (801) and the semiconductor substrate (10).

9. The method according to any of the preceding claims, wherein the first layer (800) has a Coefficient of Thermal Expansion (CTE) with the semiconductor substrate (10) and the at least one semiconductor body (20)₁₀、CTE₂₀) Similar Coefficient of Thermal Expansion (CTE)₈₀₀) Such that CTE is₈₀₀＝CTE₁₀. + -. 5ppm/K and CTE₈₀₀＝CTE₂₀±5ppm/K。

10. The method of any one of the preceding claims,

the first layer (800) has a first thickness (d1) in a vertical direction (y) perpendicular to the top surface of the semiconductor substrate (10);

The second layer (801) has a second thickness (d1) in the perpendicular direction (y); and is

The second thickness (d2) is the same as the first thickness (d1), or the second thickness (d2) is less than or greater than the first thickness (d 1).

11. The method of any of the preceding claims, further comprising at least one of:

heating the power semiconductor module arrangement (100) during the precipitation step, thereby liquefying the casting material (5); and

the precipitation step is performed in vacuo.

12. A power semiconductor module arrangement (100) comprising:

a semiconductor substrate (10), the semiconductor substrate (10) being arranged within a housing (7);

at least one semiconductor body (20), the at least one semiconductor body (20) being arranged on a top surface of the semiconductor substrate (10);

a first layer (800), the first layer (800) being arranged on the top surface of the semiconductor substrate (10), wherein the first layer (800) comprises an inorganic filler (81) being impermeable to corrosive gases and a casting material (5) filling any space present in the inorganic filler (81), and wherein the inorganic filler (81) has a density (p) higher than the casting material (5) _cc) Density (p)_f) (ii) a And

a second layer (801), the second layer (801) being arranged on the first layer (800), wherein the second layer (801) comprises the casting material (5) without the inorganic filler (81).

13. The power semiconductor module arrangement (100) according to claim 12, wherein the inorganic filler (81) has a thickness at 0.9g/cm³And 5.0g/cm³Density (p) between_f) And wherein the casting material (5) has a melt flow rate of at 0.2g/cm³And 0.9g/cm³Density (p) between_cc)。

14. The power semiconductor module device (100) according to claim 12 or 13, wherein the amount of the inorganic filler (81) in the first layer (800) is between about 20 vol% and 90 vol%, or between about 60 vol% and 80 vol%.

15. The power semiconductor module arrangement (100) according to any one of claims 12 to 14, wherein the inorganic filler (81) comprises particles having a diameter between 1 μ ι η and 400 μ ι η or between about 4 μ ι η and 20 μ ι η.

Technical Field

The present disclosure relates to a semiconductor module and a method of manufacturing the same.

Background

The power semiconductor module arrangement often comprises at least one semiconductor substrate arranged in a housing. A semiconductor arrangement comprising a plurality of controllable semiconductor elements (e.g. two IGBTs in a half-bridge configuration) is arranged on each of the at least one substrate. Each substrate typically includes a substrate layer (e.g., a ceramic layer), a first metallization layer deposited on a first side of the substrate layer, and a second metallization layer deposited on a second side of the substrate layer. For example, the controllable semiconductor element is mounted on a first metallization layer. The second metallization layer may optionally be attached to the substrate. The controllable semiconductor component is typically mounted on the semiconductor substrate by soldering or sintering techniques.

The wires or electrical connections are used to connect different semiconductor devices of the power semiconductor arrangement. Such wires and electrical connections may comprise metal and/or semiconductor materials. The housing of the power semiconductor module arrangement is generally permeable to gases to some extent. For example, some gases (e.g., sulfur-containing gases) may react with metal components inside the enclosure. This causes chemical degradation of these components, which can lead to failure of individual components and ultimately of the entire semiconductor device.

Therefore, the components inside the housing are typically protected from corrosion by encapsulating the components. Different materials are known which are suitable for protecting components inside the housing against corrosion. However, such materials may have a different Coefficient of Thermal Expansion (CTE) than the substrate and the components mounted on the substrate. Furthermore, the encapsulant materials used to reduce CTE mismatch may induce high stresses within the housing.

There is a need for a power semiconductor module in which semiconductor components are protected from corrosion and in which CTE mismatch and internal stresses between different components are reduced, thereby extending the overall life of the power semiconductor module arrangement.

Disclosure of Invention

A method for manufacturing a power semiconductor module device includes: mixing an inorganic filler with a casting material, thereby preparing a mixture comprising a first concentration of the inorganic filler, wherein the inorganic filler has a density higher than a density of the casting material. The method further comprises the following steps: filling a mixture comprising an inorganic filler and a casting material into a housing, wherein a semiconductor substrate is arranged within the housing, and wherein at least one semiconductor body is arranged on a top surface of the semiconductor substrate; performing a precipitation step during which an inorganic filler is precipitated down onto the semiconductor substrate and the at least one semiconductor body, thereby forming a first layer comprising a portion of the casting material and the inorganic filler and a second layer comprising a remaining portion of the casting material but no inorganic filler; and hardening the casting material.

A semiconductor module device includes: a semiconductor substrate disposed within the housing; at least one semiconductor body disposed on a top surface of the semiconductor substrate; a first layer disposed on a top surface of the semiconductor substrate, wherein the first layer includes an inorganic filler impermeable to a corrosive gas and a casting material filling any space present in the inorganic filler, and wherein the inorganic filler has a density higher than a density of the casting material; and a second layer disposed on the first layer, wherein the second layer comprises a casting material without an inorganic filler.

The invention can be better understood with reference to the following drawings and description. The components in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. Moreover, in the figures, like reference numerals designate corresponding parts throughout the different views.

Drawings

Fig. 1 is a cross-sectional view of a power semiconductor module arrangement.

Fig. 2 is a cross-sectional view of another power semiconductor module arrangement.

Fig. 3, which includes fig. 3A through 3D, illustrates steps of a method for manufacturing a power semiconductor module apparatus according to one example.

Fig. 4 shows exemplarily the generated forces occurring at the interfaces between the different elements and the encapsulating material.

Detailed Description

In the following detailed description, reference is made to the accompanying drawings. The drawings show specific examples in which the invention may be practiced. It should be understood that the features and principles described with respect to the various examples may be combined with each other unless otherwise indicated. In the description and claims, the designation of certain elements as "first element," "second element," "third element," etc. should not be construed as an enumeration. Rather, such designations are merely used to refer to various "elements". That is, for example, the presence of "a third element" does not require the presence of "a first element" and "a second element". The electrical wires or connections described herein may be a single conductive element or may include at least two individual conductive elements connected in series and/or parallel. The wires and electrical connections may comprise metal and/or semiconductor materials, and may be permanently conductive (i.e., non-switchable). The semiconductor bodies described herein may be composed of (doped) semiconductor material and may be or be comprised in a semiconductor chip. The semiconductor body has electrical connection pads and comprises at least one semiconductor element with an electrode.

Referring to fig. 1, a cross-sectional view of a power semiconductor module device 100 is schematically shown. The power semiconductor module device 100 includes a housing 7 and a semiconductor substrate 10. The semiconductor substrate 10 comprises a dielectric insulation layer 11, a (structured) first metallization layer 111 attached to the dielectric insulation layer 11 and a (structured) second metallization layer 112 attached to the dielectric insulation layer 11. The dielectric insulating layer 11 is disposed between the first metallization layer 111 and the second metallization layer 112.

Each of the first and second metallization layers 111, 112 may be composed of or may comprise one of the following materials: copper; a copper alloy; aluminum; an aluminum alloy; any other metal or alloy that remains in a solid state during operation of the power semiconductor module arrangement. The semiconductor substrate 10 may be a ceramic substrate, i.e., a substrate in which the dielectric insulating layer 11 is a ceramic (e.g., a thin ceramic layer). The ceramic may be composed of or include one of the following materials: alumina; aluminum nitride; zirconium oxide; silicon nitride; boron nitride; or any other dielectric ceramic. For example, the dielectric insulating layer 11 may be composed of or include one of the following materials: al (Al) ₂O₃AlN, SiC, BeO or Si₃N₄. For example, the substrate 10 may be, for example, a Direct Copper Bonded (DCB) substrate, a Direct Aluminum Bonded (DAB) substrate, or an Active Metal Braze (AMB)) A substrate. Further, the substrate 10 may be an Insulating Metal Substrate (IMS). The insulated metal substrate typically comprises a dielectric insulation layer 11 comprising a (filler) material such as epoxy or polyimide, for example. For example, the material of the dielectric insulating layer 11 may be filled with ceramic particles. Such particles may comprise, for example, Si₂O、Al₂O₃AlN or BrN, and may have a diameter between about 1 μm and about 50 μm. The substrate 10 may also be a conventional Printed Circuit Board (PCB) with a non-ceramic dielectric insulating layer 11. For example, the non-ceramic dielectric insulating layer 11 may be composed of or may include a cured resin.

The semiconductor substrate 10 is arranged in the housing 7. In the example shown in fig. 1, the semiconductor substrate 10 forms the bottom surface of the housing 7, while the housing 7 itself comprises exclusively sidewalls and a lid. However, this is merely an example. It is also possible that the housing 7 further comprises a bottom surface and that the semiconductor substrate 10 is arranged inside the housing 7. According to another example, the semiconductor substrate may be mounted on a base plate (not shown). In some power semiconductor module devices 100, more than one semiconductor substrate 10 is arranged on a single base plate. For example, the substrate may form the bottom surface of the housing 7.

One or more semiconductor bodies 20 may be arranged on the semiconductor substrate 10. Each of the semiconductor bodies 20 arranged on the semiconductor substrate 10 may comprise a diode, an IGBT (insulated gate bipolar transistor), a MOSFET (metal oxide semiconductor field effect transistor), a JFET (junction field effect transistor), a HEMT (high electron mobility transistor), or any other suitable semiconductor element.

One or more semiconductor bodies 20 may form a semiconductor device on the semiconductor substrate 10. In fig. 1, only two semiconductor bodies 20 are shown by way of example. The second metallization layer 112 of the semiconductor substrate 10 in fig. 1 is a continuous layer. In the example shown in fig. 1, the first metallization layer 111 is a structured layer. By "structured layer" is meant that the first metallization layer 111 is not a continuous layer but comprises recesses between different sections of the layer. Such a depression is schematically shown in fig. 1. The first metallization layer 111 in this example comprises three different sections. However, this is merely an example. Any other number of sections is possible. Different semiconductor bodies 20 may be mounted on the same section or on different sections of the first metallization layer 111. Different segments of the first metallization layer may not have any electrical connections or may be electrically connected to one or more other segments using, for example, bonding wires 3. For example, the electrical connection 3 may also comprise connection plates or conductor rails, to name a few. The one or more semiconductor bodies 20 may be electrically and mechanically connected to the semiconductor substrate 10 by means of a conductive connection layer 30. Such a conductive connection layer may be a solder layer, a conductive adhesive layer, or a sintered metal powder (e.g., sintered silver powder) layer.

According to other examples, the second metallization layer 112 may also be a structured layer. It is also possible to omit the second metallization layer 112. For example, the first metallization layer 111 may also be a continuous layer.

The power semiconductor module arrangement 100 shown in fig. 1 further comprises a terminal element 4. The terminal element 4 is electrically connected to the first metallization layer 111 and provides an electrical connection between the inside and the outside of the housing 7. The terminal element 4 may be electrically connected with a first end to the first metallization layer 111, while a second end 41 of the terminal element 4 protrudes from the housing 7. It is possible to make electrical contact with the terminal element 4 from the outside at the second end 41 of the terminal element 4. However, the terminal element 4 shown in fig. 1 is only an example. The terminal element 4 may be implemented in any other way and the terminal element 4 may be arranged anywhere within the housing 7. For example, one or more terminal elements 4 may be arranged close to a side wall of the housing 7 or adjacent to a side wall of the housing 7. The terminal elements 4 may also project through the side walls of the housing 7 instead of through the cover. Any other suitable implementation is possible.

The semiconductor bodies 20 may each include a chip pad metallization (not specifically shown), such as a source, drain, anode, cathode, or gate metallization. The chip pad metallization typically provides a contact surface for electrically connecting the semiconductor body 20. For example, the chip pad metallization may electrically contact the connection layer 30, the terminal elements 4 or the electrical connections 3. For example, the die pad metallization may be composed of, or may include, a metal such as aluminum, copper, gold, or silver. For example, the electrical connection portion 3 and the terminal element 4 may also be composed of or may include a metal such as copper, aluminum, gold, or silver.

The above-mentioned components of the power semiconductor module device 100 inside the housing 7 and other components may corrode when they come into contact with corrosive gases. For example, the corrosive gas may include sulfur or sulfur-containing compounds, e.g., hydrogen sulfide H₂And S. Corrosive gases in the surrounding area of the power semiconductor module device 100 may penetrate into the interior of the housing 7. The housing 7 for the power semiconductor module arrangement 100 is generally not fully protected against ingressing gases. Furthermore, for example, when the casing 7 is opened or before the casing 7 is closed, corrosive gas may enter the casing 7. Inside the housing 7, the corrosive gas may form an acid or a solution, for example, by combining with moisture present inside the housing 7. The corrosive gases or the resulting solutions may cause corrosion of some or all of the various components. During the corrosion process, the metal components of the parts may be oxidized to their corresponding sulfides. The formation of sulfides can change the electrical properties of the components or lead to the formation of new conductive connections or to short circuits within the power semiconductor module arrangement 100.

Furthermore, upon exposure to corrosive gases and further under the influence of an electric field and possibly moisture, mobile metal ions (e.g., Cu, Ag, etc.) of the components and structures of the power semiconductor module device 100 including the metal and anions (e.g., S) present in the corrosive gases ^2-) A dendrite structure may be formed. Dendrites are a characteristic dendritic crystal structure. Dendritic growth in the metal layer can have large consequences with respect to the material properties and is generally undesirable.

An example of a corrosive gas is hydrogen sulfide (H)₂S), carbonyl sulfide (OCS) or gaseous sulfur (S)₈). In some applications, the power semiconductor module assembly may be exposed to corrosive gases, such as Cl^-、SO_xOr NO_x. In general, it is also possible for sulfur to enter the interior of the housing 7 as a solid material or as a constituent of a liquid.

Components and structures that include one or more metals, such as copper (e.g., first metallization layer 111, electrical connections 3, terminal elements 4, connection layers 30, die pad metallization), silver (e.g., first metallization layer 111, electrical connections 3, terminal elements 4, connection layers 30, die pad metallization), or lead (e.g., connection layers 30 that include a lead-containing solder), may be particularly susceptible to corrosion. For example, other metals (e.g., aluminum) may have a thin oxide layer covering their surface area, which may provide at least some amount of protection against corrosive gases.

The conventional power semiconductor module arrangement 100 generally also comprises a potting compound 5. For example, the potting compound 5 may be comprised of or may include a silicone gel, or may be a rigid molding compound. The potting compound 5 can at least partially fill the interior of the housing 7, thereby covering the components and electrical connections arranged on the semiconductor substrate 10. The terminal element 4 may be partially embedded in the potting compound 5. However, at least its second end 41 is not covered by potting compound 5 and protrudes from potting compound 5 through housing 7 to the exterior of housing 7. The potting compound 5 is configured to protect components and electrical connections inside the power semiconductor module 100 (especially inside the housing 7) from certain environmental conditions and mechanical damage. The potting compound 5 also provides electrical isolation for the components inside the housing 7. However, corrosive gases are generally able to penetrate the potting compound 5. Therefore, the potting compound 5 is generally not capable of protecting the components and electrical connections from corrosive gases.

The potting compound 5 can form a protective layer in the vertical direction y of the semiconductor substrate 10. The vertical direction y is a direction substantially perpendicular to the top surface of the semiconductor substrate 10. The top surface of the semiconductor substrate 10 is the surface on which the semiconductor body 20 is mounted or can be mounted. The first protective layer 5 at least partially covers any components arranged on the top surface of the semiconductor substrate 10 and any exposed surfaces of the semiconductor substrate 10.

In order to better protect the metal parts of the power semiconductor module arrangement 100 from corrosive gases, the potting compound 5 may also comprise a filler 81, for example. In particular, the filler 81 may be mixed into the potting compound 5. However, the filler 81 may not be uniformly distributed within the potting compound 5. In contrast, the semiconductor device may include a first layer 800 formed of a mixture of the filler 81 and the potting compound 5 and a second layer 801 including only the potting compound 5 but no filler 81. The second layer 801 may be disposed above the first layer 800. That is, the first layer 800 may be arranged between the second layer 801 and the semiconductor substrate 10 on which the semiconductor body 20 is mounted.

This is illustrated in fig. 2. The packing 81 may be configured to chemically react with the corrosive gas, or particularly react with sulfur or sulfur-containing compounds of the corrosive gas. Corrosive gases may also be trapped, adsorbed or absorbed by the packing 81. By chemical reaction with the corrosive gas, the filler 81 prevents harmful substances from reaching (metal) parts inside the housing 7 and thereby protects the parts from corrosion. For example, the filler 81 may be a powder of the second material distributed throughout the first material of the potting compound 5. The second material may include any material that reacts with the corrosive gas and may, for example, form a metal sulfide when exposed to the corrosive gas. The filler 81 may be substantially uniformly distributed throughout the first layer 800. The first material of the potting compound 5 may comprise or consist of a non-reactive crosslinkable or non-crosslinkable polymer, such as a silicone gel or a silicone rubber. Other casting materials such as epoxy, for example, are also possible.

For example, the filler 81 may be an inorganic filler. For example, the inorganic filler may include an insoluble inorganic material, such as silica, fused silica, crystalline silica, precipitated silica, alumina, beryllium, boron nitride, aluminum nitride, silicon carbide, boron carbide, titanium carbide, magnesium oxide, zinc oxide, or glass fiber. For example, the filler 81 may be provided in the form of particles having a diameter between about 1 μm and 400 μm or between about 4 μm and 20 μm. All particles may have the same diameter. However, the particles of the filler 81 do not necessarily all have to have the same diameter. It is also possible to use fillers comprising particles of different sizes. For example, binary systems (e.g., particles having two different diameters) or ternary systems (particles having three different diameters) are also possible. In this way, the bulk density of the filler 81 can be increased. In the mixture comprising potting compound 5 and filler 81, i.e. in first layer 800, the amount of filler 81 may be, for example, between about 20 vol% and 90 vol%, or between about 60 vol% and 80 vol%. In general, the first layer 800 may include a relatively high amount of filler 81. The particles of the filler 81 may have a relatively high density ρ _fE.g. at about 0.9g/cm³And 5.0g/cm³In the meantime. On the other hand, potting compound 5 may have a density ρ that is lower than filler 81_fDensity of (p)_cc. According to one example, the density ρ of the potting compound 5_ccMay be at about 0.2g/cm³And 0.9g/cm³In the meantime. According to one example, if the density ρ of the filler 81 is_fIs 0.9g/cm³Then density p of casting compound 5_ccIs composed of<0.9g/cm³Or even<0.5g/cm³. For example, the aspect ratio of each of the individual particles of the filler 81 may be between 1 and 100.

If the inorganic filler 81 comprises a conductive material, such as a metallic material, the concentration of the inorganic filler 81 in the first layer 800 may be such that the first layer 800 as a whole remains electrically insulating.

The first layer 800 may have a first thickness d1 in the vertical direction y. The first layer 800 at least partially covers any features disposed on the top surface of the semiconductor substrate 10 and any exposed surfaces of the semiconductor substrate 10. For example, the first thickness d1 may be between 1mm and 10mm, or between 2mm and 6 mm.

The second layer 801 is arranged on top of the first layer 800. In this context, on top of the first layer 800 means that the second layer 801 is arranged adjacent to the first layer 800 in the vertical direction y, such that the first layer 800 is arranged between the second layer 801 and the semiconductor substrate 10. For example, the second layer 801 may include a casting material, such as a non-reactive soft cross-linked or non-cross-linked polymer. For example, the non-reactive polymer may include a silicone gel or a silicone rubber. Other casting materials such as epoxy are also possible. The material of the second layer 801 may be the same as the first material of the first layer 800. The second layer 801 may have a second thickness d2 in the perpendicular direction y. The second thickness d2 may be the same as the first thickness d1, or the second thickness d2 may be greater or less than the first thickness d 1. For example, the second thickness d2 may be between 1mm and 10mm, or between 2mm and 6 mm.

As shown in the example of fig. 2, only the bottom of the housing 7 of the power semiconductor module arrangement 100 may be filled with a first layer 800 comprising both the first material and the filler 81. The thickness d1 of the first layer 800 is significantly smaller than the height of the potting compound 5 without filler in the device shown in fig. 1, in which the main part of the housing 7 is filled with the potting compound 5. The relatively large thickness of the individual layers of potting compound 5 of the power semiconductor module arrangement of fig. 1 may cause a flexing of the power semiconductor module arrangement 100, in particular of the semiconductor substrate 10 and/or of the base plate (if applicable), in particular if the potting compound 5 comprises a so-called hard encapsulation. The hard encapsulant has a hardness greater than a certain threshold hardness. For example, the hardness of the material may be determined by a shore durometer and may be indicated by one of several shore durometer scales (e.g., shore a, shore D, etc.). The relatively thin first layer 800 of the power semiconductor module arrangement of fig. 2 generally causes only little to no flexing of the power semiconductor module arrangement 100.

This is exemplarily illustrated in fig. 4, fig. 4 schematically indicating forces that may occur on the surfaces of different elements of the semiconductor module arrangement. The corresponding forces occurring on the surfaces of the different elements of the semiconductor module arrangement comprising the potting compound 5 (see fig. 1) with the hard resin material, which in each case represents 100%, are shown as reference in fig. 4. When using a soft resin instead of a hard resin, the forces occurring can be significantly reduced. For example, when a soft resin is used instead of a hard resin, the force occurring on the surface of the second metallization layer 112(Cu, bottom) may be reduced by more than 30% to about 65%. When using a soft resin instead of a hard resin, the force that occurs on the surface of the IMS substrate (IMS) can be reduced by more than 40% to about 58%. When a soft resin is used instead of a hard resin, the force occurring on the surface of the first metallization layer 111(Cu, top) may be reduced by more than 30% to about 68%. When a soft resin is used instead of a hard resin, the force occurring on the surface of the solder layer 30 (solder) can be reduced by about 60% to about 40%. When a soft resin is used instead of a hard resin, the force occurring on the surface of the semiconductor body 20 (chip) can be reduced by more than 50% to about 47%. When a soft resin is used instead of a hard resin, the force occurring on the surface of the first layer 800 (the soft resin with the filler) may be reduced by more than 30% to about 63%.

It can be seen that by using a soft encapsulant material and forming a first layer 800 that includes both the soft encapsulant and filler 81 and a second layer 801 that includes only the soft encapsulant but no filler 81, stress within the semiconductor module can be reduced and overall system reliability can be enhanced. Furthermore, the mismatch of the coefficients of thermal expansion CTE between the different components of the semiconductor module can be reduced by adding fillers 81 to the potting compound 5 in the first layer 800. For example, the coefficient of thermal expansion CTE of the first layer 800₈₀₀Can be matched to the coefficient of thermal expansion CTE of the semiconductor substrate 10 and the at least one semiconductor body 20₁₀、CTE₂₀Similarly, such that (for example) the CTE₈₀₀＝CTE₁₀. + -. 5ppm/K and CTE₈₀₀＝CTE ₂₀5 ppm/K. In this way, undesirable bowing of the semiconductor module can be reduced. Undesirable bowing can generally occur when different forces occur at different interfaces within a semiconductor module. For example, the semiconductor substrate 10 and/or the base plate of the semiconductor module may be bent to some extent so thatThe semiconductor substrate 10 and/or the base plate is no longer flat but may have a concave or convex curvature in the vertical direction y. This may further cause undesirable tensions on connections formed in the semiconductor substrate, for example the electrically conductive connection layer 30 for mounting the semiconductor body 20 on the semiconductor substrate 10. Local thermal stresses can cause deterioration of the potting compound 5.

In an ideal semiconductor module, the force balance prevails. That is, F₁+F₂+F₃+…+F_iWhere F is the force and i is the number of the element in the semiconductor module. In addition, in an ideal semiconductor module, the moment balance prevails. That is, M₁+M₂+M₃+…+M_i＝M_extWhere M is the moment and I is the number of elements in the semiconductor module.

The strain continuity of adjacent layers within a semiconductor module may be calculated as

Or, more generally,

where F is the force, α is the CTE, E is the modulus, and d is the thickness of the layer in the perpendicular direction y. For example, the different layers of the semiconductor module can be the first metallization layer 111, the second metallization layer 112, the dielectric insulation layer 11, the conductive connection layer 30 or the potting compound 5.

The resulting bow of the semiconductor module can generally be adjusted by adjusting the amount of filler 81 in the first layer 801. For example, greater bowing may occur when the amount of filler 81 in the first layer 801 is reduced, and lesser bowing may occur when the amount of filler 81 in the first layer 801 is increased.

Fig. 2 shows an example of the power semiconductor module device 100 after the first layer 800 and the second layer 801 have been formed. A method for manufacturing the power semiconductor module device of fig. 2 will now be explained by fig. 3 including fig. 3A to 3D.

Fig. 3B shows the power semiconductor module device 100 before the first layer 800 and the second layer 801 are formed. The power semiconductor module device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 may correspond to the semiconductor substrate 10 already described above with respect to fig. 1 and 2. As described above, one or more semiconductor bodies 20 may be arranged on the semiconductor substrate 10. The power semiconductor module arrangement 100 may further comprise a terminal element 4, as already described above. The housing 7 of the power semiconductor module arrangement 100 substantially corresponds to the housing 7 already described above with respect to fig. 1 and 2. However, the cover may be added to the housing 7 at a later stage, for example, after the first layer 800 and the second layer 801 are formed. The housing 7 of the device shown in fig. 3B may also comprise a bottom. Conversely, the semiconductor substrate 10 may also be arranged on a base plate (not shown), so that the base plate forms the bottom of the housing 7. As schematically shown in fig. 3A, the inorganic filler 81 may be pre-mixed with the potting compound 5. For example, the particles of filler 81 may be uniformly distributed within potting compound 5. For example, the material of the potting compound 5 may be liquid or may be viscous.

The mixture comprising potting compound 5 and filler 81 may then be filled into a semiconductor module, as schematically shown in fig. 3B. Fig. 3C schematically shows the semiconductor module device 100 after the mixture is filled into the housing 7. It can be seen that at this point the filler 81 is still evenly distributed within the potting compound 5. However, due to the density ρ of the filler 81_fGreater than the density rho of the potting compound 5_ccThus, the filler 81 is deposited down onto the surface of the semiconductor substrate 10 and the semiconductor body 20 and any other components mounted on the semiconductor substrate 10. In this way, a dense first layer 800 is formed by the descending filler 81, as schematically shown in fig. 3D. As described above, the filler 81 may include particles. For example, the particles may have a generally rounded or oval shape. However, any other form of particles is also possible. After settling down, the particles of the filling 81 may be stacked on top of each other. However, spaces are left between the different particles of the filler 81Or a gap. Portions of the potting compound 5 fill these spaces or gaps. Thus, the first layer 800 is a relatively dense layer formed by allowing the filler 81 to settle down within the potting compound 5. The concentration of the filler within the first layer 800 is significantly higher than the concentration of the filler 81 in the pre-mixed mixture filled into the housing 7.

The remaining portion of the potting compound forms a second layer 801 disposed over the first layer 800. Since the filler 81 is lowered onto the semiconductor substrate 10, no filler 81 remains in the second layer 801. The thickness d1 of the first layer 800 and the thickness d2 of the second layer 801 depend on the amount of casting compound 5 and filler 81 used to form the pre-mixed mix (see fig. 3A).

The precipitation of the filler 81 may be accelerated by heating the semiconductor module device 10 during the precipitation step. By applying heat, the density of the potting compound 5 can be reduced, thereby liquefying the material of the potting compound (reducing the viscosity of the potting compound 5). Thus, the filler 81 can precipitate more quickly at higher temperatures than at lower temperatures. For example, the temperature during the precipitation step may be between 30 ℃ and 150 ℃.

The precipitation of the filler 81 may be performed in vacuum. For example, a vacuum of 1mbar to 200mbar may be created. In addition to or as an alternative to heating the semiconductor module arrangement, it is also possible to accelerate the precipitation of the filler 81 by reducing the vacuum during the precipitation step. The temperature and the degree of vacuum may depend on the material used for casting the compound 5.

Once the filler 81 is completely precipitated, a curing or hardening step (not specifically shown) may be performed. During curing or hardening of potting compound 5, potting compound 5 is crosslinked with inorganic filler 81. This significantly reduces the mobility of the inorganic filler 81. By filling substantially all of the remaining spaces and gaps between the particles of the inorganic filler 81 and by cross-linking the potting compound 5 with the inorganic filler, it becomes difficult, if not impossible, for any gas to diffuse through the first layer 800.

For example, curing or hardening the casting compound 5 may include heating the casting compound 5 and evaporating all or most of the liquid of the casting compound 5. For example, instead of or after curing the potting compound 5, the potting compound 5 may be cooled below its glass transition temperature. For example, potting compound 5 can be allowed to cool to room temperature, which is often well below the glass transition temperature of the material used as potting compound 5.

The particles of the inorganic filler 81 are generally stacked on each other in a random manner. Thus, the gas cannot diffuse in a straight line through the first layer 800, if there is any difference. In general, the gas cannot penetrate the inorganic filler 81, but only through the potting compound 5 surrounding the filler 81. Therefore, the gas must diffuse around the inorganic filler 81, which results in a relatively long diffusion path. This makes it more difficult for gas to diffuse through the first layer 800. In general, since the amount of the inorganic filler 81 in the first layer 800 is relatively high, there is little space for the gas to diffuse through the first layer 800. This makes it almost impossible for corrosive gases to diffuse through the first layer 800.

As can be seen from fig. 2, and as already described above, the concentration of the filling 81 in the first layer 800 adjacent to the semiconductor substrate 10 and the semiconductor body 20 mounted thereon is very high. On the other hand, the second layer 801 does not include any filler 81. In this way, the modulus of elasticity of the filling material can be increased compared to the device of fig. 1, for example, and the CTE of the first layer 800 can be reduced compared to a layer comprising only potting compound 5. In this way, the CTE of the first layer 800 can be adjusted to the CTE of the semiconductor substrate 10 and the semiconductor body 20. The CTE can be adjusted by adjusting the concentration of filler 81 in the potting compound 5. The resulting semiconductor module device 100 is stable at high temperatures (e.g., 200 ℃ or higher).