阅读说明：本技术 基于电容补偿结构的宽带混合式ef类功率放大器及设计方法 (Broadband hybrid EF (class-EF) power amplifier based on capacitance compensation structure and design method ) 是由 刘国华 王维荣 张志维 赵众 简叶龙 程知群 黄谢镔 于 2020-07-02 设计创作，主要内容包括：本发明公开了基于电容补偿结构的宽带混合式EF类功率放大器及设计方法,包括输入匹配网络、晶体管、谐波控制网络、漏极宽带补偿电路以及基波匹配网络,其中,输入匹配网络的输入端接入功率信号,其输出端与晶体管的栅极相连接；晶体管漏极与源极之间并接漏极宽带补偿电路,漏极宽带补偿电路用于根据功率信号补偿所需的输出电容；晶体管漏极与谐波控制网络的输入端相连接,谐波控制网络的输出端与基波匹配网络的输入端相连接,基波匹配网络的输出端作为功率输出端,匹配到所需要的最终阻抗值。本发明提出用于漏源输出电容的新型宽带补偿电路结构,能够根据输入功率信号获得所需的晶体管输出电容,改善了混合EF类功率放大器的工作频率。(The invention discloses a broadband hybrid EF (electric-field) power amplifier based on a capacitance compensation structure and a design method thereof, wherein the broadband hybrid EF power amplifier comprises an input matching network, a transistor, a harmonic control network, a drain broadband compensation circuit and a fundamental wave matching network, wherein the input end of the input matching network is accessed with a power signal, and the output end of the input matching network is connected with a grid electrode of the transistor; a drain broadband compensation circuit is connected between the drain and the source of the transistor in parallel, and is used for compensating the required output capacitance according to the power signal; the drain electrode of the transistor is connected with the input end of the harmonic control network, the output end of the harmonic control network is connected with the input end of the fundamental wave matching network, and the output end of the fundamental wave matching network is used as a power output end and is matched with a required final impedance value. The invention provides a novel broadband compensation circuit structure for a drain-source output capacitor, which can obtain the required transistor output capacitor according to an input power signal and improve the working frequency of a hybrid EF class power amplifier.)

1. The broadband hybrid EF-class power amplifier based on the capacitance compensation structure is characterized by comprising an input matching network, a transistor, a harmonic control network, a drain broadband compensation circuit and a fundamental wave matching network, wherein the input end of the input matching network is connected with a power signal, and the output end of the input matching network is connected with the grid electrode of the transistor; a drain broadband compensation circuit is connected between the drain and the source of the transistor in parallel, and is used for compensating the required output capacitance according to the power signal; the drain electrode of the transistor is connected with the input end of the harmonic control network, the output end of the harmonic control network is connected with the input end of the fundamental wave matching network, and the output end of the fundamental wave matching network is used as a power output end and is matched with a required final impedance value; the drain broadband compensation circuit comprises two pairs of coupling lines, a first fan-shaped microstrip line Curve1, a second fan-shaped microstrip line Curve2, an eleventh microstrip line TL11 and a twelfth microstrip line TL12, wherein the first fan-shaped microstrip line Curve1 and the second fan-shaped microstrip line Curve2 are microstrip lines with quarter of arc length; the first pair of coupling lines comprises a first coupling line and a second coupling line, the second pair of coupling lines comprises a third coupling line and a fourth coupling line, one end of the first coupling line is connected with one end of the second coupling line, the other end of the first coupling line is connected with one end of an eleventh microstrip line TL11, the other end of an eleventh microstrip line TL11 is connected with one end of a first fan-shaped microstrip line Curve1, the other end of the first fan-shaped microstrip line Curve1 is connected with one end of the third coupling line, the other end of the third coupling line is connected with one end of a fourth coupling line, the other end of the fourth coupling line is connected with one end of a second fan-shaped microstrip line Curve2, the other end of the second fan-shaped microstrip line Curve2 is connected with one end of a twelfth microstrip line TL12, and the other end of the twelfth microstrip line 12 is connected with the other end of the second coupling line;

The harmonic control network is connected with the drain broadband compensation circuit and at least comprises a first microstrip line TL1, a second microstrip line TL2 and a third microstrip line TL3, wherein one end of the first microstrip line TL1 is connected with the drain of the transistor, the other end of the first microstrip line TL1 is connected with one end of a second microstrip line TL2 and one end of a third microstrip line TL3, the other end of the second microstrip line TL2 is grounded, and the other end of the third microstrip line TL3 is connected with the drain broadband compensation circuit in parallel;

the harmonic control network considers the impedance up to the third harmonic in harmonic control, and TL1 is tuned to obtain TL1+ TL2 as lambda/4; the electrical length of the drain broadband Compensation Circuit (CCS) at the center frequency f0 is λ/12; then, TL2 was tuned to give TL1+ TL3+ CCS ═ λ/6.

2. The broadband hybrid EF-class power amplifier based on the capacitance compensation structure as claimed in claim 1, further comprising a gate broadband compensation circuit, wherein the gate broadband compensation circuit is connected in parallel with the gate of the transistor and adopts the same circuit structure as the drain broadband compensation circuit.

3. The broadband hybrid EF-class power amplifier based on the capacitance compensation structure as claimed in claim 1 or 2, wherein the transistor is a Cree GaN HEMT CGH40010F transistor.

4. The broadband hybrid EF-class power amplifier based on the capacitance compensation structure as claimed in claim 1 or 2, wherein a gate bias circuit is arranged between the input matching circuit and the transistor, and the bias voltage of the gate bias circuit is-2.7V.

5. The broadband hybrid EF-class power amplifier based on the capacitance compensation structure as claimed in claim 1 or 2, wherein a bias circuit is arranged at the drain of the transistor, and the bias voltage of the bias circuit is 28V.

6. The design method of the broadband hybrid EF-class power amplifier based on the capacitance compensation structure is characterized in that the power amplifier is realized by adopting the following design steps:

step S1: designing a standard EF class power amplifier;

step S2, designing a fundamental wave matching network and obtaining an optimal fundamental wave matching circuit by adjusting fundamental wave impedance;

step S3: calculating the compensated redundant capacitance required by the EF-type power amplifier to reach the target parameter according to the target parameter, calculating the range of inductive reactance value required by the corresponding frequency band, and then obtaining the microstrip line characteristic impedance and the coupling coefficient required for compensating the redundant capacitance according to the odd mode equivalent model so as to design a corresponding drain electrode broadband compensation circuit;

the drain broadband compensation circuit is connected in parallel with the drain of the transistor and comprises two pairs of coupling lines, a first fan-shaped microstrip line Curve1, a second fan-shaped microstrip line Curve2, an eleventh microstrip line TL11 and a twelfth microstrip line TL12, wherein the first fan-shaped microstrip line Curve1 and the second fan-shaped microstrip line Curve2 are microstrip lines with quarter arc lengths; the first pair of coupling lines comprises a first coupling line and a second coupling line, the second pair of coupling lines comprises a third coupling line and a fourth coupling line, one end of the first coupling line is connected with one end of the second coupling line, the other end of the first coupling line is connected with one end of an eleventh microstrip line TL11, the other end of an eleventh microstrip line TL11 is connected with one end of a first fan-shaped microstrip line Curve1, the other end of the first fan-shaped microstrip line Curve1 is connected with one end of the third coupling line, the other end of the third coupling line is connected with one end of a fourth coupling line, the other end of the fourth coupling line is connected with one end of a second fan-shaped microstrip line Curve2, the other end of the second fan-shaped microstrip line Curve2 is connected with one end of a twelfth microstrip line TL12, and the other end of the twelfth microstrip line 12 is connected with the other end of the second coupling line;

Step S4: designing a harmonic control circuit, wherein a harmonic control network is connected with the drain broadband compensation circuit and at least comprises a first microstrip line TL1, a second microstrip line TL2 and a third microstrip line TL3, wherein one end of the first microstrip line TL1 is connected with the drain of the transistor, the other end of the first microstrip line TL1 is connected with one end of the second microstrip line TL2 and one end of the third microstrip line TL3, the other end of the second microstrip line TL2 is grounded, and the other end of the third microstrip line TL3 is connected with the drain broadband compensation circuit in parallel;

for harmonic control, tuning TL1 yields TL1+ TL2 ═ λ/4; the electrical length of the drain broadband Compensation Circuit (CCS) at center frequency f0 is about λ/12; TL2 was then applied to obtain TL1+ TL3+ CCS ═ λ/6.

7. The design method of the broadband hybrid EF-class power amplifier based on the capacitance compensation structure as claimed in claim 6, further comprising the steps of:

step S5: the grid electrode is connected with a broadband compensation circuit with the same structure in parallel, and the whole circuit is adjusted and optimized, so that the optimal output power and efficiency can be obtained in a target frequency band.

8. The design method of the broadband hybrid EF-class power amplifier based on the capacitance compensation structure as claimed in claim 6 or 7,

In step S1, a standard EF-type power amplifier is designed by the load pull technique.

9. The design method of the broadband hybrid EF-class power amplifier based on the capacitance compensation structure as claimed in claim 6 or 7,

in step S2, designing a fundamental wave matching network by adopting a matching method of a Chebyshev filter; and then, the fundamental wave impedance is adjusted on the Smith chart according to the target frequency band to obtain the optimal fundamental wave matching circuit.

10. The design method of the broadband hybrid EF-class power amplifier based on the capacitance compensation structure as claimed in claim 6 or 7,

a transistor package model is embedded into the output matching circuit to reduce parasitic parameter effects of the transistor package.

Technical Field

The invention relates to the technical field of radio frequency communication, in particular to a broadband hybrid EF (electric-field) power amplifier based on a capacitance compensation structure and a design method thereof.

Background

With the rapid development of modern mobile communication technology, especially the development of fifth generation mobile communication technology, a power amplifier with high efficiency, wide band and good linearity has become a hot topic. In recent years, many new power amplifiers have been reported in some papers, such as class E, class J, class F and class EF. They are all high efficiency power amplifiers. Class E power amplifiers are switching type power amplifiers, ideally with a 100% drain efficiency, but with higher harmonic drain voltages due to the switching characteristics of the transistors. By controlling the second harmonic impedance with the output capacitance, class J power amplifiers can achieve 78.5% drain efficiency and the PA behaves as an ideal class B PA over a specific frequency range. Class F power amplifiers were developed from overdriven class B power amplifiers. By applying the waveform technique, the output drain voltage and current waveforms of the transistor do not overlap in the time domain, thereby achieving 100% efficiency. Of these high efficiency power amplifiers, the hybrid EF-class power amplifier is a new high efficiency hybrid power amplifier proposed by a.grebennikov in 2008, and ideally can achieve 100% efficiency. A hybrid class EF power amplifier has not only soft switching of a class E power amplifier, but also a low peak switching voltage similar to a class F power amplifier. FIG. 1 is a schematic diagram of a conventional class EF power amplifier, for a given power amplifier Output power, DC power supply voltage and maximum working frequency f of power amplifier_MAXOutput capacitor C of receiving transistor_outSize limitation, i.e. at high frequencies, C_outTypically larger than the capacitance C required for a hybrid EF class power amplifier. So that a high-power transistor with a high output power is often accompanied by a high output capacitance C_outTherefore, the topological structure of the hybrid EF class power amplifier is not suitable for high-frequency-band high-power use, which severely limits the application of the hybrid EF class power amplifier. Recently, there have been many reports on methods of increasing the operating frequency, and one of them introduces two new variants of class EF power amplifiers, namely, class Three Harmonic Peak (THP) and class Five Harmonic Peak (FHP) EF power amplifiers, which use a simple transmission line loading network to achieve a higher f_MAX. One class EF PA is designed by reducing the duty cycle, which turns on the transistor in a shorter time. Yet another inverter EF2 has a drain efficiency of 91% and utilizes a series-tuned resonant network. However, the above method can only increase the operating frequency within a narrow frequency band.

Therefore, it is necessary to provide a solution to the above-mentioned drawbacks in the prior art.

Disclosure of Invention

In order to overcome the defects of the prior art, it is necessary to provide a broadband hybrid EF power amplifier based on a capacitance compensation structure and a design method thereof, and to overcome the limitation that the working frequency of the conventional hybrid EF power amplifier is limited by the drain-source output capacitance, a novel broadband compensation circuit structure is designed to realize the drain-source output capacitance, and a required transistor output capacitance can be obtained according to an input power signal, so that the working frequency of the hybrid EF power amplifier is improved, and high efficiency is maintained in a broadband.

In order to solve the technical problems in the prior art, the technical scheme of the invention is as follows:

the broadband hybrid EF-class power amplifier based on the capacitance compensation structure comprises an input matching network, a transistor, a harmonic control network, a drain broadband compensation circuit and a fundamental wave matching network, wherein the input end of the input matching network is connected with a power signal, and the output end of the input matching network is connected with a grid electrode of the transistor; a drain broadband compensation circuit is connected between the drain and the source of the transistor in parallel, and is used for compensating the required output capacitance according to the power signal; the drain electrode of the transistor is connected with the input end of the harmonic control network, the output end of the harmonic control network is connected with the input end of the fundamental wave matching network, and the output end of the fundamental wave matching network is used as a power output end and is matched with a required final impedance value; the drain broadband compensation circuit comprises two pairs of coupling lines, a first fan-shaped microstrip line Curve1, a second fan-shaped microstrip line Curve2, an eleventh microstrip line TL11 and a twelfth microstrip line TL12, wherein the first fan-shaped microstrip line Curve1 and the second fan-shaped microstrip line Curve2 are microstrip lines with quarter of arc length; the first pair of coupling lines comprises a first coupling line and a second coupling line, the second pair of coupling lines comprises a third coupling line and a fourth coupling line, one end of the first coupling line is connected with one end of the second coupling line, the other end of the first coupling line is connected with one end of an eleventh microstrip line TL11, the other end of an eleventh microstrip line TL11 is connected with one end of a first fan-shaped microstrip line Curve1, the other end of the first fan-shaped microstrip line Curve1 is connected with one end of the third coupling line, the other end of the third coupling line is connected with one end of a fourth coupling line, the other end of the fourth coupling line is connected with one end of a second fan-shaped microstrip line Curve2, the other end of the second fan-shaped microstrip line Curve2 is connected with one end of a twelfth microstrip line TL12, and the other end of the twelfth microstrip line 12 is connected with the other end of the second coupling line.

As a further improvement, the harmonic control network and the drain broadband compensation circuit include that the harmonic control network at least includes a first microstrip line TL1, a second microstrip line TL2 and a third microstrip line TL3, wherein one end of the first microstrip line TL1 is connected to the drain of the transistor, the other end of the first microstrip line TL1 is connected to one end of the second microstrip line TL2 and one end of the third microstrip line TL3, the other end of the second microstrip line TL2 is grounded, and the other end of the third microstrip line TL3 is connected in parallel to the drain broadband compensation circuit.

As a further improvement, the harmonic control network takes into account the impedance up to the third harmonic in the harmonic control, and the TL1 is tuned to obtain TL1+ TL2 ═ λ/4; the electrical length of the drain broadband Compensation Circuit (CCS) at the center frequency f0 is λ/12; then, TL2 was tuned to give TL1+ TL3+ CCS ═ λ/6.

As a further improvement scheme, the transistor further comprises a grid electrode broadband compensation circuit, wherein the grid electrode broadband compensation circuit is connected with the grid electrode of the transistor in parallel, and the circuit structure of the transistor is the same as that of the drain electrode broadband compensation circuit. The gate broadband compensation circuit is used to suppress harmonics, thereby further improving output power and efficiency.

As a further improvement, the transistor is a GaN HEMT CGH40010F transistor of Cree company.

As a further improvement, a grid bias circuit is arranged between the input matching circuit and the transistor, and the bias voltage of the grid bias circuit is-2.7V.

As a further improvement, a bias circuit is arranged at the drain electrode of the transistor, and the bias voltage of the bias circuit is 28V.

The invention also discloses a design method of the broadband hybrid EF-class power amplifier based on the capacitance compensation structure, and the power amplifier is realized by adopting the following design steps:

step S1: designing a standard EF class power amplifier;

step S2, designing a fundamental wave matching network and obtaining an optimal fundamental wave matching circuit by adjusting fundamental wave impedance;

step S3: calculating the compensated redundant capacitance required by the EF-type power amplifier to reach the target parameter according to the target parameter, calculating the range of inductive reactance value required by the corresponding frequency band, and then obtaining the microstrip line characteristic impedance and the coupling coefficient required for compensating the redundant capacitance according to the odd mode equivalent model so as to design a corresponding drain electrode broadband compensation circuit;

the drain broadband compensation circuit is connected in parallel with the drain of the transistor and comprises two pairs of coupling lines, a first fan-shaped microstrip line Curve1, a second fan-shaped microstrip line Curve2, an eleventh microstrip line TL11 and a twelfth microstrip line TL12, wherein the first fan-shaped microstrip line Curve1 and the second fan-shaped microstrip line Curve2 are microstrip lines with quarter arc lengths; the first pair of coupling lines comprises a first coupling line and a second coupling line, the second pair of coupling lines comprises a third coupling line and a fourth coupling line, one end of the first coupling line is connected with one end of the second coupling line, the other end of the first coupling line is connected with one end of an eleventh microstrip line TL11, the other end of an eleventh microstrip line TL11 is connected with one end of a first fan-shaped microstrip line Curve1, the other end of the first fan-shaped microstrip line Curve1 is connected with one end of the third coupling line, the other end of the third coupling line is connected with one end of a fourth coupling line, the other end of the fourth coupling line is connected with one end of a second fan-shaped microstrip line Curve2, the other end of the second fan-shaped microstrip line Curve2 is connected with one end of a twelfth microstrip line TL12, and the other end of the twelfth microstrip line 12 is connected with the other end of the second coupling line;

Step S4: designing a harmonic control circuit, wherein a harmonic control network is connected with the drain broadband compensation circuit and at least comprises a first microstrip line TL1, a second microstrip line TL2 and a third microstrip line TL3, wherein one end of the first microstrip line TL1 is connected with the drain of the transistor, the other end of the first microstrip line TL1 is connected with one end of the second microstrip line TL2 and one end of the third microstrip line TL3, the other end of the second microstrip line TL2 is grounded, and the other end of the third microstrip line TL3 is connected with the drain broadband compensation circuit in parallel;

for harmonic control, tuning TL1 yields TL1+ TL2 ═ λ/4; the electrical length of the drain bandwidth Compensation Circuit (CCS) at center frequency f0 is about λ/12; TL2 was then applied to obtain TL1+ TL3+ CCS ═ λ/6.

As a further improvement, the method also comprises the following steps:

step S5: the grid electrode is connected with a broadband compensation circuit with the same structure in parallel, and the whole circuit is adjusted and optimized, so that the optimal output power and efficiency can be obtained in a target frequency band.

As a further improvement, it is proposed that,

in step S1, a standard EF-type power amplifier is designed by the load pull technique.

As a further improvement, in step S2, a fundamental matching network is designed by using a chebyshev filter matching method; and then, the fundamental wave impedance is adjusted on the Smith chart according to the target frequency band to obtain the optimal fundamental wave matching circuit.

As a further improvement, a transistor package model is embedded in the output matching circuit to reduce the parasitic parameter effect of the transistor package.

Compared with the prior art, the invention provides a novel broadband compensation circuit structure for the drain-source output capacitor aiming at the problem that the working frequency of the traditional mixed EF-class power amplifier is limited by the drain-source output capacitor, so that the required transistor output capacitor is obtained, the working frequency of the mixed EF-class power amplifier is improved, and the high efficiency is kept on a broadband. Meanwhile, the grid compensation circuit is used for suppressing harmonic waves, so that the output power and the efficiency are further improved.

Drawings

Fig. 1 is a schematic diagram of a conventional EF-type power amplifier according to the present invention.

Fig. 2 is a block diagram of a wideband hybrid EF-class power amplifier based on a capacitance compensation structure according to the present invention.

Fig. 3 is a schematic diagram of the structure of the broadband compensation circuit of the present invention.

Fig. 4 is an equivalent circuit diagram of the wideband compensation circuit in the odd-even mode.

Fig. 5 is a schematic diagram of the structure of the harmonic control network in the present invention.

Fig. 6 is a simulation result diagram of the output power and the drain efficiency of the broadband hybrid EF-type power amplifier based on the capacitance compensation structure according to the present invention.

Fig. 7 is a flow chart of a design method of a broadband hybrid EF-type power amplifier based on a capacitance compensation structure according to the present invention.

The following specific embodiments will further illustrate the invention in conjunction with the above-described figures.

Detailed Description

The technical solution provided by the present invention will be further explained with reference to the accompanying drawings.

In view of the defects of the prior art, the applicant has conducted intensive research on the structure of the conventional hybrid EF-type power amplifier in the prior art, and found that the operating frequency of the conventional hybrid EF-type power amplifier in the prior art is limited by the drain-source output capacitance. And thus cannot maintain high efficiency over a wide frequency band.

In order to overcome the defects of the prior art, the broadband hybrid EF power amplifier based on the capacitance compensation structure provided by the application provides a novel broadband compensation circuit structure for the drain-source output capacitance, so that the required transistor output capacitance is obtained, the working frequency of the hybrid EF power amplifier is improved, and the high efficiency is kept on a broadband. Meanwhile, the grid compensation circuit is used for suppressing harmonic waves, so that the output power and the efficiency are further improved.

Referring to fig. 2, the broadband hybrid EF-class power amplifier based on the capacitive compensation structure of the present invention is shown, which comprises an input matching network, a gate broadband compensation circuit, a transistor, an output harmonic control network, a drain broadband compensation circuit, a fundamental matching network, wherein the input end of the input matching network is used as a power input end, the output end of the input matching network is connected with the grid electrode of the transistor, the grid broadband compensation circuit is connected with the grid electrode of the transistor in parallel, for suppressing harmonics and thereby increasing output power and efficiency, a transistor drain connected in parallel with a drain wide band compensation circuit for compensating capacitance, therefore, the working bandwidth and efficiency of the EF class are changed, the drain electrode of the transistor is connected with the input end of the output harmonic control network, the output end of the output harmonic control network is connected with the input end of the fundamental wave matching network, and the output end of the fundamental wave matching network is used as a power output end and matched with a required final impedance value.

Referring to fig. 3, which shows a schematic structural diagram of the broadband compensation circuit of the present invention, the broadband compensation circuit includes two pairs of coupling lines, two microstrip lines with a quarter arc length and two conventional microstrip lines, the first pair of coupling lines is connected to one end of an eleventh microstrip line TL11, the other end of the eleventh microstrip line TL11 is connected to one end of a first fan-shaped microstrip line Curve1, the other end of the first fan-shaped microstrip line is connected to the second pair of coupling lines, the second pair of coupling lines is connected to one end of a second fan-shaped microstrip line Curve2, the other end of the second fan-shaped microstrip line Curve2 is connected to one end of a twelfth microstrip line TL12, and the other end of the twelfth microstrip line TL12 is connected to the.

Since the broadband compensation circuit structure shown in fig. 3 is symmetrical, the present invention adopts an analysis method of an odd-even mode. The equivalent circuit of the parity mode is shown in fig. 4. Fig. 4(a), (b) are respectively odd mode and even mode equivalent circuits. For the sake of simplicity of calculation, it is assumed that θ 1 — θ 2 — θ 3 is 30 °. The relationship between the characteristic impedance and the characteristic impedance of the parity mode is as follows:

where Z0e, Z0o are the characteristic impedances for the odd and even modes, respectively. Z0 is the characteristic impedance of the microstrip line. C is the coupling coefficient. Thus, the odd mode input impedance can be derived as:

The even mode input impedance is shown as:

the relation between the input impedance of the odd-even mode, the characteristic impedance of the microstrip line and the coupling coefficient can be obtained according to the formula. And then, according to the redundant capacitance value required to be compensated when the circuit is designed, obtaining the inductive reactance range of the corresponding frequency band. And then, reversely deducing the required characteristic impedance and coupling coefficient of the microstrip line according to the formula. Finally, a corresponding broadband compensation circuit is designed.

Referring to fig. 5, a schematic structural diagram of the harmonic control network according to the present invention is shown, and the harmonic control network includes a harmonic control network including a first microstrip line TL1, a second microstrip line TL2, a third microstrip line TL3, and a drain broadband Compensation Circuit (CCS). One end of the first microstrip line TL1 is connected with the drain of the transistor, the other end of the first microstrip line TL1 is connected with the second microstrip line TL2 in parallel and is connected with one end of the third microstrip line TL3, the other end of the second microstrip line TL2 is grounded, and the other end of the third microstrip line TL3 is connected with the drain broadband Compensation Circuit (CCS) in parallel. For harmonic control, the present invention considers impedances up to the third harmonic, tuning TL1 to obtain TL1+ TL2 ═ λ/4. The electrical length of the drain broadband Compensation Circuit (CCS) at the center frequency f0 is approximately λ/12. TL2 was then applied to obtain TL1+ TL3+ CCS ═ λ/6. At point D, ZD is zero for the second harmonic and infinite for the third harmonic. Therefore, the second harmonic impedance is converted to 0 and the third harmonic impedance is converted to infinity. Meanwhile, the transistor packaging model is embedded into the output matching circuit so as to reduce the influence of parasitic parameters of transistor packaging and improve the precision of the output matching circuit.

In a preferred embodiment, the power amplifier is implemented using Cree's GaN HEMT CGH40010F transistor.

In a preferred embodiment, a gate bias circuit is provided between the input matching circuit and the transistor, with a bias voltage of-2.7V.

In a preferred embodiment, a bias circuit is provided at the drain of the transistor, with a bias voltage of 28V.

Referring to fig. 7, a flow chart of the method for designing the broadband hybrid EF-type power amplifier based on the capacitance compensation structure according to the present invention is shown, and the method can be implemented by the following design steps:

step S1: designing a standard EF power amplifier through technologies such as load traction and the like;

step S2: designing a fundamental wave matching network by adopting a matching method of a Chebyshev filter; then, adjusting the fundamental wave impedance on the Smith chart according to the target frequency band to obtain an optimal fundamental wave matching circuit;

step S3: calculating the compensation redundant capacitance required by the EF-class power amplifier to reach the target parameters according to the target parameters such as the applied bias voltage, calculating the range of inductive reactance values required by the corresponding frequency band, and then inputting impedance according to an odd mode

Input impedance of even number mode

And finally, simulating the imaginary part of the Zin of the designed broadband compensation circuit structure through ADS to verify that the designed structure inductance value is in the required range.

Step S4: the harmonic control circuit is designed and for harmonic control, TL1 is tuned to obtain TL1+ TL2 ═ λ/4. The electrical length of the drain broadband Compensation Circuit (CCS) at the center frequency f0 is approximately λ/12. TL2 was then applied to obtain TL1+ TL3+ CCS ═ λ/6. At point D, ZD is zero for the second harmonic and infinity for the third harmonic; meanwhile, the transistor packaging model is embedded into the output matching circuit so as to reduce the influence of parasitic parameters of transistor packaging and improve the precision of the output matching circuit.

Step S5: the grid electrode is connected with the broadband compensation circuit with the same structure in parallel, the working bandwidth and efficiency are further improved through adjustment and optimization, and the whole circuit is adjusted and optimized, so that the optimal output power and efficiency are obtained in a target frequency band.

Referring to fig. 6, which is a simulation result diagram of the output power and efficiency of the broadband hybrid EF-type power amplifier based on the capacitance compensation structure, the designed power amplifier has the output power within the range of 40.4-41.3dBm and the drain efficiency within the range of 67-72% within the frequency band of 1.6-2.6GHz, and shows good performance indexes.

The above description of the embodiments is only intended to facilitate the understanding of the method of the invention and its core idea. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.