阅读说明：本技术 多电压芯片 (Multi-voltage chip ) 是由 蔡文浩 谢志明 于 2021-02-25 设计创作，主要内容包括：本发明提供了一种多电压芯片,包括：稳压电路、高压域控制器、低压域控制器以及数字逻辑电路。稳压电路接收回馈信号、稳压启动信号及参考电压,以反应于稳压启动信号、回馈信号及参考电压将系统高电压转换为稳压电压。高压域控制器接收电源信号及系统高电压,以提供参考电压及稳压启动信号。低压域控制器耦接高压域控制器,且接收稳压电压,以反应于稳压启动信号提供系统启动信号。数字逻辑电路耦接稳压电路以接收稳压电压且提供回馈信号,并且耦接低压域控制器以反应于系统启动信号而运作。(The present invention provides a multi-voltage chip, including: voltage stabilizing circuit, high voltage domain controller, low voltage domain controller and digital logic circuit. The voltage stabilizing circuit receives the feedback signal, the voltage stabilizing starting signal and the reference voltage, and converts the high voltage of the system into the voltage stabilizing voltage in response to the voltage stabilizing starting signal, the feedback signal and the reference voltage. The high voltage domain controller receives the power signal and the system high voltage to provide a reference voltage and a voltage stabilization starting signal. The low voltage domain controller is coupled with the high voltage domain controller and receives the stabilized voltage to provide a system starting signal in response to the stabilized starting signal. The digital logic circuit is coupled to the voltage stabilizing circuit to receive the stabilized voltage and provide a feedback signal, and is coupled to the low-voltage domain controller to operate in response to the system start signal.)

1. A multi-voltage chip, comprising:

the voltage stabilizing circuit receives a feedback signal, a voltage stabilizing starting signal and a reference voltage, and converts a system high voltage into a voltage stabilizing voltage in response to the voltage stabilizing starting signal, the feedback signal and the reference voltage;

a high voltage domain controller for receiving a power signal, a low voltage feedback signal and the system high voltage to provide the feedback signal, the reference voltage and the voltage stabilization starting signal;

a low voltage domain controller coupled to the high voltage domain controller and receiving the regulated voltage to provide a system start signal in response to the regulated start signal; and

a digital logic circuit coupled to the voltage regulator circuit to receive the regulated voltage and provide the low voltage feedback signal, and coupled to the low voltage domain controller to operate in response to the system enable signal.

2. The multi-voltage chip of claim 1, wherein the high voltage domain controller comprises:

a first level detector for receiving the system high voltage, detecting a voltage level of the system high voltage, and providing a high voltage enable signal in response to the system high voltage rising to a high voltage reset level;

a second level detector for receiving the system high voltage and detecting a voltage level of the system high voltage, wherein the second level detector enables a control enable signal in response to the high voltage enable signal and disables the control enable signal in response to the system high voltage rising to a high voltage ready level;

a high voltage controller receiving the low voltage feedback signal, the system high voltage and the control enable signal, providing a bandgap control signal in response to enabling of the power signal and the control enable signal, providing a first clock control signal and the voltage stabilization start signal in response to disabling of the control enable signal, and providing the feedback signal in response to the low voltage feedback signal;

a bandgap circuit receiving the system high voltage, the high voltage enable signal and the bandgap control signal and providing the reference voltage in response to the high voltage enable signal and the bandgap control signal; and

a first oscillator, receiving the system high voltage, the high voltage enable signal and the first clock control signal, and providing a first clock signal in response to the high voltage enable signal and the first clock control signal.

3. The multi-voltage chip of claim 2, wherein the first clock control signal is enabled in response to disabling of the control enable signal, and the first clock control signal is disabled after an initial clock time has elapsed.

4. The multi-voltage chip of claim 3, wherein the initial clock time is greater than a voltage rise time required for the regulated voltage to rise from a ground voltage to a target voltage.

5. The multi-voltage chip of claim 2, wherein the high voltage ready level is higher than the high voltage reset level.

6. The multi-voltage chip of claim 2, wherein the low-voltage domain controller comprises:

a third level detector receiving the regulated voltage and the regulated enable signal, detecting the regulated voltage in response to the regulated enable signal, and enabling a low voltage control signal in response to the regulated voltage rising to a regulated ready level;

a low voltage controller receiving the regulated voltage, the low voltage control signal and the first clock control signal to sequentially enable a second clock control signal and the system start signal in response to enabling of the low voltage control signal and disabling of the first clock control signal; and

and the second oscillator receives the regulated voltage, the regulated starting signal and the second clock pulse control signal to provide a second clock pulse signal in response to the second clock pulse control signal.

7. The multi-voltage chip of claim 6, wherein the enable time point of the second clock control signal is aligned with the disable time point of the first clock control signal, and the system enable signal is enabled after an enable time has elapsed after the second clock control signal is enabled.

8. The multi-voltage chip of claim 7, wherein the start-up time is greater than a time required for the second oscillator to stabilize oscillation.

9. The multi-voltage chip of claim 6, wherein the first clock signal is limited to be used in the high-voltage domain controller, and the second clock signal is used in a global domain of the multi-voltage chip.

10. The multi-voltage chip of claim 6, wherein the second clock signal has a higher frequency than the first clock signal.

11. The multi-voltage chip of claim 1, further comprising a plurality of power circuits for receiving the system high voltage, the reference voltage and the feedback signal to provide a plurality of operating voltages, respectively.

Technical Field

The present invention relates to a chip, and more particularly, to a multi-voltage chip.

Background

Technology is integrated into each layer of our lives, and a common interconnection and media-driven life style is brought, so that a circuit system comprises various complex electronic element combinations, such as high-performance micro-controllers, memories, interfaces, driver integrated circuits and other consumer electronic elements. Power supply designs tend to be complicated as each component may require various low voltage power supply rails with a wide range of power requirements, and thus multi-voltage integrated circuits are a trend. However, in the conventional multi-voltage integrated circuit, the power-on timing may not be correct, which may not only cause power consumption but also cause the integrated circuit to fail to start.

Disclosure of Invention

The invention provides a multi-voltage chip which can reduce the unstable period of a voltage stabilizing circuit.

The multi-voltage chip of the present invention includes: voltage stabilizing circuit, high voltage domain controller, low voltage domain controller and digital logic circuit. The voltage stabilizing circuit receives the feedback signal, the voltage stabilizing starting signal and the reference voltage, and converts the high voltage of the system into the voltage stabilizing voltage in response to the voltage stabilizing starting signal, the feedback signal and the reference voltage. The high voltage domain controller receives the power signal, the system high voltage and the low voltage feedback signal to provide a reference voltage, a voltage stabilization starting signal and a feedback signal. The low voltage domain controller is coupled with the high voltage domain controller and receives the stabilized voltage to provide a system starting signal in response to the stabilized starting signal. The digital logic circuit is coupled to the voltage stabilizing circuit to receive the stabilized voltage and provide a low-voltage feedback signal, and is coupled to the low-voltage domain controller to operate in response to the system start signal.

Based on the above, in the multi-voltage chip according to the embodiment of the invention, the voltage stabilizing circuit is a high-voltage domain controller controlled to receive the high voltage of the system, so that the unstable period of the voltage stabilizing circuit can be reduced.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a system diagram of a multi-voltage chip according to an embodiment of the invention.

Fig. 2 is a system diagram of a high-voltage domain controller and a low-voltage domain controller according to an embodiment of the invention.

FIG. 3 is a schematic diagram of driving waveforms of the high-voltage domain controller and the low-voltage domain controller according to an embodiment of the invention.

Description of the symbols:

100: multi-voltage chip

110: voltage stabilizing circuit

120: digital logic circuit

130: high-voltage domain controller

140: low-voltage domain controller

150-170: power supply circuit

210: first level detector

220: second level detector

230: bandgap circuit

240: first oscillator

250: high voltage controller

260: third level detector

270: second oscillator

280: low-voltage controller

BANDGAPEN: band gap control signal

CLK 1: a first clock signal

CLK 2: the second clock signal

FB: feedback signal

FB _ LV: low voltage feedback signal

Logcstart: system start signal

LVR _ OUT: control enable signal

MAINOSCEN: a second clock control signal

POR _ HVB: high voltage enable signal

POR _ LVB: low voltage control signal

PORSOCEN: a first clock control signal

POWER _ DOWN: power supply signal

REDDEN: regulated start signal

Tmin _ start: starting time

Tpor _ osc: initial clock time

And (3) Trise: rise time of voltage

VDDA: high voltage of system

Vlvr: high voltage ready level

VO 1-VO 3: operating voltage

Vpor _ hv: high voltage reset level

Vpor _ lv: regulated ready level

VREGD: regulated voltage

VRF: reference voltage

VTG: target voltage

Detailed Description

FIG. 1 is a system diagram of a multi-voltage chip according to an embodiment of the invention. Referring to fig. 1, in the present embodiment, a multi-voltage chip 100 includes a voltage regulator circuit 110, a digital logic circuit 120, a high-voltage domain controller 130, a low-voltage domain controller 140, and a plurality of power circuits 150 to 170. The regulator circuit 110 receives the feedback signal FB, the regulated start signal redgen, and the reference voltage VRF to convert the system high voltage VDDA into the regulated voltage VREGD in response to the regulated start signal redgen, the feedback signal FB, and the reference voltage VRF.

The high-voltage domain controller 130 is coupled to the regulator circuit 110 and receives the POWER signal POWER _ DOWN and the system high voltage VDDA to provide the reference voltage VRF, the regulated enable signal redgen provided when the system high voltage VDDA is ready, and the feedback signal FB. Also, after receiving the low voltage feedback signal FB _ LV, the high voltage domain controller 130 provides the feedback signal FB in response to the low voltage feedback signal FB _ LV. The low voltage domain controller 140 is coupled to the regulator circuit 110, the digital logic circuit 120 and the high voltage domain controller 130 to receive the regulated voltage VREGD and the regulated enable signal REGDEN, and the low voltage domain controller 140 detects the regulated voltage VREGD in response to the regulated enable signal REGDEN to provide the system enable signal logiscstart when the regulated voltage VREGD is ready.

The digital logic circuit 120 is coupled to the regulator circuit 110 for receiving the regulated voltage VREGD and providing the low voltage feedback signal FB _ LV, and is coupled to the low voltage domain controller 140 for operating in response to the system enable signal logitstart. The power circuits 150-170 are coupled to the regulator 110 and the high-voltage domain controller 130, and receive the system high voltage VDDA, the reference voltage VRF and the feedback signal FB to provide a plurality of operating voltages VO 1-VO 3, respectively.

Fig. 2 is a system diagram of a high-voltage domain controller and a low-voltage domain controller according to an embodiment of the invention. Referring to fig. 1 and 2, in the present embodiment, the high voltage domain controller 130 includes a first level detector 210, a second level detector 220, a bandgap circuit 230, a first oscillator 240 and a high voltage controller 250. The first level detector 210 is coupled to the second level detector 220, the bandgap circuit 230 and the first oscillator 240, and the high voltage controller 250 is coupled to the second level detector 220, the bandgap circuit 230 and the first oscillator 240. The first level detector 210, the second level detector 220, the bandgap circuit 230, the first oscillator 240 and the high voltage controller 250 receive the system high voltage VDDA.

The low-voltage domain controller 140 includes a third level detector 260, a second oscillator 270, and a low-voltage controller 280. The third level detector 260 is coupled to the second oscillator 270 and the low voltage controller 280, and the low voltage controller 280 is coupled to the second oscillator 270. The third level detector 260, the second oscillator 270, and the low voltage controller 280 receive the regulated voltage VREGD.

FIG. 3 is a schematic diagram of driving waveforms of the high-voltage domain controller and the low-voltage domain controller according to an embodiment of the invention. Referring to fig. 1 to 3, in the present embodiment, when the POWER signal POWER _ DOWN indicates that the multi-voltage chip 100 is powered on (i.e., receives the system high voltage VDDA), the high-voltage domain controller 130 is activated in response to the POWER signal POWER _ DOWN. At this time, the first level detector 210 detects a voltage level of the system high voltage VDDA, and provides the enabled high voltage enable signal POR _ HVB (e.g., at a high voltage level) in response to the system high voltage VDDA rising to the high voltage reset level Vpor _ hv.

Next, the second level detector 220 is activated (as shown by LVREN) in response to the enabling of the high voltage enable signal POR _ HVB to detect the voltage level of the system high voltage VDDA, and enables the control enable signal LVR _ OUT in response to the enabling of the high voltage enable signal POR _ HVB, and disables the control enable signal LVR _ OUT (e.g., is a low voltage level) in response to the system high voltage VDDA rising from the high voltage reset level Vpor _ hv to the high voltage ready level Vlvr, wherein the high voltage ready level Vlvr is higher than the high voltage reset level Vpor _ hv.

The high voltage controller 250 receives the control enable signal LVR _ OUT, provides an enabled bandgap control signal bandopen to the bandgap circuit 230 in response to the POWER signal POWER _ DOWN and the control enable signal LVR _ OUT being enabled, and provides an enabled first clock control signal PORSOCEN to the first oscillator 240 and an enabled regulator enable signal redden to the regulator circuit 110 and the low voltage domain controller 140 in response to the control enable signal LVR _ OUT being disabled.

The bandgap circuit 230 receives the high voltage enable signal POR _ HVB and the bandgap control signal bandgapn and provides the reference voltage VRF in response to the high voltage enable signal POR _ HVB and the bandgap control signal bandgapn. The first oscillator 240 receives the high voltage enable signal POR _ HVB and the first clock control signal PORSOCEN and provides the first clock signal CLK1 in response to the high voltage enable signal POR _ HVB and the first clock control signal PORSOCEN.

The first clock signal CLK1 is mainly limited to be used in the high voltage domain controller 130. The first clock control signal PORSOCEN is enabled in response to the disabling of the control enable signal LVR _ OUT, and is disabled after the initial clock time Tpor _ osc elapses. In the embodiment of the invention, the initial clock time Tpor _ osc is greater than the voltage rise time Trise required for the regulated voltage VREGD to rise from the ground voltage (i.e., voltage 0) to the target voltage VTG.

In the embodiment of the invention, after the initial clock time Tpor _ osc, the high voltage controller 250 provides the feedback signal FB in response to the low voltage feedback signal FB _ LV, wherein the feedback signal FB may be substantially the same as the low voltage feedback signal FB _ LV, i.e. the high voltage controller 250 may directly transmit the low voltage feedback signal FB _ LV as the feedback signal FB, but the embodiment of the invention is not limited thereto. In contrast, the feedback signal FB may be set to a predetermined voltage level (e.g., the ground voltage) during and before the initial clock time Tpor _ osc, but the embodiment of the invention is not limited thereto.

In the low voltage domain controller 140, the third level detector 260 receives the regulated enable signal redgen, detects the regulated voltage VREGD in response to the regulated enable signal redgen, and enables the low voltage control signal POR _ LVB in response to the regulated voltage VREGD rising to the regulated ready level Vpor _ lv. The low voltage controller 280 receives the low voltage control signal POR _ LVB and the first clock control signal PORSOCEN, and sequentially enables the second clock control signal main and the system enable signal logic gate in response to the enabling of the low voltage control signal POR _ LVB and the disabling of the first clock control signal PORSOCEN.

After the digital logic circuit 120 receives the system enable signal logcstart, the digital logic circuit 120 provides the low voltage feedback signal FB _ LV to the high voltage controller 250. The high voltage controller 250 receives the low voltage feedback signal FB _ LV and then provides the feedback signal FB to the power circuits 150-170 and the voltage regulator circuit 110.

The second oscillator 270 receives the regulated enable signal redgen and the second clock control signal main to provide the second clock signal CLK2 in response to the second clock control signal main. The second clock signal CLK2 is used for all of the multi-voltage chip 100, and the frequency of the second clock signal CLK2 is higher than that of the first clock signal CLK 1.

In the embodiment of the present invention, the enable time point of the second clock control signal main is aligned with the disable time point of the first clock control signal porosen, and the system enable signal logic enable is enabled after the enable time Tmain _ start elapses after the second clock control signal main is enabled. Wherein the start time Tmain _ start is greater than the time required for the second oscillator 270 to stably oscillate.

In summary, in the multi-voltage chip according to the embodiment of the invention, the voltage regulator circuit is controlled by the high-voltage domain controller receiving the high voltage of the system, so that the unstable period of the voltage regulator circuit can be reduced. And the low voltage domain controller enables the digital logic circuit when the stabilized voltage is ready so as to prevent the digital logic circuit from providing wrong low voltage feedback signals.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.