Method for patching chip and chip
阅读说明：本技术 为芯片打补丁的方法及芯片 (Method for patching chip and chip ) 是由 邹南 于 2020-01-17 设计创作，主要内容包括：本申请实施例公开了一种为芯片打补丁的方法及芯片,能够通过中断指令进行中转,获得补丁函数的函数地址,从而对需要被替换的函数进行替换。这种方式不需要在指令中携带补丁函数的地址信息,因此不受跳转地址范围的限制,能够实现长地址跳转。所述芯片中包括第一程序,所述方法包括：当运行到所述第一程序中的需要被替换的函数时,根据预存的所述需要被替换的函数的地址与中断指令的对应关系,执行中断服务程序,所述中断服务程序为与所述需要被替换的函数对应的中断指令调度的服务程序,所述中断服务程序的返回地址为所述需要被替换的函数的补丁函数的地址；根据所述补丁函数的地址,运行所述补丁函数,以对所述第一程序进行打补丁处理。(The embodiment of the application discloses a method and a chip for patching a chip, which can transfer through an interrupt instruction to obtain a function address of a patch function, so that the function needing to be replaced is replaced. The method does not need to carry the address information of the patch function in the instruction, so the method is not limited by the jump address range and can realize long address jump. The chip comprises a first program, and the method comprises the following steps: when a function needing to be replaced in the first program is operated, executing an interrupt service program according to a corresponding relation between a prestored address of the function needing to be replaced and an interrupt instruction, wherein the interrupt service program is a service program scheduled by the interrupt instruction corresponding to the function needing to be replaced, and the return address of the interrupt service program is the address of a patch function of the function needing to be replaced; and running the patch function according to the address of the patch function so as to perform patching processing on the first program.)
1. A method for patching a chip, wherein the chip includes a first program, the method comprising:
when a function needing to be replaced in the first program is operated, executing an interrupt service program according to a corresponding relation between a prestored address of the function needing to be replaced and an interrupt instruction, wherein the interrupt service program is a service program scheduled by the interrupt instruction corresponding to the function needing to be replaced, and the return address of the interrupt service program is the address of a patch function of the function needing to be replaced;
and running the patch function according to the address of the patch function so as to perform patching processing on the first program.
2. The method of claim 1, wherein the interrupt instruction is a soft interrupt instruction.
3. The method of claim 1 or 2, wherein the interrupt instruction is a system call SVC instruction.
4. The method of any of claims 1-3, wherein the first program is an intrinsic program in the chip.
5. Method according to any of claims 1-4, wherein the distance between the address of the function to be replaced and the address of the patch function exceeds the address range that one jump instruction can jump to.
6. Method according to any of claims 1-4, wherein the address of the patch function is an arbitrary address in a register of the chip.
7. The method according to any one of claims 1 to 6, wherein when the function needing to be replaced in the first program is executed, executing an interrupt service program according to a pre-stored correspondence relationship between an address of the function needing to be replaced and an interrupt instruction, comprises:
when a function which needs to be replaced in the first program is operated, determining an interrupt instruction corresponding to the function which needs to be replaced according to a corresponding relation between a prestored address of the function which needs to be replaced and the interrupt instruction;
determining an interrupt number according to the interrupt instruction;
and executing the interrupt service program corresponding to the interrupt number according to the interrupt number.
8. The method according to any of claims 1-7, wherein after the running of the patch function according to the address of the patch function, the method further comprises:
executing a next function of the functions in the first program that need to be replaced.
9. The method according to any one of claims 1 to 8, wherein there is a one-to-one correspondence between addresses of functions in the first program that need to be replaced and interrupt instructions.
10. The method according to any one of claims 1 to 9, wherein the correspondence between the address of the function to be replaced and the interrupt instruction is pre-stored in a register of the first component in the chip.
11. The method of claim 10, wherein the first component is a flash address reload and breakpoint FPB.
12. The method according to any of claims 1-11, wherein the chip is a Micro Control Unit (MCU) chip.
13. A chip, characterized in that the chip comprises a processor for performing the method of any of claims 1 to 12.
14. The chip according to claim 13, wherein the chip further comprises a register, and the register is used for storing the correspondence between the address of the function needing to be replaced in the first program and the interrupt instruction.
15. The chip of claim 14, in which the register is a flash address reload and breakpoint FPB register.
Technical Field
The embodiment of the application relates to the technical field of computers, in particular to a method for patching a chip and the chip.
Background
Patch technology is capable of fixing errors in programs and is therefore receiving increasing attention.
At present, a program is patched based on a jump instruction, but the jump instruction cannot realize long address jump, so that strict requirements are placed on storage positions of a replacement function, and the design of a chip on the layout space of a memory is not facilitated.
Disclosure of Invention
The embodiment of the application provides a method for patching a chip and the chip, which can realize long address jump and is beneficial to the layout space design of the chip for a memory.
In a first aspect, a method for patching a chip is provided, where the chip includes a first program, and the method includes: when a function needing to be replaced in the first program is operated, executing an interrupt service program according to a corresponding relation between a prestored address of the function needing to be replaced and an interrupt instruction, wherein the interrupt service program is a service program scheduled by the interrupt instruction corresponding to the function needing to be replaced, and the return address of the interrupt service program is the address of a patch function of the function needing to be replaced; and running the patch function according to the address of the patch function so as to perform patching processing on the first program.
The method transfers through the interrupt instruction to obtain the function address of the patch function, so that the function to be replaced is replaced. In the method, the address information of the patch function is not required to be carried in the interrupt instruction, but the address of the patch function is scheduled by the interrupt service program, so that long address jump can be realized without being limited by a jump address range.
In some possible implementations, the interrupt instruction is a soft interrupt instruction.
In some possible implementations, the interrupt instruction is a system call SVC instruction.
The SVC command can realize interruption only by one command, and occupies less system resources. In addition, the SVC can support a large number of interrupt numbers, and thus can realize a large number of patches.
In some possible implementations, the first program is an inherent program in the chip.
In some possible implementations, the distance between the address of the function to be replaced and the address of the patch function exceeds the address range over which a jump instruction can jump.
In some possible implementations, the address of the patch function is an arbitrary address in a register of the chip.
In some possible implementation manners, when the function needing to be replaced in the first program is run, executing an interrupt service program according to a pre-stored correspondence between an address of the function needing to be replaced and an interrupt instruction, where the executing includes: when a function which needs to be replaced in the first program is operated, determining an interrupt instruction corresponding to the function which needs to be replaced according to a corresponding relation between a prestored address of the function which needs to be replaced and the interrupt instruction; determining an interrupt number according to the interrupt instruction; and executing the interrupt service program corresponding to the interrupt number according to the interrupt number.
In some possible implementations, after the executing the patch function according to the address of the patch function, the method further includes: executing a next function of the functions in the first program that need to be replaced.
In some possible implementations, there is a one-to-one correspondence between addresses of functions in the first program that need to be replaced and interrupt instructions.
In some possible implementations, the first component is a flash address reload and breakpoint FPB.
In some possible implementations, the chip is a MCU chip.
In a second aspect, a chip is provided, where the chip includes a processor configured to perform the method of the first aspect or any one of the possible implementations of the first aspect.
In some possible implementations, the chip further includes a register, and the register is used for storing a correspondence between an address of a function to be replaced in the first program and an interrupt instruction.
In some possible implementations, the register is a flash address reload and breakpoint FPB register.
Drawings
FIG. 1 is a diagram illustrating a conventional patching based on a jump instruction.
Fig. 2 is a schematic diagram of the storage location of the function address.
FIG. 3 is a schematic illustration of patching based on two jump instructions.
Fig. 4 is a schematic flowchart of a method for patching a chip according to an embodiment of the present application.
Fig. 5 is a schematic diagram of an interruption based on an SVC mechanism provided in an embodiment of the present application.
Fig. 6 is a schematic diagram of patching based on SVC breaks according to an embodiment of the present application.
Fig. 7 is a flow diagram of function execution for patching based on SVC breaks.
Fig. 8 is a schematic diagram of a function address replacement list according to an embodiment of the present application.
Fig. 9 is a schematic block diagram of a chip provided in an embodiment of the present application.
Detailed Description
The technical solution in the present application will be described below with reference to the accompanying drawings.
Under the current high-speed development of technology, the development of integrated circuits is very rapid, and the demand of Micro Controller (MCU) type chips is also rapidly developed due to market influence. However, the MCU type chip has a feature that when the chip is manufactured, a code (i.e., a program) is stored in an internal read-only memory (ROM) space to execute a boot (boot) program or other program with a specific function. After the chips are completely downloaded, the programs on the chips cannot be modified again, which requires that the stored programs absolutely have no problem, otherwise the chips with the problems cannot be used again.
In order to solve the problem of high risk, currently, a patch (patch) technology may be used to replace an error function in a program, so that the program can run correctly and the chip can continue to be used. Patch technology has received increasing attention because of its functionality.
The error in the program often exists in one or more functions, and the original function with the error is called by other functions. Although finding these calling functions is difficult, it is easy to find the original function that is in error. Therefore, the critical operations of patching should focus on these erroneous primitives. The patching process comprises the following steps: when the original functions with errors are called, the original functions with errors are jumped to the modified functions (namely patch functions), and the original program is returned after the patch functions are executed. Thus, the wrong primitive function will never be executed, thereby completing the modification of the program.
The patch technology generally needs hardware support, and the kernel of the MCU chip generally can support patch technology. The number of the Patch is limited by the hardware resource, and the more the number of the Patch that the hardware can support, the more the function that can be repaired is represented, and the less the possibility that the chip is wasted.
Thus, if more taps are desired to be supported by a chip, the higher the requirements placed on the chip hardware, and the corresponding increase in chip cost.
The core of the chip in the embodiment of the present application is not specifically limited in type, for example, the core of the chip may be an ARM, and may also be an X86, a Million Instructions Per Second (MIPS), a PowerPC, and the like.
The ARM is used as a kernel for explanation, and provides a patch mode based on flash patch address reload and breakpoint (FPB) hardware.
The current patch technology replaces the old function with the new function to achieve the purpose of program modification. For example, when a program runs to a patched function, a jump instruction is used to cause the program to jump to the address of the patching function to run the patching function. And after the patch function is executed, returning to the original program to continue executing.
The patch technique implemented by the FPB mechanism is described below with reference to fig. 1.
At present, the ARM core-m series of kernels all provide an FPB mechanism which is specially used for making patch for ROM codes of chips. The mechanism of the FPB is to create a list of functions that need to be replaced, i.e. the original function list, and configure the list into hardware FPB registers. Then another function list, namely a patch function list, is created, which is mainly used for storing the address of the new function. The primitive function list has a correspondence to the patch function list, and these two lists and their correspondence are stored in the FPB register. When the Program Counter (PC) pointer is run to the function a that needs to be replaced, the FPB responds automatically and finds the address of the new function, which is automatically assigned to the PC pointer, so that the PC pointer automatically jumps to the new function execution.
As shown in FIG. 1, when the PC pointer is moved to address 0x1000, the processor detects that the address 0x1000 is stored in the register, and the FPB responds automatically, the processor can execute a jump instruction. The processor finds that the address corresponding to the address 0x1000 is 0x2000 according to the corresponding relation between the original function list and the patch function list. The PC pointer would then jump to the 0x2000 address to perform the patch function.
The replacement function technology is generally realized by using a jump instruction, and due to the structural limitation of the jump instruction, the jump instruction can only realize short address jump and cannot realize long address jump. For example, the structure of the jump instruction is the address of the instruction + the patch function, and the address of the instruction + the patch function needs to be stored in a register. If the register is 32 bits, the storage space of the address representing the instruction + the patch function is 32 bits in total, and since the instruction needs to occupy a part of the storage space, the storage space of the address of the patch function is less than 32 bits, so that the system cannot perform full address jump in the 32-bit range.
It is understood that the long address jump in the embodiment of the present application may also be understood as a full address jump.
As shown in FIG. 2, if the primitive function and the patch function are both located in the short address jump range (such as the PowerPC processor, address range is 0x 0-16M) in the memory, the jump instruction may jump to the patch function for execution. However, if the distance between the addresses of the original function and the patch function in the memory is greater than the short address jump range, the jump instruction cannot jump to the patch function for execution.
In order to implement long address jump, the embodiments of the present application may be implemented by multiple jump instructions. For example, a long address jump may be implemented by two jump instructions, as shown in FIG. 3. Firstly, a first jump instruction is used for jumping to a fixed address range to find a transfer function, and a second jump instruction is used for jumping to a final address in the transfer function to find a patch function.
In the method, the distance between the storage position of the transfer function and the addresses of the patched function and the patched function cannot be too far, the transfer function needs to be in a short address jump range, otherwise, the jump cannot be realized, and therefore, the requirement on the storage address of the transfer function by a multi-jump mode is higher. In addition, the design complexity of the instruction by means of multiple jumps is also high.
The embodiment of the application provides a method for patching a chip, the transfer is performed through an interrupt instruction, the limitation of the range of a jump address is avoided, the long address jump is realized, and the realization mode is simpler.
The interrupt handling process is described below.
The interrupt is that when the processor executes the program normally, the processor temporarily suspends the currently executing program due to the triggering of the internal or external event or the presetting of the program, saves the relevant information of the executed program into the stack, and then executes the interrupt service subprogram which is used as the internal or external event or the time preset by the program, after the interrupt service subprogram is executed, the processor acquires the information of the interrupted program saved in the stack again, and continues to execute the interrupted program, which is called interrupt.
The types of interrupts may include three types: 1. soft or inner, 2, outer or hard, 3, exception. The interrupts described in the embodiments of the present application may be of any of these three types.
The soft interrupt is realized through an interrupt instruction and can be manually set according to needs, so that the method is more flexible, and is simple to realize and easy to operate. Therefore, the embodiment of the present application preferably uses soft interrupts for the relay.
For external interrupts, an interrupt request signal is generated by an external device and applied to the NMI or INTR pin of the processor, which identifies whether an interrupt request has occurred by constantly detecting the NMI or INTR pin signal. For internal interrupts, the interrupt request mode does not require an externally applied signal to fire, but rather is invoked by internal interrupt control logic.
Whether an external interrupt or an internal interrupt, the interrupt handling process may include the steps of: request interrupt-response interrupt-close interrupt-reserve breakpoint-interrupt source identification-protect scene-interrupt service subroutine-resume scene-interrupt return.
The method and the device for processing the patch function can add the address information of the patch function in the interrupt return instruction, so that the patch function can be skipped to execute when the interrupt returns, and the patch processing of the chip is realized. After the interruption service program is jumped to the original program, the original error function can not be executed, but the patch function is executed, so that the normal operation of the program is ensured.
For example, after the interrupt service program is executed, the processor may return to the first program and continue execution from the breakpoint of the first program, but since the return address of the interrupt service program is the address of the patch function, after returning to the first program, the processor executes the patch function, and at this time, the PC pointer may be updated to point to the next function of the functions to be replaced in the first program. After the patch function is operated, the next instruction can be operated according to the position pointed by the PC pointer, so that the function needing to be replaced can be skipped, and the function needing to be replaced is not executed, thereby avoiding the operation error of the program.
The chip provided by the embodiment of the application may include a first program, and the first program may be any one of programs stored in the chip. For example, the first program may be an inherent program in the chip, i.e., a non-editable program. For another example, the first program may be an editable program in the chip.
After the first program is stored in the chip, the processor of the chip may run the program to implement the corresponding function.
The chip may be, for example, the MCU chip described above, and the first program may be a program stored in the MCU chip during manufacturing of the MCU chip. Of course, the chip in the embodiment of the present application may also be other types of chips.
However, when some functions in the first program are wrong or need to be replaced, the method of the embodiment of the application can be used for replacement.
As shown in fig. 4, the method provided in the embodiment of the present application may include steps S410 to S420.
S410, when the function which needs to be replaced in the first program is operated, executing an interrupt service program according to the corresponding relation between the address of the function which needs to be replaced and an interrupt instruction, wherein the interrupt service program is a service program scheduled by the interrupt instruction corresponding to the function which needs to be replaced, and the return address of the interrupt service program is the address of a patch function of the function which needs to be replaced.
It will be appreciated that the first program may be written by addresses of functions, that the first program may include addresses of a plurality of functions, and that the processor runs the first program by calling functions stored at the plurality of addresses.
Executing the interrupt service program according to the corresponding relationship between the address of the function to be replaced and the interrupt instruction, may refer to determining the interrupt instruction corresponding to the function to be replaced according to the corresponding relationship between the address of the function to be replaced and the interrupt instruction, then determining an interrupt number according to the interrupt instruction, and executing the interrupt service program corresponding to the interrupt number according to the interrupt number.
The address of the function of the first program includes an address of a function in the first program where an error occurs or needs to be replaced. The method and the device for processing the interrupt instruction can pre-establish the corresponding relation between the address of the function needing to be replaced and the interrupt instruction, so that when the function needing to be replaced is hit, the interrupt instruction can be jumped to according to the corresponding relation.
The addresses of the functions that need to be replaced may have a one-to-one correspondence with the interrupt instructions. For example, a list of addresses of functions to be replaced and a list of interrupt instructions may be established in advance, and the contents of the two lists have a one-to-one correspondence relationship. If there are multiple functions to be replaced in the first program, the multiple functions to be replaced may correspond to multiple interrupt instructions, and the multiple functions to be replaced have a one-to-one correspondence relationship with the multiple interrupt instructions.
In the running process of the first program, when the function which needs to be replaced runs, the system can automatically respond, and find the corresponding interrupt instruction according to the corresponding relation between the address of the function which needs to be replaced and the interrupt instruction.
The function to be replaced that is run into the first program may refer to the PC pointer pointing to the function to be replaced.
And S420, operating the patch function according to the address of the patch function so as to perform patching processing on the first program.
By means of the interrupt instruction, the interrupt service routine that triggered the interrupt can be found. The interrupt instruction may include an interrupt number, and different interrupt sources have different interrupt numbers, so that the embodiment of the present application may determine, by using the interrupt number, the interrupt source that triggers the interrupt, so as to find the interrupt service routine.
The interrupt number is the code number that the system assigns to each interrupt source for identification and processing. The processor can find the entry address of the interrupt service program through the interrupt number to realize the program transfer.
Thus, the processor may suspend execution of the first program in accordance with the interrupt instruction and jump to the interrupt service routine to execute the interrupt service routine. After the running of the interrupt service program is finished, returning to the first program to continue executing.
After the interrupt service program is executed, the processor needs to return to the original program to continue executing, so that each interrupt service program needs to have an interrupt return instruction, so that after the interrupt event is processed, the processor can return to the original program to continue executing.
According to the method and the device, the address information of the patch function can be added in the interrupt return instruction, so that when the interrupt returns, the system can automatically jump to the patch function to execute the patch function, and does not execute the function needing to be replaced, and therefore patching processing of the chip is achieved.
The patching method provided by the embodiment of the application is a patching processing of a running program, the address of a patch function is not stored in an instruction but is obtained from another program (such as an interrupt service program), the address information of the patch function is called by the interrupt service program, and the interrupt service program can call a function at any address, so that the address of the patch function can be the address of any storage space in a chip and is not limited by a jump address range. Therefore, long address jump can be realized by patching the interrupt instruction, which is beneficial to the layout design of the SRAM and the flash to the storage space.
For example, for a 32-bit register, the interrupt service routine may call any address within the 32-bit range, thereby enabling a full address jump. It will be appreciated that the register is the register described above for storing the address of the patch function in correspondence with the interrupt instruction.
In addition, because the address of the primitive function and the interrupt instruction corresponding to the address of the primitive function are prestored in the chip, the system can automatically respond and execute the corresponding interrupt instruction without human intervention. For the replacement of a plurality of identical functions in the program, the manual replacement operation of each function is not needed, the system can realize the replacement of a plurality of positions according to the pre-stored corresponding relation, and the operation process is simple.
Different addresses of primitive functions can correspond to different interrupt instructions, different interrupt instructions can trigger different interrupt service programs, different interrupt service programs can correspond to different return addresses, one return address corresponds to an address of a patch function, therefore, different addresses of primitive functions can correspond to different addresses of patch functions through the interrupt instructions, and patching processing can be carried out on multiple positions of a program through a plurality of interrupt instructions.
Therefore, when a plurality of primitive functions in a program have errors, the corresponding relation between the addresses of the primitive functions and a plurality of interrupt instructions can be stored in a register, and the addresses of patch functions can be called by the interrupt instructions to patch the program.
The method of the embodiment of the present application may also be applied to the upgrade process of a system or software, which is not particularly limited.
As a preferred implementation manner, the interrupt instruction of the embodiment of the present application may be a soft interrupt instruction, and the soft interrupt instruction may be a system service call (SVC) instruction.
SVC interrupts are special interrupts that are used mostly in software development on top of the operating system. The SVC is used to generate call requests for system functions. For example, instead of having the user program directly access the hardware, the operating system provides some system service functions to which the user program calls in this way by issuing call requests using the SVC. Thus, when a user program wants to control a particular piece of hardware, it generates an SVC exception, and an SVC exception service routine provided by the operating system is executed, which recalls the associated operating system functions that complete the service requested by the user program.
Fig. 5 shows a schematic diagram of the interruption mechanism of SVC. When the system detects an SVC interruption instruction in the process of running on the main program, the system jumps to an SVC service program corresponding to the SVC interruption instruction to run the SVC service program.
The SVC interruption is the interruption that must be immediately patched, so that the first program can be guaranteed to be patched immediately by the SVC interruption.
The SVC interruption has the other characteristics that the interruption can be realized only by one instruction, the realization mode is simple, and the storage space occupied by the instruction is small.
The SVC instruction is simple in setting mode and generally has the following topography:
In addition, the SVC interrupt can support more interrupt numbers, for example, 256 interrupt numbers can be supported, each interrupt number corresponds to one interrupt service routine, and each interrupt service routine can return an address of a patch function, so that the SVC interrupt can support 256 patches. Therefore, the SVC instruction can support a larger number of patches, and the hardware of the chip does not need to be improved, so that the cost is lower.
The correspondence relationship between the address of the function of the first program and the interrupt instruction may be pre-stored in a register of the first component in the chip. The first component belongs to a hardware resource of the chip.
The first component may be the FPB described above. In the register of the FPB, two lists are stored, one is an address difference table of a function to be replaced, and the other is a list of an interrupt instruction, and the contents of the two lists have a one-to-one correspondence relationship.
The following describes the patching process of the chip by taking SVC instructions as an example in conjunction with fig. 6 and 7.
As shown in fig. 6, there are two lists in the FPB register, one list is the list of addresses of primitive functions and the other list is the list of SVC instructions. The address of the original function indicates the address of the function that needs to be replaced in the first program.
In the list shown in fig. 6, the interrupt command corresponding to the address 0x1000 of the primitive function is SVC #1, and the interrupt command corresponding to the address 0x1200 of the primitive function is
The significance of pre-storing the list of SVC interrupt instructions in the FPB register is that when the address of the primitive function in the list is hit, the processor can determine the SVC instruction corresponding to the address of the primitive function according to the corresponding relation in the list. The SVC instruction then triggers an SVC interrupt, and the SVC instruction can include an interrupt number, such that the system can obtain the SVC interrupt service routine corresponding to the interrupt number based on the interrupt number. After the SVC interrupt service routine is executed, an SVC interrupt return may be performed, and then the processor may run a patch function corresponding to a return address of the SVC interrupt according to the return address. In fig. 5, after the SVC interrupt service program runs, the address of the patch function is obtained as 0x30000000 by the SVC interrupt return address. The PC pointer may jump to the address 0x30000000 causing the processor to run the patch function at the address 0x 30000000.
It is understood that the interrupt service routine in the embodiment of the present application may also be referred to as an interrupt handling function.
In fig. 6 and 7, function a in the program is a function in which an error occurs, and the address of function a is 0x 1200. When the PC pointer is moved to address 0x1200, the processor detects that the address exists in the FPB register, and may execute
After the function B is executed, the PC pointer is updated and points to the next instruction in the program after the function a, so that the processor can skip the function a and execute the next function after the function a after the function B is executed.
The method and the device for patching the chip can also be used for patching the chip in a mode of combining the jump instruction and the SVC interruption.
Two lists can be stored in the FPB register, one list is the list of addresses of original functions, and the other list is the list of the combination of SVC instruction and addresses of new functions. As shown in fig. 8, address 0x1000 of the original function corresponds to address 0x2000 of the new function, and address 0x1200 of the original function corresponds to the interrupt
In this embodiment, the patch function may be patched by the above-mentioned interrupt method in any case, and in this case, the address of the patch function may be any address in a register, or, in a case where a distance between the address of the function to be replaced and the address of the patch function exceeds an address range where a jump instruction can jump, patching may be performed in the above-described manner.
For example, for the case that the distance between the address of the patch function and the address of the original function is within the address range where a jump instruction can jump, the jump instruction can be used to jump, so as to implement the patching processing on the chip; and for the condition that the distance between the address of the patch function and the address of the original function exceeds the address range which can be jumped by a jump instruction, the SVC interrupt can be used for acquiring the address of the patch function so as to realize the patching processing of the chip.
The address range to which a jump instruction can jump is understood to be the short address jump range.
It will be appreciated that the range of short address jumps may be different for different cores. For an ARM core, the short address jump range is 0-32M; if the ARM core uses the thumb instruction set, the short address jump range is 0-4M. For the PowerPC kernel, the short address jump range is 0-16M, and it should be noted that the address range where one jump instruction can jump may also be a preset address range, and the preset address range may be set according to user requirements or different kernels.
In addition, an embodiment of the present application further provides a chip, as shown in fig. 9, where the chip 1000 includes a processor 1010, and the processor 1010 is configured to execute any one of the above-described methods for patching a chip.
Optionally, the chip 1010 further includes a register 1020 for storing a correspondence between an address of a function to be replaced and an interrupt instruction.
Optionally, the register is an FPB register.
It is to be understood that the terminology used in the embodiments of the present application and the appended claims is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of the present application.
For example, as used in the examples of this application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
Those of skill in the art would appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the embodiments of the present application.
If implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application may be essentially implemented or make a contribution to the prior art, or may be implemented in the form of a software product stored in a storage medium and including several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: u disk, removable hard disk, read only memory, random access memory, magnetic or optical disk, etc. for storing program codes.
The above description is only a specific implementation of the embodiments of the present application, but the scope of the embodiments of the present application is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the embodiments of the present application, and all the changes or substitutions should be covered by the scope of the embodiments of the present application. Therefore, the protection scope of the embodiments of the present application shall be subject to the protection scope of the claims.
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