阅读说明：本技术 一种低温度系数快速电压检测电路 (Low-temperature coefficient rapid voltage detection circuit ) 是由 吴建辉 周全才 谢祖帅 吴志强 瞿剑 于 2020-07-31 设计创作，主要内容包括：本发明公开了应用于能量采集领域的一种低温度系数快速电压检测电路,该电压检测电路包括CTAT偏置电路、正反馈偏置电路和电压检测电路；供电电压即输入信号端(V<Sub>in</Sub>),电路整体输出信号端(V<Sub>out</Sub>)；CTAT偏置电路的输出端(V<Sub>bias</Sub>)接电压检测电路的输入端,电压检测电路的输出端即电路整体输出信号端(V<Sub>out</Sub>)与正反馈偏置电路的输入端相连。电压检测电路由两个cascode MOS管构成,当上拉网络电流和下拉网络电流相等时,达到检测电压。通过CTAT基准电路为电压检测电路的上检测管提供偏置,从而降低了温度对检测电压值的影响。通过正反馈偏置电路为电压检测电路的下检测管提供偏置,当达到检测电压时通过反馈网络减小下拉网络的电流,从而加快输出端触发信号的建立。(The invention discloses a low-temperature coefficient rapid voltage detection circuit applied to the field of energy collection, which comprises a CTAT bias circuit, a positive feedback bias circuit and a voltage detection circuit; supply voltage, i.e. input signal terminal (V) in ) Output signal terminal (V) of circuit out ) (ii) a Output terminal (V) of CTAT bias circuit bias ) Is connected with the input end of the voltage detection circuit and the output end of the voltage detection circuit, namely the output signal end (V) of the whole circuit out ) Connected to the input of the positive feedback bias circuit. The voltage detection circuit is composed of two cascode MOS tubes, and when the pull-up network current and the pull-down network current are equal, the voltage detection circuit achieves detection voltage. The upper detection tube of the voltage detection circuit is provided with bias through the CTAT reference circuit, so that the influence of temperature on the detection voltage value is reduced. The positive feedback bias circuit provides bias for a lower detection tube of the voltage detection circuit, and when the detection voltage is reached, the current of the pull-down network is reduced through the feedback network, so that the establishment of the output end trigger signal is accelerated.)

1. A low temperature coefficient rapid voltage detection circuit is characterized in that the voltage detection circuit comprises a CTAT bias circuit, a positive feedback bias circuit and a voltage detection circuit; supply voltage, i.e. input signal terminal (V)_in) Output signal terminal (V) of circuit_out) (ii) a Output terminal (V) of CTAT bias circuit_bias) Is connected with the input end of the voltage detection circuit and the output end of the voltage detection circuit, namely the output signal end (V) of the whole circuit_out) Connected to the input of the positive feedback bias circuit.

2. The low temperature coefficient fast voltage detecting circuit as claimed in claim 1, wherein the CTAT bias circuit portion is composed of a first transistor (M1), a second transistor (M2), a third transistor (M3), a fourth transistor (M4), a fifth transistor (M5); the positive feedback bias circuit is composed of a sixth transistor (M6) and a seventh transistor (M7); the voltage detection circuit part is composed of an eighth transistor (M8) and a ninth transistor (M9) which are cascaded.

3. The low temperature coefficient fast voltage detection circuit of claim 1, wherein the first transistor (M1), the second transistor (M2), and the eighth transistor (M8) are PMOS transistors, and the third transistor (M3), the fourth transistor (M4), the fifth transistor (M5), the sixth transistor (M6), the seventh transistor (M7), and the ninth transistor (M9) are NMOS transistors.

4. The low temperature coefficient fast voltage detecting circuit as claimed in claim 3, wherein the fifth transistor (M5) is a thick gate NMOS transistor having a higher threshold voltage.

5. The fast voltage detection circuit with low temperature coefficient as claimed in claim 2, wherein in the CTAT bias circuit, the first transistor (M1) is connected with the input signal terminal (V) as the source of the supply voltage_in) A gate of the first transistor (M1) is connected to a drain of the first transistor (M1) and a gate of the second transistor (M2), respectively, and a drain of the first transistor (M1) is connected to a drain of the third transistor (M3); the source of the second transistor (M2) is connected to the supply voltage, i.e. the input signal terminal (V)_in) The drain of the second transistor (M2) is connected to the drain of the fourth transistor (M4) to form the output terminal (V) of the CTAT biasing circuit_bias) (ii) a The gate of the fourth transistor (M4) is connected with the drain of the fourth transistor (M4) and the gate of the fifth transistor (M5), the source of the fourth transistor (M4) is connected with the drain of the fifth transistor (M5) to be connected with the gate of the third transistor (M3) and provide bias for the gate of the third transistor (M3); the drains of the fifth transistor (M5) and the third transistor (M3) are grounded.

6. The low temperature coefficient fast voltage detecting circuit as claimed in claim 2, wherein in said positive feedback bias circuit, the drain of the sixth transistor (M6) is connected to the supply voltage (i.e. input signal terminal V)_in) A gate of the sixth transistor (M6) is connected to the source, and a source of the sixth transistor (M6) is connected to a gate of the seventh transistor (M7); the source of the seventh transistor (M7) is grounded.

7. The fast voltage detection circuit with low temperature coefficient as claimed in claim 2, wherein the voltage detection circuit part is composed of an eighth transistor (M8) and a ninth transistor (M9), and the source of the eighth transistor (M8) is connected to the input signal terminal (V)_in) Eighth CrystalThe gate of the transistor (M8) and the output (V) of the CTAT bias circuit_bias) And the drain electrode of the eighth transistor (M8) and the drain electrode of the ninth transistor (M9) are connected to form an output signal end (V) of the whole circuit_out) While the circuit outputs a signal terminal (V) as a whole_out) Is connected with the gate of a seventh transistor (M7) in the positive feedback bias circuit; the gate of the ninth transistor (M9) is connected with the gate of the sixth transistor (M6) in the positive feedback bias circuit to form a positive feedback loop, and the source of the ninth transistor (M9) is grounded.

Technical Field

The invention belongs to the field of energy collection, and particularly relates to a voltage detection circuit capable of realizing low temperature coefficient rapidness.

Background

With the development of the technology of the internet of things, it is currently an important research direction to obtain energy from the environment to supply power to equipment, and the energy acquisition circuit converts the voltage generated by the energy source into the voltage value required by the system through the conversion circuit. Due to the change of the environment, the voltage value generated by the energy source fluctuates, and in order to stabilize the output voltage of the energy collection system, the input or output voltage needs to be detected. Since the power generated by the energy source is typically low, the power consumption of the various modules in the energy harvesting circuit needs to be minimized. And the working environment of the nodes of the internet of things is relatively complex, so that the voltage detection circuit needs good temperature isolation, and the detection voltage is not influenced by temperature. In addition, the quick response of the voltage detection circuit is beneficial to keeping the stability of the output voltage of the energy acquisition system, so the invention provides the voltage detection circuit with a quick low temperature coefficient.

A bandgap reference (BGR) and a comparator are commonly used to detect the voltage, and since the operating voltage of the bandgap reference circuit is relatively high and a dc bias resistor is used, the power consumption thereof is relatively large. The energy acquisition circuit generally needs to work under low voltage and low power consumption, and a voltage detection circuit consisting of two MOS tubes with cascode structures is proposed, wherein the detection voltage is determined by comparing the current of a pull-up network and the current of a pull-down network, wherein the current of the pull-up network is increased along with the increase of input voltage, the current of the pull-down network is kept unchanged, and different detection voltages can be realized by setting the width-length ratio of the MOS tubes. However, this method requires a very large aspect ratio, and the detected voltage value increases with the temperature, so that the voltage detection result may have a large deviation under different environments, and the trigger signal at the output end is very slow to establish when the input voltage is closer to the detected voltage. The invention provides a voltage detection circuit with a quick low temperature coefficient, which is mainly designed by providing bias with a temperature coefficient for an upper detection tube to realize the low temperature coefficient of detection voltage; the current of the pull-down network is reduced through feedback, and the establishment of the trigger signal is accelerated.

Disclosure of Invention

The technical problem is as follows: the invention aims to provide a low-temperature coefficient rapid voltage detection circuit applied to an energy acquisition circuit, which is used as a basic unit of an analog circuit and can realize voltage detection under different environments.

The technical scheme is as follows: in order to solve the technical problem, the low-temperature coefficient rapid voltage detection circuit adopts the following technical scheme:

the voltage detection circuit comprises a CTAT biasing circuit, a positive feedback biasing circuit and a voltage detection circuit; the power supply voltage is an input signal end, and the circuit integrally outputs a signal end; the output end of the CTAT (negative to absolute temperature (CTAT)) bias circuit is connected to the input end of the voltage detection circuit, and the output end of the voltage detection circuit, that is, the output signal end of the whole circuit, is connected to the input end of the positive feedback bias circuit.

The CTAT bias circuit part consists of a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor; the positive feedback bias circuit consists of a sixth transistor and a seventh transistor; the voltage detection circuit portion is composed of an eighth transistor and a ninth transistor which are cascaded.

The first transistor, the second transistor and the eighth transistor are PMOS transistors, and the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the ninth transistor are NMOS transistors.

The fifth transistor is a thick gate NMOS transistor and has a higher threshold voltage.

In the CTAT biasing circuit, a source of a first transistor is connected with a power supply voltage, namely an input signal end in a cascade mode, a grid electrode of the first transistor is respectively connected with a drain electrode of the first transistor and a grid electrode of a second transistor, and a drain electrode of the first transistor is connected with a drain electrode of a third transistor; the source electrode of the second transistor is connected with a power supply voltage, namely an input signal end, and the drain electrode of the second transistor is connected with the drain electrode of the fourth transistor to form the output end of the CTAT biasing circuit; the grid electrode of the fourth transistor is connected with the drain electrode of the fourth transistor and the grid electrode of the fifth transistor, the source electrode of the fourth transistor is connected with the drain electrode of the fifth transistor, the grid electrode of the third transistor is connected, and a bias is provided for the grid electrode of the third transistor; the drains of the fifth transistor and the third transistor are grounded.

In the positive feedback bias circuit, the drain electrode of a sixth transistor is connected with a power supply voltage, namely an input signal end, the grid electrode of the sixth transistor is connected with a source electrode, and the source electrode of the sixth transistor is connected with the grid electrode of a seventh transistor; the source of the seventh transistor is connected to ground.

The voltage detection circuit part consists of an eighth transistor and a ninth transistor, wherein the source of the eighth transistor is connected with a power supply voltage, namely an input signal end, and the grid of the eighth transistor is connected with the output end of the CTAT biasing circuit; the drain electrode of the eighth transistor is connected with the drain electrode of the ninth transistor to form a circuit integral output signal end, and meanwhile, the circuit integral output signal end is connected with the grid electrode of the seventh transistor in the positive feedback biasing circuit; and the grid electrode of the ninth transistor is connected with the grid electrode of the sixth transistor in the positive feedback biasing circuit to form a positive feedback loop, and the source stage of the ninth transistor is grounded.

Has the advantages that: compared with the prior art, the invention has the following advantages:

the upper detection tube of the voltage detection circuit is provided with bias through the CTAT reference circuit, so that the influence of temperature on a detection voltage value is reduced, and the low temperature coefficient of the detection voltage is realized. The positive feedback bias circuit provides bias for a lower detection tube of the voltage detection circuit, and when the detection voltage is reached, the current of the pull-down network is reduced through the feedback network, so that the establishment of the output end trigger signal is accelerated.

Drawings

FIG. 1 is a circuit topology of the present invention;

FIG. 2 is a graph showing the relationship between the input voltage and the output voltage of the low temperature coefficient rapid voltage detection circuit realized by the present invention at different temperatures (-20 deg.C-80 deg.C).

FIG. 3 is a partial enlarged view of the relationship curve between the input voltage and the output voltage of the low temperature coefficient rapid voltage detection circuit realized by the invention under different temperatures (-20 ℃ -80 ℃).

FIG. 4 shows the detection voltage V of the low temperature coefficient fast voltage detection circuit implemented by the present invention_detectTemperature dependence.

Fig. 5 is a transient characteristic curve of a low temperature coefficient fast voltage detection circuit implemented by the present invention.

The figure shows that: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9; supply voltage, i.e. input signal terminal V_inOutput end V of CTAT bias circuit_biasAnd a circuit integral output signal end V_out。

Detailed Description

The invention is further described below with reference to the accompanying drawings.

The low-temperature coefficient rapid voltage detection circuit is composed of a CTAT bias circuit, a positive feedback bias circuit and a voltage detection circuit.

The circuit supply voltage and the input signal are V_inThe overall output signal of the circuit is V_out。

The voltage detection circuit part consists of an eighth transistor M8 and a ninth transistor M9 which are cascaded, the CTAT bias circuit part consists of a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4 and a fifth transistor M5, the positive feedback bias circuit consists of a sixth transistor M6 and a seventh transistor M7, wherein the first transistor M1, the second transistor M2 and the eighth transistor M8 are PMOS, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the ninth transistor M9 are NMOS, and the fifth transistor M5 is a thick-gate NMOS transistor and has a higher threshold voltage.

The CTAT bias circuit comprises a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4 and a fifth transistor M5, wherein the source of the first transistor M1 is connected with a power supply voltage, namely an input signal end V_inA gate of the first transistor M1 is connected to a drain of the first transistor M1 and a gate of the second transistor M2, respectively, and a drain of the first transistor M1 is connected to the third transistor M3The drain electrodes of the two electrodes are connected; the source of the second transistor M2 is connected to the supply voltage, i.e. the input signal terminal V_inThe drain of the second transistor M2 is connected to the drain of the fourth transistor M4 to form the output terminal V of the CTAT biasing circuit_bias(ii) a The gate of the fourth transistor M4 is connected to the drain of the fourth transistor M4 and the gate of the fifth transistor M5, the source of the fourth transistor M4 is connected to the drain of the fifth transistor M5, and the gate of the third transistor M3 is biased to be connected to the gate of the third transistor; the drains of the third transistor M5 and the third transistor M3 are grounded.

The positive feedback bias circuit comprises a sixth transistor M6 and a seventh transistor M7, the drain of the sixth transistor M6 is connected with the power supply voltage, namely the input signal end V_inThe gate of the sixth transistor M6 is connected to the source, and the source of the sixth transistor M6 is connected to the gate of the seventh transistor M7; the source of the seventh transistor M7 is connected to ground. The voltage detection circuit part consists of an eighth transistor M8 and a ninth transistor M9, the source of the eighth transistor M8 is connected with the power supply voltage, namely the input signal end V_inThe gate of the eighth transistor M8 and the CTAT biased output V_biasAnd the drain electrode of the eighth transistor M8 and the drain electrode of the ninth transistor M9 are connected to form an output end V of the whole circuit_outMeanwhile, the output end is connected with the grid electrode of a seventh transistor M7 in the positive feedback bias circuit; the gate of the ninth transistor M9 is connected to the gate of the sixth transistor M6 in the positive feedback bias circuit, which forms a positive feedback loop, and the source of the ninth transistor M9 is grounded.

The invention provides bias for the upper detection tube of the voltage detection circuit through the CTAT reference circuit, thereby reducing the influence of temperature on the detection voltage value and realizing the low temperature coefficient of the detection voltage. The positive feedback bias circuit provides bias for a lower detection tube of the voltage detection circuit, and when the detection voltage is reached, the current of the pull-down network is reduced through the feedback network, so that the establishment of the output end trigger signal is accelerated. The operation principle of the simulation method is described in detail below with reference to specific circuits and simulation results.

As shown in fig. 1, in the proposed structure of the present invention, the voltage detection circuit is composed of a cascade connection of a PMOS eighth transistor M8 and an NMOS ninth transistor M9,the gate of the eighth transistor M8 and the output V of the CTAT biasing circuit_biasThe gate of the ninth transistor M9 is connected to V of the positive feedback bias circuit_xThe nodes are connected. Detecting voltage value V_detectIs defined as making the voltage detection circuit output end V_outInput signal terminal V of input power supply voltage with voltage changing from low to high_inThe value of the current of the pull-up network at this time is the current I flowing through the eighth transistor M8_M8Current I to the pull-down network_M9Equally, the eighth transistor M8 and the ninth transistor M9 operate in the sub-threshold region, assuming V_dsMore than 100mV, according to the expression of subthreshold region current, formula 1 can be obtained:

wherein mu₈，μ₉Denotes mobility, C, of the eighth transistor M8, the ninth transistor M9_oxDenotes the oxide capacitance per unit area, m₈，m₉Represents the sub-threshold slope factors, V, of the eighth transistor M8, the ninth transistor M9_TRepresents a thermal voltage whose value is proportional to the absolute temperature, (W/L)₈，(W/L)₉Denotes the width-to-length ratio, V, of M8 and M9_th8，V_th9Indicates the threshold voltages, V, of the eighth transistor M8, the ninth transistor M9_detectIndicating the value of the detected voltage, V_biasIndicating the bias voltage, V, supplied by the CTAT bias circuit output to the gate of the eighth transistor M8_xIndicating the bias voltage provided by the positive feedback bias circuit to the gate of the ninth transistor M9.

It is assumed that the sub-threshold slope factors and the threshold voltages of the eighth transistor M8 and the ninth transistor M9 are approximately equal, i.e., M ═ M₈＝m₉，V_th8＝V_th9And the detection voltage value V can be obtained by simplification_detectIs expressed as formula 2:

wherein V_detectIncluding temperature-dependent in the expressionAn item, wherein

Proportional to absolute temperature by adjusting V_biasAnd V_xThe cancellation of positive and negative temperature coefficients can be realized, and V can be realized_detectLow temperature coefficient of (2).

The positive feedback bias circuit consists of a sixth transistor M6 and a seventh transistor M7, when V is_in＜V_detectWhen, V_outClose to 0, V of the sixth and seventh transistors M6, M7 _gs0, thus V_xThe point voltage is divided by the transistors of the sixth transistor M6 and the seventh transistor M7, and the width-to-length ratio of the transistors of the sixth transistor M6 and the seventh transistor M7 is set to be V_xThe partial pressure value of the spot. When V is_in>V_detectWhen, V_outThe voltage will gradually rise to V_inSo that V of the tube of the seventh transistor M7_gsIncrease to V_xThe point potential is reduced, and the V of the tube M9 of the ninth transistor is reduced_gsSo that the current of the pull-down network of the voltage detection branch circuit is reduced, and the output end V is accelerated_outThe voltage rising speed accelerates the establishment of the trigger signal.

The CTAT bias circuit consists of a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4 and a fifth transistor M5, wherein the fourth transistor M4 and the fifth transistor M5 work in a subthreshold region, the fifth transistor M5 is a MOS transistor with high threshold voltage, and in order to make the circuit work at the lowest possible current, the bias current is output by an output voltage V_yThe third transistor M3 is biased through a feedback path, forming a self-biased configuration. V_yThe point bias voltage is shown in equation 3:

wherein V_gs4，V_gs5Respectively, the gate-source voltages, V, of the fourth transistor M4 and the fifth transistor M5_th4，V_th5Respectively, the threshold voltages of the fourth transistor M4 and the fifth transistor M5, M represents a sub-threshold slope factor, μ₄，μ₅Respectively, the mobility of the fourth transistor M4 and the fifth transistor M5, (W/L)₄，(W/L)₅Respectively, the width-to-length ratios of the fourth transistor M4 and the fifth transistor M5 are shown.

The first transistor M1 and the second transistor M2 form a current mirror, the current determined by self-bias is copied to the branch of the second transistor M2, and the output voltage V is biased_biasNamely, the gate voltages of the fourth transistor M4 and the fifth transistor M5, as shown in equation 4:

wherein I_M5Indicating the current flowing through the fifth transistor M5. Threshold voltage V of fifth transistor M5_th5The temperature is increased and decreased, and the temperature coefficient is negative, the second term of the formula 4 can realize positive temperature coefficient or negative temperature coefficient by adjusting the width-to-length ratio of the fifth transistor M5, and in this application, the required CTAT bias voltage can be obtained by adjusting the width-to-length ratio of the fifth transistor M5. Make it and the detection voltage V_detectThe temperature coefficients of the temperature-dependent terms in the expression cancel each other out to realize the low temperature coefficient of the detection voltage. The CTAT biasing circuit works in a subthreshold region and can normally work under low voltage.

FIG. 2 is a graph showing the relationship between the input voltage and the output voltage of the low temperature coefficient rapid voltage detection circuit implemented by the present invention at different temperatures (-20 deg.C-80 deg.C), and it is obvious from the graph that the detection voltage has little variation with temperature at different temperatures.

FIG. 3 is a partial enlarged view of the relationship curve between the input voltage and the output voltage of the low temperature coefficient rapid voltage detection circuit realized by the invention at different temperatures (-20 ℃ -80 ℃), wherein the detection voltage variation range is 546.5mV-548.5mV within the temperature range.

FIG. 4 shows the detection voltage V of the low temperature coefficient fast voltage detection circuit implemented by the present invention_detectAccording to the relation curve with the temperature, the temperature coefficient of the detection voltage is 0.016 mV/DEG C.

FIG. 5 is a diagram showing the transient characteristic curve of the low temperature coefficient rapid voltage detection circuit implemented by the present invention, when the voltage V is detected_detect547.5mV, the supply voltage is the input signal terminal V_inAt 550mV, the voltage V is output after 0.2ms_outIs lifted to V_in。

The above description is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above embodiment, but equivalent modifications or changes made by those skilled in the art according to the present disclosure should be included in the scope of the present invention as set forth in the appended claims.