阅读说明：本技术 电源合路电路、诊断方法、装置及系统 (Power supply combining circuit, diagnosis method, device and system ) 是由 程佳 于 2020-03-20 设计创作，主要内容包括：本申请公开了一种电源合路电路、诊断方法、装置及系统,涉及电源技术领域,该电源合路电路是带有诊断功能的电源合路电路。该电源合路电路系统包括：合路电路模块和控制模块。合路电路模块包括第一电源、第一场效应管、第二电源以及第二场效应管。控制模块用于控制合路电路模块为负载电路供电,并获取第一输入电压、第二输入电压和第三输入电压,以及,基于所获取的电压,诊断合路电路模块是否异常；其中,第一输入电压是第一场效应管的输入侧电压,第二输入电压是第二场效应管的输入侧电压,第三输入电压是负载电路的电源输入端的电压。(The application discloses a power supply combining circuit, a diagnosis method, a diagnosis device and a diagnosis system, and relates to the technical field of power supplies. This power combiner circuit system includes: a combiner circuit module and a control module. The combiner circuit module comprises a first power supply, a first field effect transistor, a second power supply and a second field effect transistor. The control module is used for controlling the combiner circuit module to supply power to the load circuit, acquiring a first input voltage, a second input voltage and a third input voltage, and diagnosing whether the combiner circuit module is abnormal or not based on the acquired voltages; the first input voltage is the input side voltage of the first field effect transistor, the second input voltage is the input side voltage of the second field effect transistor, and the third input voltage is the voltage of the power supply input end of the load circuit.)

1. The utility model provides a power supply combiner circuit, its characterized in that, power supply combiner circuit is applied to in power supply combiner circuit system, power supply combiner circuit includes:

a combiner circuit module; the combiner circuit module comprises a first power supply, a first field effect transistor, a second power supply and a second field effect transistor; the first power supply is connected with the input end of the first field effect transistor, the second power supply is connected with the input end of the second field effect transistor, and the output end of the first field effect transistor and the output end of the second field effect transistor are both connected with the power supply input end of the load circuit;

a control module; the control module is used for controlling the combiner circuit module to supply power to the load circuit, acquiring a first input voltage, a second input voltage and a third input voltage, and diagnosing whether the combiner circuit module is abnormal or not based on the acquired voltages; wherein the first input voltage is an input side voltage of the first field effect transistor, the second input voltage is an input side voltage of the second field effect transistor, and the third input voltage is a voltage of a power supply input terminal of the load circuit.

2. The circuit of claim 1,

the control module is further used for diagnosing whether the combiner circuit module is abnormal or not based on the acquired voltage and preset parameters;

wherein the preset parameters include at least one of: the maximum voltage drop value of the second field effect transistor is calculated based on the maximum current of the load circuit, or the maximum voltage drop value of the second field effect transistor is calculated based on the maximum current of the load circuit.

3. The circuit of claim 1 or 2, wherein the power combining circuit further comprises:

a sampling module; the sampling module is respectively connected with the input end of the first field effect transistor, the input end of the second field effect transistor and the power supply input end of the load circuit;

the sampling module is used for collecting the first input voltage, the second input voltage and the third input voltage;

the control module is further configured to obtain the first input voltage, the second input voltage, and the third input voltage collected by the sampling module.

4. The circuit of claim 3,

the control module is also used for controlling the states of the first field effect transistor and the second field effect transistor; the states include an on state and an off state; the sampling module is used for acquiring the first input voltage, the second input voltage and the third input voltage of the first field effect transistor and the second field effect in a target state combination, wherein the first field effect transistor and the second field effect are acquired by the sampling module;

wherein the target state combination comprises any one of: the first field effect transistor and the second field effect transistor are both in a conducting state; the first field effect transistor and the second field effect transistor are both in a cut-off state; the first field effect transistor is in a conducting state, and the second field effect transistor is in a cut-off state; the first field effect transistor is in a cut-off state, and the second field effect transistor is in a conducting state.

5. The circuit of claim 4, wherein the combining circuit module further comprises: the first combining controller and the second combining controller; the first combining controller is connected with the exciting end of the first field effect transistor, and the second combining controller is connected with the exciting end of the second field effect transistor;

the control module is further configured to control the first combining controller to output a first excitation voltage, where the first excitation voltage is used to control the first field-effect transistor to be in a conducting state; and controlling the second combiner controller to output a second excitation voltage, wherein the second excitation voltage is used for controlling the second field effect transistor to be in a conducting state.

6. The circuit of claim 4 or 5, wherein the control module is further configured to:

if the diagnosis result of the combiner circuit module is normal, controlling the first field effect transistor and the second field effect transistor to be in a conducting state so as to control the combiner circuit module to supply power to the load circuit;

and if the diagnosis result of the combiner circuit module is abnormal, outputting an alarm signal.

7. The circuit according to any one of claims 1 to 6, wherein the power of the control module is equal to or less than a preset threshold, and the power of the load circuit is equal to or greater than the preset threshold.

8. The method for diagnosing the power supply combining circuit is characterized by being applied to a power supply combining circuit system, wherein the power supply combining circuit system comprises the power supply combining circuit; the power supply combining circuit comprises a combining circuit module and a control module; the combiner circuit module comprises a first power supply, a first field effect transistor, a second power supply and a second field effect transistor; the first power supply is connected with the input end of the first field effect transistor, the second power supply is connected with the input end of the second field effect transistor, and the output end of the first field effect transistor and the output end of the second field effect transistor are both connected with a power supply port of a load circuit; the control module is used for controlling the combiner circuit module to supply power to the load circuit, and the method is executed by the control module and comprises the following steps:

acquiring a first input voltage, a second input voltage and a third input voltage, wherein the first input voltage is an input side voltage of the first field effect transistor, the second input voltage is an input side voltage of the second field effect transistor, and the third input voltage is a voltage of a power supply terminal of the load circuit;

diagnosing whether the combiner circuit module is abnormal based on the acquired voltage.

9. The method of claim 8, wherein diagnosing whether the combining circuit module is abnormal based on the acquired voltage comprises:

diagnosing whether the combiner circuit module is abnormal or not based on the acquired voltage and preset parameters;

wherein the preset parameters include at least one of: the maximum voltage drop value of the second field effect transistor is calculated based on the maximum current of the load circuit, or the maximum voltage drop value of the second field effect transistor is calculated based on the maximum current of the load circuit.

10. The method of claim 8 or 9, wherein the power combining circuit further comprises a sampling module; the sampling module is respectively connected with the input end of the first field effect transistor, the input end of the second field effect transistor and the power supply input end of the load circuit; the sampling module is used for collecting the first input voltage, the second input voltage and the third input voltage;

the obtaining a first input voltage, a second input voltage, and a third input voltage includes:

and acquiring the first input voltage, the second input voltage and the third input voltage acquired by the sampling module.

11. The method of claim 10, further comprising:

controlling the states of the first field effect transistor and the second field effect transistor, wherein the states comprise a conducting state and a cut-off state;

the obtaining the first input voltage, the second input voltage, and the third input voltage collected by the sampling module includes:

acquiring the first input voltage, the second input voltage and the third input voltage of the first field effect transistor and the second field effect transistor which are acquired by the sampling module under a target state combination;

wherein the target state combination comprises any one of: the first field effect transistor and the second field effect transistor are both in a conducting state; the first field effect transistor and the second field effect transistor are both in a cut-off state; the first field effect transistor is in a conducting state, and the second field effect transistor is in a cut-off state; the first field effect transistor is in a cut-off state, and the second field effect transistor is in a conducting state.

12. The method of claim 11, wherein the combining circuit module further comprises a first combining controller and a second combining controller, the first combining controller is connected to the driving terminal of the first fet, and the second combining controller is connected to the driving terminal of the second fet;

the controlling the state of the first field effect transistor and the second field effect transistor comprises:

controlling the first combiner controller to output a first excitation voltage, wherein the first excitation voltage is used for controlling the first field effect transistor to be in a conducting state;

and controlling the second combiner controller to output a second excitation voltage, wherein the second excitation voltage is used for controlling the second field effect transistor to be in a conducting state.

13. The method according to claim 11 or 12, characterized in that the method further comprises:

if the diagnosis result of the combiner circuit module is normal, controlling the first field effect transistor and the second field effect transistor to be in a conducting state so as to control the combiner circuit module to supply power to the load circuit;

and if the diagnosis result of the combiner circuit module is abnormal, outputting an alarm signal.

14. The method according to any one of claims 8 to 13, wherein the power of the control module is equal to or less than a preset threshold value, and the power of the load circuit is equal to or greater than the preset threshold value.

15. A power combining circuitry, comprising the power combining circuitry of any of claims 1-7, for powering a load circuit.

Technical Field

The present disclosure relates to the field of power supply technologies, and in particular, to a power supply combining circuit, a diagnostic method, a diagnostic device, and a diagnostic system.

Background

To ensure reliable power utilization of circuitry, such as Electronic Control Units (ECUs) having various functions, a two-way power supply is typically used to power the circuitry. In order to realize the power supply of the two-way power supply, the power supply combining circuit is produced.

The conventional power combining circuit is generally used for supplying power to a low-voltage circuit system with lower power, and a failure (such as a short circuit or an open circuit) device in the power combining circuit cannot be diagnosed, so that the safety of the low-voltage circuit system is reduced.

Disclosure of Invention

The application provides a power supply combining circuit, a diagnosis method, a diagnosis device and a diagnosis system, which can be used for diagnosing a failure device in the power supply combining circuit, so that the safety of a load circuit system is improved.

In a first aspect, the present application provides a power supply combining circuit, which is applied to a power supply combining circuit system, and includes a combining circuit module and a control module. The combiner circuit module comprises a first power supply, a first field effect transistor, a second power supply and a second field effect transistor; the first power supply is connected with the input end of the first field effect transistor, the second power supply is connected with the input end of the second field effect transistor, and the output end of the first field effect transistor and the output end of the second field effect transistor are both connected with the power supply input end of the load circuit. And the control module is used for controlling the combiner circuit module to supply power to the load circuit and acquiring a first input voltage, a second input voltage and a third input voltage. The control module is also used for diagnosing whether the combiner circuit module is abnormal or not based on the acquired voltage. The first input voltage is the input side voltage of the first field effect transistor, the second input voltage is the input side voltage of the second field effect transistor, and the third input voltage is the voltage of the power supply input end of the load circuit.

By adopting the power supply combining circuit, the power supply combining circuit can be diagnosed before the power supply combining circuit supplies power to the load circuit, so that the use safety of the load circuit is improved. In addition, the power supply combining circuit takes a field effect transistor as a key device. Since the fet has a very low voltage drop (millivolt level) when it is turned on, the fet does not generate excessive heat loss even when the current flowing through the fet is large. That is, the power supply combining circuit can provide a plurality of paths (e.g., two paths) of power supply for the low-voltage load circuit with higher power.

In a possible design, the control module is further configured to diagnose whether the combiner circuit module is abnormal based on the acquired voltage and a preset parameter. Wherein the preset parameters include at least one of the following: the maximum voltage drop value of the second field effect transistor is calculated based on the maximum current of the load circuit, or the maximum voltage drop value of the second field effect transistor is calculated based on the maximum current of the load circuit.

And diagnosing the power supply combining circuit based on the acquired first input voltage, second input voltage, third input voltage and preset parameters.

In another possible design, the power combining circuit further includes: and a sampling module. The sampling module is respectively connected with the input end of the first field effect transistor, the input end of the second field effect transistor and the power supply input end of the load circuit. The sampling module is used for collecting a first input voltage, a second input voltage and a third input voltage. The control module is further configured to obtain a first input voltage, a second input voltage, and a third input voltage collected by the sampling module. Therefore, the power supply combining circuit can be diagnosed by collecting the first input voltage, the second input voltage and the third input voltage.

In another possible design, the control module is further configured to control states of the first fet and the second fet; the states include an on state and an off state. The control module is further configured to obtain a first input voltage, a second input voltage, and a third input voltage of the first field effect transistor and the second field effect collected by the sampling module in a target state combination. Wherein the target state combination comprises any one of: the first field effect transistor and the second field effect transistor are both in a conducting state; the first field effect transistor and the second field effect transistor are both in a cut-off state; the first field effect transistor is in a conducting state, and the second field effect transistor is in a cut-off state; the first field effect transistor is in a cut-off state, and the second field effect transistor is in a conducting state.

The control module detects a first input voltage, a second input voltage and a third input voltage through a first field effect transistor corresponding to a first power supply and a second field effect transistor corresponding to a second power supply under different state combinations, and diagnoses the failure of devices in the combiner circuit module by determining whether the values of the first input voltage, the second input voltage and the third input voltage are within a theoretical range under each state combination.

In another possible design, the combiner circuit module further includes: the first combination controller and the second combination controller. The first combining controller is connected with the exciting end of the first field effect transistor, and the second combining controller is connected with the exciting end of the second field effect transistor. The control module is further configured to control the first combining controller to output a first excitation voltage, where the first excitation voltage is used to control the first field-effect transistor to be in a conducting state. The control module is further configured to control the second combiner controller to output a second excitation voltage, where the second excitation voltage is used to control the second field effect transistor to be in a conducting state.

In another possible design, the control module is further configured to: if the diagnosis result of the combiner circuit module is normal, controlling the first field effect tube and the second field effect tube to be in a conducting state so as to control the combiner circuit module to supply power to the load circuit; and if the diagnosis result of the combiner circuit module is abnormal, outputting an alarm signal. Through the possible design mode, when the abnormality of the device in the power supply combining circuit is diagnosed, an alarm signal can be output to prompt a user to stop electrifying the load circuit, so that the load circuit is ensured not to have a fault due to the abnormality of the power supply combining circuit in the power supply process, and the use safety of the load circuit is improved.

In another possible design, the power of the control module is less than or equal to a preset threshold, and the power of the load circuit is greater than or equal to the preset threshold.

In a second aspect, the present application provides a method for diagnosing a power combining circuit, which is applied to a power combining circuit system. The power supply combining circuit system comprises a power supply combining circuit. The power supply combining circuit comprises a combining circuit module and a control module. The combiner circuit module comprises a first power supply, a first field effect transistor, a second power supply and a second field effect transistor. Here, the first power supply is connected to an input terminal of the first fet, the second power supply is connected to an input terminal of the second fet, and both an output terminal of the first fet and an output terminal of the second fet are connected to a power supply port of the load circuit. The control module is used for controlling the combiner circuit module to supply power to the load circuit, and the method is executed by the control module and comprises the following steps: acquiring a first input voltage, a second input voltage and a third input voltage, wherein the first input voltage is an input side voltage of a first field effect transistor, the second input voltage is an input side voltage of a second field effect transistor, and the third input voltage is a voltage of a power supply end of a load circuit; and diagnosing whether the combiner circuit module is abnormal or not based on the acquired voltage.

In one possible design, the "diagnosing whether the combiner circuit module is abnormal based on the acquired voltage" includes: and diagnosing whether the combiner circuit module is abnormal or not based on the acquired voltage and preset parameters. Wherein the preset parameters include at least one of the following: the maximum voltage drop value of the second field effect transistor is calculated based on the maximum current of the load circuit, or the maximum voltage drop value of the second field effect transistor is calculated based on the maximum current of the load circuit.

In another possible design, the power combining circuit further includes a sampling module. The sampling module is respectively connected with the input end of the first field effect transistor, the input end of the second field effect transistor and the power supply input end of the load circuit. The sampling module is used for collecting a first input voltage, a second input voltage and a third input voltage. The "obtaining the first input voltage, the second input voltage, and the third input voltage" includes: and acquiring the first input voltage, the second input voltage and the third input voltage acquired by the sampling module.

In another possible design, the method further includes: and controlling the states of the first field effect transistor and the second field effect transistor, wherein the states comprise a conducting state and a cut-off state. The "acquiring the first input voltage, the second input voltage and the third input voltage collected by the sampling module" includes: and acquiring a first input voltage, a second input voltage and a third input voltage of the first field effect transistor and the second field effect transistor which are acquired by the sampling module under the target state combination. Wherein the target state combination comprises any one of: the first field effect transistor and the second field effect transistor are both in a conducting state; the first field effect transistor and the second field effect transistor are both in a cut-off state; the first field effect transistor is in a conducting state, and the second field effect transistor is in a cut-off state; the first field effect transistor is in a cut-off state, and the second field effect transistor is in a conducting state.

In another possible design manner, the combiner circuit module further includes a first combiner controller and a second combiner controller, the first combiner controller is connected to the excitation end of the first field-effect transistor, and the second combiner controller is connected to the excitation end of the second field-effect transistor. The above-mentioned "controlling the states of the first field effect transistor and the second field effect" includes: controlling the first combiner controller to output a first excitation voltage, wherein the first excitation voltage is used for controlling the first field effect transistor to be in a conducting state; and controlling the second combiner controller to output a second excitation voltage, wherein the second excitation voltage is used for controlling the second field effect transistor to be in a conducting state.

In another possible design, the method further includes: and if the diagnosis result of the combiner circuit module is normal, controlling the first field effect tube and the second field effect tube to be in a conducting state so as to control the combiner circuit module to supply power to the load circuit. And if the diagnosis result of the combiner circuit module is abnormal, outputting an alarm signal.

In another possible design, the power of the control module is less than or equal to a preset threshold, and the power of the load circuit is greater than or equal to the preset threshold.

It is understood that the beneficial effects of the second aspect and any one of the possible technical solutions thereof can be described by referring to the technical solutions provided by the first aspect or the corresponding possible designs thereof, which are not described herein again.

In a third aspect, an embodiment of the present application provides a diagnostic apparatus for a power combining circuit, where the diagnostic apparatus is applied to a power combining circuit in a power combining circuit system.

In one possible design, the diagnostic device is configured to perform any one of the methods provided by any one of the possible designs of the second aspect and the second aspect. The present application may divide the functional blocks of the diagnostic device according to any one of the methods provided by the second aspect. For example, the functional blocks may be divided for the respective functions, or two or more functions may be integrated into one processing block. For example, the present application may divide the diagnostic apparatus into an acquisition unit, a diagnostic unit, a control unit, and the like according to functions. The above description of possible technical solutions and beneficial effects executed by each divided functional module can refer to the technical solution provided by the second aspect or its corresponding possible design, and will not be described herein again.

In another possible design, the diagnostic device includes: the memory is coupled to the one or more processors. The memory is for storing computer instructions that the processor is adapted to invoke in order to perform any of the methods as provided by the second aspect and any of its possible designs.

In a fourth aspect, the present application provides a power combining circuit system, which includes a load circuit and the power combining circuit provided in the first aspect and any possible design manner thereof, wherein the power combining circuit is configured to supply power to the load circuit.

In a fifth aspect, the present application provides a computer-readable storage medium, such as a computer non-transitory readable storage medium. A computer program (or instructions) is stored thereon, which, when run on a diagnostic apparatus of a power combining circuit, causes the diagnostic apparatus to perform any of the methods provided by any of the possible implementations of the second aspect.

In a sixth aspect, a computer program product is provided that, when run on a diagnostic apparatus of a power combining circuit, causes any of the methods provided by any of the possible implementations of the second aspect to be performed.

In a seventh aspect, a chip system is provided, including: and the processor is used for calling and running the computer program stored in the memory from the memory and executing any method provided by the implementation mode in the second aspect.

It is understood that any one of the methods, apparatuses, computer storage media, computer program products, or chip systems provided above can be applied to the corresponding methods provided above, and therefore, the beneficial effects achieved by the methods can refer to the beneficial effects in the corresponding methods, and are not described herein again.

The present application can further combine to provide more implementations on the basis of the implementations provided by the above aspects.

Drawings

Fig. 1 is a schematic diagram of a power supply combining circuit provided in an embodiment of the present application;

fig. 2 is a schematic diagram of another power combining circuit provided in an embodiment of the present application;

fig. 3 is a schematic diagram of a power combining circuit system according to an embodiment of the present disclosure;

fig. 4 is a schematic diagram of another power combining circuit system provided in an embodiment of the present application;

fig. 5 is a schematic diagram of a combining circuit module according to an embodiment of the present disclosure;

fig. 6 is a schematic diagram of another combining circuit module according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of a control module according to an embodiment of the present disclosure;

fig. 8 is a schematic diagram of another power combining circuit system provided in an embodiment of the present application;

fig. 9 is a schematic flowchart of a diagnostic method for a power combining circuit according to an embodiment of the present disclosure;

fig. 10 is a schematic structural diagram of a diagnostic apparatus of a power combining circuit according to an embodiment of the present application.

Detailed Description

The embodiment of the application provides a power supply combining circuit and a system, and solves the problem of high heat loss of the power supply combining circuit when at least two paths of power supplies are provided for a load circuit with high power. Meanwhile, the application also provides a power supply combining circuit diagnosis method and device, and the method is applied to a power supply combining circuit system. The method can diagnose the failure device in the power supply combining circuit when the power supply combining circuit system is powered on, and alarm the user when the diagnosis result is abnormal.

The load circuit may be a circuit system having any function, and may be, for example, an ECU (electronic control unit) that implements multiple functions, such as a Vehicle Control Unit (VCU), an Electronic Stability Program (ESP), an Advanced Driving Assistance System (ADAS), and the like in an electric vehicle control system. Here, VCU and ESP are ECUs with lower power (e.g., power below 100W), and ADAS with higher autopilot level (e.g., level 3(level 3) or levels above L4(level 4)) are ECUs with higher power (e.g., power above 100W).

In the following description, the embodiments of the present application take a power combining circuit as an example to provide two-way power supply for a load circuit.

Referring to fig. 1, fig. 1 illustrates a power combining circuit 10 provided in an embodiment of the present application. The power supply combining circuit 10 is configured to combine two power supplies (e.g., the power supply 1 and the power supply 2) into one power supply (i.e., a combined power supply) to supply power to the load circuit 14. The power supply combining circuit 10 includes a combining circuit module 11, a control module 12 and a sampling module 13.

The combiner circuit module 11 is configured to provide a combiner circuit of two power supplies. And the control module 12 is configured to diagnose the circuit combining circuit module 11 when the power supply combining circuit system is powered on, and control the combining circuit module 11 to provide two-way power supply for the load circuit when the diagnosis result is normal. The control module 12 may be implemented by a Micro Controller Unit (MCU), or may be implemented by an ECU having some function, which is not limited thereto. The sampling module 13 is configured to collect a voltage at an input side of the combining circuit module 11 and an input voltage of the load circuit, so that the control module 12 may diagnose the combining circuit module 11 according to the collected voltage.

It should be noted that the sampling module 13 and the control module 12 may exist independently or may be integrated together, and this is not limited thereto. For simplicity of description, the embodiment of the present application is illustrated by taking the control module 12 and the sampling module 13 as an example. It will be appreciated that the control module 12 described hereinafter includes a sampling module 13.

It should be noted that the control module 12 needs to be separately powered to ensure its normal operation. In order to improve the reliability of power supply, a two-way combined power supply 15 controlled by diodes (e.g., D1 and D2) as shown in fig. 2 may be generally used to supply power to the control module 12. As shown in fig. 2, the power supply 1 is connected to the diode D1, the power supply 2 is connected to the diode D2, and the diodes D1 and D2 are simultaneously connected to the power input terminal of the control module 12, so as to provide a two-way combination power supply for the control module 12.

The power supply 1 and the power supply 2 shown in fig. 2 are respectively the power supply 1 and the power supply 2 connected to the combiner circuit module 11 in fig. 1. The diode-controlled two-way combined power supply 15 cannot afford a low-voltage (e.g., less than 48V (volts)) load circuit of higher power (e.g., power greater than 100W (watts)) due to the inherent voltage drop of the diodes themselves. That is, the MCU or ECU implementing the functions of the control module 12 is typically a lower power MCU or ECU. For example, the ECU may be the VCU described above. The power supply combining circuit 10 shown in fig. 1 provided in the embodiment of the present application may provide two power supplies for a low-voltage load circuit with a higher power, which is described in detail below and is not described herein again.

The embodiment of the present application further provides a power supply combining circuit system, and the power supply combining circuit 10 may be applied to the power supply combining circuit system. The power combining circuitry also includes a load circuit 14. The power supply combining circuit 10 is configured to provide two-way power supply for the load circuit.

In one possible implementation, referring to fig. 1, the power combining circuit 10 may be implemented as a stand-alone electronic unit to provide two-way power supply for any one of the load circuits 14. For example, the load circuit 14 may be an ECU having any function in the electric vehicle described above. In this case, the control module 12 in the power combining circuit 10 may be a separate MCU.

In another possible implementation manner, the combining circuit module 11 and the control module 12 in the power combining circuit 10 may be integrated in different circuit systems, respectively, and provide two-way power supply for the circuit system of the integrated combining circuit module 11. For example, the different circuitry may be different ECUs. As shown in fig. 3, the combining circuit module 11 may be integrated in the ECU 1, and the control module 12 may be integrated in the ECU 2. The control module 12 in the ECU 2 controls the combining circuit module 11 in the ECU 1, so as to provide two-way power supply for the load circuit (corresponding to the load circuit 14) of the ECU 1. The ECU 1 may be the ADAS described above, and the ECU 2 may be the VCU described above, but the present invention is not limited thereto.

In yet another possible implementation manner, the combining circuit module 11 and the control module 12 in the power combining circuit 10 may also be integrated into the same circuit system, and provide two power supplies for the circuit system. For example, the circuitry may be an ECU. As shown in fig. 4, the combining circuit module 11 and the control module 12 may be integrated in the ECU 3, and serve as a power circuit of a load circuit (corresponding to the load circuit 14) of the ECU 3, so as to provide two-way power supply for the load circuit. In this case, the control module 12 may implement its functions by an MCU integrated in the ECU 3.

The combining circuit module 11 and the control module 12 in the power combining circuit 10 shown in fig. 1 will be described in detail below.

Referring to fig. 5, fig. 5 illustrates a combining circuit module 11 provided in an embodiment of the present application. The combining circuit module 11 includes a field effect transistor Q1, a combining controller U1, a field effect transistor Q2, and a combining controller U2. Wherein, Q1 and Q2 are both field effect transistors with N channels. Q1 corresponds to the coupling controller U1, and Q2 corresponds to the coupling controller U2.

Q1 includes two states, on and off. When Q1 is in the on state, the internal resistance of Q1 is small (e.g., in milliohms). In this way, Q1 does not generate excessive heat even if the current through Q1 is large. As such, the load circuit to which Q1 is connected may be a high power, low voltage load circuit. When Q1 is in the off state, Q1 does not conduct current. Similarly, Q2 also includes on and off states, and the description of Q2 can refer to the description of Q1 and will not be repeated.

It should be noted that, in the power combining circuit 10, Q1 and Q2 may be both P-channel fets, or one of Q1 and Q2 may be an N-channel fet and the other may be a P-channel fet, which is not limited in this embodiment of the present application. In fig. 5, only field-effect transistors in which Q1 and Q2 are both N-channels are illustrated as an example.

As shown in fig. 5, a first terminal Q11 (corresponding to the excitation terminal of the first fet in the embodiment of the present application) of Q1 may be connected to an excitation port U11 of the combining controller U1. When the enable terminal U14 of the combining controller U1 is activated, the combining controller U1 is in an operating state. At this time, the combining controller U1 may input the first driving voltage to the first terminal Q11 of the Q1 through the driving port U11 to drive the Q1 in a conductive state. When the enable terminal U14 of the combination controller U1 is turned off, the combination controller U1 is in a non-operating state, and at this time, the Q1 is in a cut-off state. Here, the first terminal Q11 of Q1 may be a gate, and the first driving voltage has a voltage value greater than or equal to a threshold voltage value for Q1 to be in a conducting state. The activation or the shutdown of the enable terminal U14 of the combining controller U1 may be controlled by a control signal sent by the control module 12, and the detailed description may refer to the following description of the control module 12, which is not repeated herein.

Similarly, the first terminal Q21 of Q2 corresponds to the excitation terminal of the second fet in the embodiment of the present application) may be connected to the excitation port U21 of the combining controller U2. When the enable terminal U24 of the combining controller U2 is activated, the combining controller U2 is in an operating state. At this time, the combining controller U2 may input the second driving voltage to the first terminal Q21 of the Q2 through the driving port U21 to drive the Q2 in a conductive state. When the enable terminal U24 of the combination controller U2 is turned off, the combination controller U2 is in a non-operating state, and at this time, the Q2 is in a cut-off state. The first terminal Q21 of Q2 may be a gate, and the second driving voltage is required to have a voltage value greater than or equal to a threshold voltage value for Q2 to be in a conducting state. The activation or the shutdown of the enable terminal U24 of the combining controller U2 may be controlled by a control signal sent by the control module 12, and the detailed description may refer to the following description of the control module 12, which is not repeated herein.

Referring to fig. 5, a second terminal Q12 (corresponding to an input terminal of the first fet in the embodiment of the present application) of Q1 may be connected to the power supply 1, and a second terminal Q12 of Q1 may be a source. It is understood that a voltage regulator or a fuse (not shown in fig. 5) may be further included between the second end Q12 of the Q1 and the power supply 1.

Similarly, a second terminal Q22 (corresponding to the input terminal of the second fet in the embodiment of the present application) of Q2 may be connected to the power supply 2, and a second terminal Q22 of Q2 may be a source. It is understood that a voltage regulator or a fuse (not shown in fig. 5) may be further included between the second end Q22 of the Q2 and the power supply 2.

It should be noted that, if Q1 and Q2 are both P-channel fets, the second terminal Q12 of Q1 and the second terminal Q22 of Q2 may be drains. At this time, the drain of Q1 is connected to power supply 1, and the drain of Q2 is connected to power supply 2.

As shown in fig. 5, the second terminal Q12 of Q1 may also be connected with the port U12 of the combiner controller U1. That is, the power supply 1 is connected to the port U12 of the combining controller U1. As such, power supply 1 may serve as a power supply for combiner controller U1, thereby placing combiner controller U1 in a powered-up standby state. When the enable terminal U14 of the combining controller U1 is activated, the combining controller U1 may also collect a first input voltage of the second terminal Q12 of Q1 through the port U12, which is the input side voltage of Q1.

As shown in fig. 5, a third terminal Q13 (corresponding to the output terminal of the first fet in the embodiment of the present application) of Q1 may be connected to a port U13 of the combining controller U1. When the enable terminal U14 of the combining controller U1 is activated, the combining controller U1 may collect a first output voltage of the third terminal Q13 of the Q1 through the port U13, which is a voltage of the output side of the Q1. When the Q1 is turned on, if the first input voltage collected by the combination controller U1 is lower than the first output voltage, the combination controller U1 controls the voltage output by the excitation port U11 to be lower than the first excitation voltage, or the combination controller U1 controls the excitation port U11 to stop outputting the voltage, so that the Q1 is in a cut-off state. Thus, the reverse flow of current to the power supply 1 can be prevented.

Similarly, as shown in fig. 5, the second terminal Q22 of Q2 may also be connected to the port U22 of the combiner controller U2. That is, the power supply 2 is connected to the port U22 of the combining controller U2. As such, power supply 2 may be the power supply for combiner controller U2, thereby placing combiner controller U2 in a powered-up standby state. When the enable terminal U24 of the combining controller U2 is activated, the combining controller U2 may also collect a second input voltage of the second terminal Q22 of the Q2 through the port U22, the second input voltage being an input side voltage of the Q2.

A third terminal Q23 (corresponding to the output terminal of the second fet in the embodiment of the present application) of Q2 may be connected to a port U23 of the combining controller U2. When the enable terminal U24 of the combining controller U2 is activated, the combining controller U2 may collect a second output voltage of the third terminal Q23 of the Q2 through the port U23, which is a voltage of the output side of the Q2. When the Q2 is turned on, if the second input voltage collected by the combination controller U2 is lower than the second output voltage, the combination controller U2 controls the voltage output by the excitation port U21 to be lower than the second excitation voltage, or the combination controller U2 controls the excitation port U21 to stop outputting the voltage, so that the Q2 is in an off state. In this way, the current can be prevented from flowing backward to the power supply 2.

As shown in fig. 5, the third terminal Q13 of Q1 and the third terminal Q23 of Q2 may both be connected to a load circuit (not shown in fig. 5) to serve as a combined power source for supplying power to the load circuit. Wherein, the third end Q13 of Q1 and the third end Q23 of Q2 are both drains.

It can be understood that, when Q1 and Q2 are both P-channel fets, the third terminal Q13 of Q1 and the third terminal Q23 of Q2 may both be sources, that is, the source of Q1 and the source of Q2 are respectively connected to the load circuit to serve as a combined power supply to supply power to the load circuit.

When Q1 is an N-channel FET, the third terminal Q13 of Q1 is the drain. When Q2 is a P-channel FET, the third terminal Q23 of Q2 is the source. In this case, the drain of Q1 and the source of Q2 are connected to the load circuit, respectively, to provide power to the load circuit as a combined power supply.

When Q1 is a P-channel FET, the third terminal Q13 of Q1 is the source. When Q2 is an N-channel FET, the third terminal Q23 of Q2 is the drain. In this case, the source of Q1 and the drain of Q2 are connected to the load circuit, respectively, to provide power to the load circuit as a combined power supply.

It can be seen that in the power combining circuit, the field effect transistor (for example, Q1 or Q2) needs to ensure that the anode of the internal body diode (D shown in fig. 5) of the field effect transistor is connected with the power. That is, when the fet is turned on, the current in the fet flows from the anode to the cathode of the internal body diode D.

Alternatively, referring to fig. 6, fig. 6 shows another combining circuit module 11 provided in the embodiment of the present application, and the difference from the combining circuit module shown in fig. 5 is that only one combining controller is provided in fig. 6. Q1 and Q2 in the combiner circuit module 11 are both N-channel field effect transistors. And, Q1 and Q2 share a combiner controller U1.

The interconnection among Q1, the power supply 1, and the combining controller U1 may refer to the description of the interconnection among Q1, the power supply 1, and the combining controller U1 in the combining circuit module 11 in fig. 5, and the interconnection among Q2, the power supply 2, and the combining controller U1 may refer to the description of the interconnection among Q2, the power supply 2, and the combining controller U2 in the combining circuit module 11 in fig. 5, which is not described herein again.

In the combination controller U1, the excitation port U11, the port U12, the port U13, and the enable port U14 connected to the Q1 are used as a first port group for controlling on/off of the Q1. The excitation port U15, the port U16, the port U17 and the enable port U18 of the combination controller U1, which are connected to the Q2, are used as a second port group for controlling the on/off of the Q2.

Referring to fig. 7, fig. 7 shows a schematic structural diagram of a control module 12 according to an embodiment of the present application. In the embodiment of the present application, the control module 12 includes the sampling module 13 as an example. The control module 12 is used for controlling the combiner circuit module 11 to provide two-way power supply for the load circuit. The control module 12 may be an MCU or ECU, but is not limited thereto.

The control module 12 may include a processor 71, an analog-to-digital converter (ADC) 72 (corresponding to the sampling module in the embodiment of the present application), and an input-output interface 73. Optionally, the control module 12 may also include a memory 74. The ADC 72 (corresponding to the sampling module in the embodiment of the present application), the input/output interface 73, and the memory 74 may be respectively connected to and communicate with the processor 71.

The processor 71 is a control center of the control module 12, and may be a general-purpose Central Processing Unit (CPU), or other general-purpose processor, a Digital Signal Processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, or the like. Wherein a general purpose processor may be a microprocessor or any conventional processor or the like.

By way of example, processor 71 may include one or more CPUs, such as CPU 0 and CPU 1 shown in FIG. 7.

And the ADC 72 is configured to acquire a first input voltage of the Q1, a second input voltage of the Q2, and a third input voltage of the load circuit in the combining circuit module 11. The ADC 72 also sends the collected first, second and third input voltages to the processor 71 for diagnostic analysis. Wherein the first input voltage is the input side voltage of Q1, the second input voltage is the input side voltage of Q2, and the third input voltage is the input voltage of the load circuit, i.e. the voltage at the power supply input of the load circuit.

The number of ADCs 72 is related to the number of power supplies that need to be combined by combining circuit block 11. If the number of power supplies to be combined by the combining circuit module 11 is m, the number of ADCs 72 is m + 1. Wherein m is an integer greater than or equal to 1.

For example, as shown in fig. 8, in the power supply combining circuit system shown in fig. 8, the combining circuit module 11 includes two power supplies (power supply 1 and power supply 2) that need to be combined, and therefore, the control module 12 may include 3 ADCs 72(ADC 72_1, ADC 72_2, ADC 72_ 3). Specifically, the ADC 72_1 may be connected to the second terminal Q12 of the Q1 through the port 121 and capture the first input voltage VA of the second terminal Q12 of the Q1. The ADC 72_2 may be connected to the second terminal Q22 of the Q2 through the port 122 and collect the second input voltage VB of the second terminal Q22 of the Q2. The ADC 72_3 may be connected to the power input 141 of the load circuit 14 via the port 123 and collect a third input voltage VC at the power input 141 of the load circuit 14.

The input/output interface 73 may be a general-purpose input/output (GPIO) interface. The input/output interface 73 is configured to send a control signal to the combining circuit module 11, so as to activate or deactivate an enable terminal of a combining controller in the combining circuit module 11. Furthermore, when the enable terminal of the combining controller in the combining circuit module 11 is activated, the combining controller is in a working state, so that the combining controller can input an excitation voltage to the field-effect tube through the excitation port to enable the field-effect tube to be in a conducting state; or, when the enable terminal of the combining controller in the combining circuit module 11 is turned off, the combining controller is in a non-operating state, so that the fet cannot receive the excitation voltage input by the combining controller through the excitation port, that is, is in a cut-off state.

The control signal may be a level signal, and the control signal may include at least one of a high level signal and a low level signal. For example, the input/output interface 73 may send a high level signal to an enable terminal of the combining controller to activate the combining controller, and the input/output interface 73 may send a low level signal to an enable terminal of the combining controller to deactivate the combining controller. Alternatively, the input/output interface 73 may send a low level signal to an enable terminal of the combining controller to activate the combining controller, and the input/output interface 73 may send a high level signal to an enable terminal of the combining controller to deactivate the combining controller. The embodiments of the present application do not limit this.

The number of the input/output interfaces 73 is the same as the number of the power supplies to be combined by the combining circuit module 11. If the number of power supplies to be combined by the combining circuit module 11 is m, the number of the input/output interfaces 73 is m.

For example, as shown in fig. 8, the combining circuit module 11 includes two power supplies (power supply 1 and power supply 2) that need to be combined, and therefore, the control module 12 may include 2 input/output interfaces 73 (port 124 and port 125). The port 124 of the control module 12 is connected to the enable terminal U14 of the combining controller U1, and may send a control signal to the enable terminal U14 of the combining controller U1 according to the instruction of the processor 71. This control signal may be used to activate the combining controller U1, thereby placing Q1 in a conductive state. Alternatively, the control signal may be used to turn off the combining controller U1, thereby turning off the Q1. Here, the control signal may include at least one of a high level or a low level, which is not limited thereto.

Similarly, the port 125 of the control module 12 is connected to the enable terminal U24 of the combining controller U2, and may send a control signal to the enable terminal U24 of the combining controller U2 according to an instruction of the processor 71. This control signal may be used to activate the combining controller U2, thereby placing Q2 in a conductive state. Alternatively, the control signal may be used to turn off the combining controller U2, thereby turning off the Q2.

It should be noted that the ADC 72 and the input/output interface 73 may be integrated with the processor 71. In this case, the device integrating the ADC 72, the input-output interface 73, and the processor 71 may be referred to as an MCU.

The memory 74 may be, but is not limited to, a read-only memory (ROM) or other type of static storage device that may store static information and instructions, a Random Access Memory (RAM) or other type of dynamic storage device that may store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.

In one possible implementation, the memory 74 may exist independently of the processor 71. The memory 74 may be coupled to the processor 71 via a bus for storing data, instructions or program code. When the processor 71 calls and executes the instructions or program codes stored in the memory 74, the diagnostic method of the power supply combining circuit provided by the embodiment of the present application can be implemented.

In another possible implementation, the memory 74 may also be integrated with the processor 71.

It should be noted that the configuration shown in fig. 7 does not constitute a limitation of the control module 12, and that the control module 12 may include more or less components than those shown, or some components may be combined, or a different arrangement of components than those shown in fig. 7.

So far, the control module 12 in the power supply combining circuit 10 described above controls the conduction of the fet in the combining circuit module 11, so as to combine the power supply 1 and the power supply 2 into one power supply and supply power to the load circuit.

Before the power combining circuit 10 supplies power to the load circuit, the embodiment of the present application further provides a power combining circuit diagnosis method. The diagnosis method is used for diagnosing the failure device in the power supply combining circuit 10 and alarming to a user after the failure is diagnosed.

The following describes a diagnosis method of a power supply combining circuit provided by the embodiment of the invention with reference to the accompanying drawings.

Referring to fig. 9, fig. 9 is a schematic flowchart illustrating a power combining circuit diagnosis method according to an embodiment of the present application. The method is applied to the power supply combining circuit system shown in fig. 8, and may include the following steps:

s101, the control module 12 sends a control signal to the combining circuit module 11 to control and obtain a state combination of the field effect transistors in the combining circuit module 11.

Specifically, the control module 12 may send the first group of control signals, the second group of control signals, the third group of control signals, and the fourth group of control signals to the combining circuit module 11 through the input/output interface after the power supply combining circuit system shown in fig. 8 is powered on. Here, the first group control signal, the second group control signal, the third group control signal, and the fourth group control signal are four groups of control signals that the control module 12 transmits to the combining circuit module 11 at different timings, respectively. And, each of the first, second, third and fourth sets of control signals includes a first signal and a second signal. The first signal is used to control an enable terminal of the combining controller U1 in the combining circuit module 11, and the second signal is used to control an enable terminal of the combining controller U2 in the combining circuit module 11.

Specifically, a first signal in the first group of control signals may be used to activate an enable terminal of the combining controller U1 in the combining circuit module 11, so that the combining controller U1 is in an operating state. A second signal of the first set of control signals may be used to activate the enable terminals of the combining controllers U2 to place each of the combining controllers U2 in an active state. In this way, the combining controller U1 may control the Q1 to be in a conducting state, and the combining controller U2 may control the Q2 to be in a conducting state.

A first signal of the second set of control signals may be used to activate an enable terminal of the combining controller U1 in the combining circuit module 11, so that the combining controller U1 is in an operating state. A second signal of the second set of control signals may be used to turn off the enable terminal of the combining controller U2 in the combining circuit module 11, so that the combining controller U2 is in a non-operating state. In this way, the combining controller U1 may control the Q1 to be in an on state, and the combining controller U2 may control the Q2 to be in an off state.

The first signal of the third set of control signals may be used to activate the enable terminal of the combining controller U2 in the combining circuit module 11, so that the combining controller U2 is in an operating state. At this time, the second signal of the third set of control signals may be used to turn off the enable terminal of the combining controller U1 in the combining circuit module 11, so that the combining controller U1 is in a non-operating state. In this way, the combining controller U2 may control the Q2 to be in an on state, and the combining controller U1 may control the Q1 to be in an off state.

A first signal of the fourth set of control signals may be used to turn off the enable terminal of the combining controller U1 in the combining circuit module 11, so that the combining controller U1 is in a non-operating state. The second signal of the fourth set of control signals may be used to turn off the enable terminal of the combining controller U2 in the combining circuit module 11, so that the combining controller U2 is in a non-operating state. In this way, the combining controller U1 may control the Q1 to be in an off state, and the combining controller U2 may control the Q2 to be in an off state.

That is, the first set of control signals may control the combination of the first states of the fets in the combiner circuit block 11: that is, Q1 and Q2 are both in the on state. The second group of control signals may control to obtain a second state combination of the fets in the combiner circuit module 11: that is, Q1 is on state and Q2 is off state. The third group of control signals may control to obtain a third state combination of the field effect transistors in the combiner circuit module 11: that is, Q1 is off, and Q2 is on. The fourth group of control signals may control to obtain a fourth state combination of the fets in the combiner circuit module 11: namely, Q1 and Q2 are both off.

It should be noted that, in the embodiment of the present application, the timing for the control module 12 to send the first group control signal, the second group control signal, the third group control signal, and the fourth group control signal to the combining circuit module 11 is not limited. For example, the control module 12 may sequentially transmit a first group control signal, a second group control signal, a third group control signal, and a fourth group control signal to the combining circuit module 11. Alternatively, the control module 12 may first send the second set of control signals, and then send the first set of control signals, the third set of control signals, the fourth set of control signals, and so on in sequence.

It can be understood that, in the embodiment of the present application, the timing sequence for controlling the control module 12 to obtain the state combination of the fets in the combiner circuit module 11 is not limited. For example, the control module 12 may sequentially control to obtain the first state combination, the second state combination, the third state combination, and the fourth state combination of the fets in the combiner circuit module 11, and of course, the control module 12 may also control to obtain the second state combination of the fets in the combiner circuit module 11 first, and then sequentially obtain the third state combination, the first state combination, and the fourth state combination, and the like, which is not limited herein.

In response to the operation of the control module 12, the states of the fets in the combining circuit module 11 may be in a first state combination, a second state combination, a third state combination, and a fourth state combination, respectively.

S102, the control module 12 obtains a first input voltage, a second input voltage, and a third input voltage of the field effect transistor in the combiner circuit module 11 under different state combinations.

Specifically, the control module 12 may acquire the first input voltage, the second input voltage, and the third input voltage of the field effect transistor in the combiner circuit module 11 in different state combinations through the sampling module, so as to acquire the first input voltage, the second input voltage, and the third input voltage of the field effect transistor in the combiner circuit module 11 in different state combinations.

Of course, if the control module 12 does not include an adoption module, the sampling module collects the first input voltage, the second input voltage, and the third input voltage of the fet in the combiner circuit module 11 under different state combinations, and sends the collected voltages to the control module 12, so that the control module 12 obtains the first input voltage, the second input voltage, and the third input voltage of the fet in the combiner circuit module 11 under different state combinations.

Referring to fig. 8, the first input voltage may be an input side voltage VA of Q1, the second input voltage may be an input side voltage VB of Q2, and the third input voltage may be an input voltage VC of the load circuit.

Specifically, the control module 12 may respectively acquire, through the ADC, the first input voltage VA1, the second input voltage VB1, and the third input voltage VC1 when the state combination of the fets in the combiner circuit module 11 is the first state combination.

The control module 12 may collect, through the ADC, the first input voltage VA2, the second input voltage VB2, and the third input voltage VC2 when the state combination of the fets in the combiner circuit module 11 is the second state combination.

The control module 12 may collect, through the ADC, the first input voltage VA3, the second input voltage VB3, and the third input voltage VC3 when the state combination of the fets in the combiner circuit module 11 is the third state combination.

The control module 12 may collect, through the ADC, the first input voltage VA4, the second input voltage VB4, and the third input voltage VC4 when the state combination of the fets in the combiner circuit module 11 is the fourth state combination.

S103, the control module 12 diagnoses the combining circuit module 11 based on the first input voltage, the second input voltage, the third input voltage and the preset parameters of the field effect transistors in the combining circuit module 11 under different state combinations.

Wherein, the preset parameters may include: a minimum forward voltage drop value of the internal body diode of Q1 (VQ1_ D _ min), a maximum forward voltage drop value of the internal body diode of Q1 (VQ1_ D _ max), a minimum forward voltage drop value of the internal body diode of Q2 (VQ2_ D _ min), a maximum forward voltage drop value of the internal body diode of Q2 (VQ2_ D _ max), a maximum voltage difference value across Q1 calculated based on the maximum load circuit current and the maximum on-dc internal resistance of Q1 (VQ1_ max), and a maximum voltage difference value of Q2 calculated based on the maximum load circuit current and the maximum on-dc internal resistance of Q2 (VQ2_ max).

Specifically, the control module may diagnose the circuit module 11 according to the diagnosis standard shown in table 1, and obtain a corresponding diagnosis result.

TABLE 1

The contents of table 1 are described below.

When the state combination of the fets in the combining circuit module 11 is the first state combination, i.e. Q1 and Q2 are both in the on state. In this case, VC1 must satisfy: greater than or equal to (VA1-VQ1_ max), and greater than or equal to (VB1-VQ2_ max). That is, when VC1 is equal to or greater than the larger one of (VA1-VQ1_ max) and (VB1-VQ2_ max), it indicates that the combining circuit block 11 is normal. Otherwise, it indicates that the combiner circuit module 11 is abnormal.

When the state combination of the fets in the combiner circuit module 11 is the second state combination, i.e. Q1 is turned on, Q2 is turned off. In this case, since the on internal resistance is small, the voltage difference generated by the internal resistance of Q1 is much lower than the voltage drop generated by the body diode inside Q2. Therefore, when VA2 is smaller than (VB2-VQ2_ D _ max), if VC2 is between (VB2-VQ2_ D _ max) and (VB2-VQ2_ D _ min), it indicates that the combining circuit module 11 is normal; if VC2 is less than (VB2-VQ2_ D _ max), it indicates that Q2 is abnormal, for example, VQ2_ D _ max is too large. When VA2 is greater than or equal to ((VB2-VQ2_ D _ min) + VQ1_ max), if VC2 is greater than or equal to (VA2-VQ1_ max), it indicates that the combining circuit module 11 is normal; otherwise, it indicates Q1 abnormality or U1 abnormality, for example, the on-resistance of Q1 is too large, or the excitation voltage outputted from the excitation terminal of U1 is lower than the first excitation voltage.

When the state combination of the fets in the combiner circuit module 11 is the third state combination, i.e. Q1 is off, Q2 is on. In this case, since the on internal resistance of Q2 is small, the voltage difference generated by the internal resistance of Q2 is much lower than the voltage drop generated by the body diode inside Q1. Therefore, when VB3 is smaller than (VA3-VQ1_ D _ max), if VC3 is between (VA3-VQ1_ D _ max) and (VA3-VQ1_ D _ min), it indicates that the combining circuit module 11 is normal; if VC3 is less than (VA3-VQ1_ D _ max), it indicates that Q1 is abnormal, for example, VQ1_ D _ max is too large. When VB3 is greater than or equal to ((VA3-VQ1_ D _ min) + VQ2_ max), if VC is greater than or equal to (VB3-VQ2_ max), it indicates that the combining circuit module 11 is normal; otherwise, it indicates Q2 abnormality or U2 abnormality, for example, the on-resistance of Q2 is too large, or the excitation voltage outputted from the excitation terminal of U2 is lower than the second excitation voltage.

When the state combination of the fets in the combining circuit module 11 is the fourth state combination, i.e., Q1 and Q2 are both off. In this case, VC4 should be within the normal voltage drop range of the body diode inside Q1, Q2. Therefore, when VC4 is between (VA4-VQ1_ D _ max) and (VA4-VQ1_ D _ min), or VC4 is between (VB4-VQ2_ D _ max) and (VB4-VQ2_ D _ min), it indicates that the combining circuit module 11 is normal. Otherwise, it indicates that the combiner circuit module 11 is abnormal.

For convenience of the following description, the embodiments of the present application will simply refer to "four state combinations of fets in combiner circuit block 11" as "four state combinations".

As can be seen, the control module 12, based on the first input voltage, the second input voltage and the third input voltage acquired under the combination of the four states and according to the diagnosis standard, determines that the diagnosis result obtained after the diagnosis is normal for the combining circuit module 11, which indicates that the combining circuit module 11 is normal. At this time, the control module 12 may continuously control both Q1 and Q2 to be in the on state to achieve normal power supply for the load circuit. When the diagnosis result of at least one of the four state combinations is abnormal, the control module 12 may control both Q1 and Q2 to be in the off state, and send an alarm message to the user interaction module to remind the user that the power supply combining circuit system is abnormal.

The control module 12 may be implemented in any one of the following manners when diagnosing the circuit module 11 based on the first input voltage, the second input voltage, and the third input voltage acquired in the combination of the four states.

In a first possible implementation manner, since the four state combinations are state combinations of the field effect transistor in the combining circuit module 11 at different times, when the control module 12 obtains one state combination of the field effect transistor in the combining circuit module 11, that is, according to the first input voltage, the second input voltage, and the third input voltage collected under the state combination, it may perform a diagnosis on the combining circuit module 11 once, and obtain a diagnosis result. In this way, the control module may perform four diagnoses based on the first input voltage, the second input voltage, and the third input voltage acquired each time, so as to obtain four diagnosis results. Then, the control module 12 determines whether the combining circuit module 11 is normal based on the four diagnosis results.

Optionally, the control module 12 may stop the diagnosis of the combining circuit module 11 when the diagnosis result obtained for the first time is "abnormal", control both Q1 and Q2 to be in a cut-off state, and send an alarm message to the user interaction module to remind the user that the power supply combining circuit system is abnormal. In this way, if the diagnosis result indicating "abnormal" is not the diagnosis result of the fourth diagnosis, the number of times that the control module 12 collects the first input voltage, the second input voltage, and the third input voltage of the combining circuit module 11 is reduced, and the number of times that the combining circuit module 11 is diagnosed is reduced, so that the efficiency of the power combining circuit diagnosis method provided by the embodiment of the present application is improved.

In a second possible implementation manner, the control module 12 may also collect the first input voltage, the second input voltage, and the third input voltage in the combination of the four states, and then diagnose the combining circuit module 11 according to the standard in table 1 to determine whether the combining circuit module 11 is normal.

The control module 12 detects the first input voltage, the second input voltage, and the third input voltage under different state combinations of Q1 corresponding to the first power supply and Q2 corresponding to the second power supply, and diagnoses a device failure in the combining circuit module 11 by determining whether values of the first input voltage, the second input voltage, and the third input voltage are within a theoretical range under each state combination.

In summary, the present application provides a method for diagnosing a power supply combining circuit, which can diagnose the power supply combining circuit before the power supply combining circuit supplies power to a load circuit. When the abnormality of the device in the power supply combining circuit is diagnosed, the power supply for the load circuit can be stopped, so that the load circuit is prevented from being failed due to the abnormality of the power supply combining circuit in the power supply process, and the safety of the load circuit is improved. In addition, the embodiment of the application also provides a power supply combining circuit and a system, wherein the power supply combining circuit takes a field effect transistor as a key device. Since the fet has a very low voltage drop (millivolt level) when it is turned on, the fet does not generate excessive heat loss even when the current flowing through the fet is large. Therefore, the power supply combining circuit provided by the embodiment of the application can provide two or more paths of power supply for the low-voltage load circuit with higher power.

The scheme provided by the embodiment of the application is mainly introduced from the perspective of a method. To implement the above functions, it includes hardware structures and/or software modules for performing the respective functions. Those of skill in the art would readily appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. Whether a function is performed as hardware or computer software drives hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiment of the present application, the functional modules of the diagnostic apparatus of the power combining circuit may be divided according to the above method examples, for example, each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. It should be noted that, in the embodiment of the present application, the division of the module is schematic, and is only one logic function division, and there may be another division manner in actual implementation.

As shown in fig. 10, fig. 10 is a schematic structural diagram of a diagnostic apparatus 100 of a power supply combining circuit provided in the embodiment of the present application. The diagnostic apparatus 100 is applied to a power combining circuit in a power combining circuit system, and the power combining circuit further includes a combining circuit module. The combiner circuit module comprises a first power supply, a first field effect transistor, a second power supply and a second field effect transistor. The first power supply is connected with the input end of the first field effect transistor, the second power supply is connected with the input end of the second field effect transistor, and the output end of the first field effect transistor and the output end of the second field effect transistor are both connected with the power supply port of the load circuit. The diagnostic apparatus 100 is used to control the combiner circuit block to supply power to the load circuit.

The diagnostic apparatus 100 is used for diagnosing a power supply combining circuit. And a diagnostic method for implementing the power combining circuit described above, for example, for implementing the method shown in fig. 9. The diagnostic apparatus 100 may include an acquisition unit 101 and a diagnostic unit 102, among others.

An obtaining unit 101 is configured to obtain a first input voltage, a second input voltage, and a third input voltage. Wherein the first input voltage is an input side voltage of the first field effect transistor, the second input voltage is an input side voltage of the second field effect transistor, and the third input voltage is a voltage of a power supply terminal of the load circuit. And a diagnosing unit 102, configured to diagnose whether the combiner circuit module is abnormal based on the acquired voltage.

As an example, in connection with fig. 9, the obtaining unit 101 may be configured to perform S102, and the diagnosing unit 102 may be configured to perform S103.

Optionally, the diagnosing unit 102 is specifically configured to diagnose whether the combiner circuit module is abnormal based on the obtained voltage and a preset parameter. Wherein the preset parameters include at least one of the following: the maximum voltage drop value of the second field effect transistor is calculated based on the maximum current of the load circuit, or the maximum voltage drop value of the second field effect transistor is calculated based on the maximum current of the load circuit.

As an example, in connection with fig. 9, the diagnostic unit 102 may be configured to perform S103.

Optionally, the power supply combining circuit further includes a sampling module. The sampling module is respectively connected with the input end of the first field effect transistor, the input end of the second field effect transistor and the power supply input end of the load circuit, and the sampling module is used for collecting first input voltage, second input voltage and third input voltage. The obtaining unit 101 is specifically configured to obtain a first input voltage, a second input voltage, and a third input voltage acquired by the sampling module.

As an example, in connection with fig. 9, the obtaining unit 101 may be configured to execute S102.

Optionally, the diagnostic apparatus 100 further includes: and the control unit 103 is used for controlling the states of the first field effect transistor and the second field effect transistor, wherein the states comprise an on state and an off state. An obtaining unit 101, specifically configured to obtain a first input voltage, a second input voltage, and a third input voltage of the first field effect transistor and the second field effect transistor in a target state combination, which are collected by the sampling module; wherein the target state combination comprises any one of: the first field effect transistor and the second field effect transistor are both in a conducting state; the first field effect transistor and the second field effect transistor are both in a cut-off state; the first field effect transistor is in a conducting state, and the second field effect transistor is in a cut-off state; the first field effect transistor is in a cut-off state, and the second field effect transistor is in a conducting state.

As an example, in conjunction with fig. 9, the control unit 103 may be configured to perform S101, and the acquisition unit 101 may be configured to perform S102.

Optionally, the combiner circuit module further includes a first combiner controller and a second combiner controller. The first combining controller is connected with the exciting end of the first field effect transistor, and the second combining controller is connected with the exciting end of the second field effect transistor. The control unit 103 is specifically configured to control the first combining controller to output a first excitation voltage, where the first excitation voltage is used to control the first field-effect transistor to be in a conducting state. The control unit 103 is further configured to control the second combining controller to output a second excitation voltage, where the second excitation voltage is used to control the second field effect transistor to be in a conducting state.

As an example, in connection with fig. 9, the control unit 103 may be configured to execute S101.

Optionally, the control unit 103 is further configured to control the first field effect transistor and the second field effect transistor to be in a conducting state if the diagnosis result of the combining circuit module is normal, so as to control the combining circuit module to supply power to the load circuit.

The diagnostic device 100 further includes: and the output unit 104 is configured to output an alarm signal if the diagnosis result of the combining circuit module is abnormal.

Optionally, the power of the diagnostic apparatus 100 is less than or equal to a preset threshold, and the power of the load circuit is greater than or equal to the preset threshold.

For the detailed description of the above alternative modes, reference may be made to the foregoing method embodiments, which are not described herein again. In addition, for any explanation and beneficial effects of the diagnostic apparatus 100 provided above, reference may be made to the corresponding method embodiments, and details are not repeated.

As an example, in connection with fig. 7, the functions implemented by the acquisition unit 101, the diagnostic unit 102, and the control unit 103 in the diagnostic apparatus 100 may be implemented by the processor 71 in fig. 7 executing program instructions in the memory 74. The functions performed by the output unit 104 can be realized by the input/output interface 73 in fig. 7.

Another embodiment of the present application further provides a computer-readable storage medium, where instructions are stored in the computer-readable storage medium, and when the instructions are executed on a diagnostic apparatus of a power supply combining circuit, the diagnostic apparatus of the power supply combining circuit executes each step executed by the diagnostic apparatus of the power supply combining circuit in the method flow shown in the foregoing method embodiment.

In some embodiments, the disclosed methods may be implemented as computer program instructions encoded on a computer-readable storage medium in a machine-readable format or encoded on other non-transitory media or articles of manufacture.

The embodiment of the present application further provides a circuit system for power supply rationality, where the system includes a power supply combining circuit shown in fig. 1 or fig. 2, and the power supply combining circuit is used to implement the diagnostic method of the diagnostic device for power supply combining, and for brevity, details are not described here again.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented using a software program, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. The processes or functions according to the embodiments of the present application are generated in whole or in part when the computer-executable instructions are loaded and executed on a computer. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored on a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wire (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). Computer-readable storage media can be any available media that can be accessed by a computer or can comprise one or more data storage devices, such as servers, data centers, and the like, that can be integrated with the media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.