阅读说明：本技术 一种音频模数转换芯片阵列的同步采集方法及装置 (Synchronous acquisition method and device for audio analog-to-digital conversion chip array ) 是由 唐海琪 何宣佑 于 2020-06-30 设计创作，主要内容包括：本发明提供一种音频模数转换芯片阵列的同步采集方法及装置,该方法包括主控芯片向二个以上的模数转换芯片发送时钟参考信号以及数据参考信号,每一模数转换芯片接收数据参考信号并到达预设时间后,由频率调整电路向模数转换电路输出工作时钟信号；多个模数转换芯片应用各自的工作时钟信号工作,并且将所采集的音频数据以时分复用的方式传输至主控芯片。本发明还提供实现上述方法的装置。本发明的装置结构简单,且方法实现难度小,并且能够提高多个模数转换芯片传输的音频数据的同步性。(The invention provides a synchronous acquisition method and a device of an audio analog-digital conversion chip array, wherein the method comprises the steps that a main control chip sends a clock reference signal and a data reference signal to more than two analog-digital conversion chips, and each analog-digital conversion chip receives the data reference signal and outputs a working clock signal to an analog-digital conversion circuit through a frequency adjusting circuit after reaching preset time; the analog-to-digital conversion chips work by applying respective working clock signals and transmit the acquired audio data to the main control chip in a time division multiplexing mode. The invention also provides a device for realizing the method. The device has simple structure, the method has small realization difficulty, and the synchronism of the audio data transmitted by a plurality of analog-to-digital conversion chips can be improved.)

1. A synchronous acquisition method of an audio analog-to-digital conversion chip array is characterized by comprising the following steps:

the master control chip sends clock reference signals and data reference signals to more than two analog-to-digital conversion chips, and after each analog-to-digital conversion chip receives the data reference signals and reaches preset time, a frequency adjusting circuit outputs working clock signals to an analog-to-digital conversion circuit;

the analog-to-digital conversion chips work by applying respective working clock signals and transmit the acquired audio data to the main control chip in a time division multiplexing mode.

2. The synchronous acquisition method of the audio analog-to-digital conversion chip array according to claim 1, characterized in that:

each analog-to-digital conversion chip receives the data reference signal and determines whether a preset time is reached or not, wherein the step of determining whether the preset time is reached comprises the following steps: and after each analog-to-digital conversion chip receives the data reference signal, calculating whether the level turnover frequency of the data reference signal reaches a preset frequency.

3. The synchronous acquisition method of the audio analog-to-digital conversion chip array according to claim 2, characterized in that:

the analog-to-digital conversion chip is provided with a synchronous switch, and the synchronous switch is connected between the frequency adjusting circuit and the analog-to-digital conversion circuit;

and when the level turnover frequency of the data reference signal reaches a preset frequency, the synchronous switch is switched from an off state to an on state.

4. The synchronous acquisition method of the audio analog-to-digital conversion chip array according to any one of claims 1 to 3, characterized in that:

the frequency adjusting circuit of each analog-to-digital conversion chip receives the clock reference signal sent by the master control chip, and the frequency adjusting circuit divides or multiplies the frequency of the clock reference signal to obtain the working clock signal.

5. The synchronous acquisition method of the audio analog-to-digital conversion chip array according to any one of claims 1 to 3, characterized in that:

the plurality of analog-to-digital conversion chips transmit the acquired audio data to the main control chip in a time division multiplexing mode, and the method comprises the following steps: and each analog-to-digital conversion chip transmits the acquired audio data to the main control chip according to a preset time sequence.

6. The synchronous acquisition method of the audio analog-to-digital conversion chip array according to claim 5, characterized in that:

before the master control chip sends the clock reference signal and the data reference signal to the analog-to-digital conversion chip, setting the time sequence of the data sent by each analog-to-digital conversion chip in a frame of audio data.

7. The synchronous acquisition method of the audio analog-to-digital conversion chip array according to claim 6, characterized in that:

each analog-to-digital conversion chip transmits the acquired audio data to the main control chip according to a preset time sequence, and the method comprises the following steps: and each analog-to-digital conversion chip sends the collected audio data according to preset sending time in a frame of audio data transmission time period.

8. Synchronous collection system of audio frequency analog-to-digital conversion chip array, its characterized in that includes:

the device comprises a main control chip and more than two analog-to-digital conversion chips, wherein the main control chip is used for sending clock reference signals and data reference signals to the analog-to-digital conversion chips;

each analog-to-digital conversion chip is provided with a frequency adjusting circuit and an analog-to-digital conversion circuit, after each analog-to-digital conversion chip receives the data reference signal and reaches preset time, the frequency adjusting circuit outputs a working clock signal to the analog-to-digital conversion circuit, each analog-to-digital conversion chip works by applying the respective working clock signal, and the acquired audio data are transmitted to the main control chip in a time division multiplexing mode.

9. The synchronous acquisition device of the audio analog-to-digital conversion chip array according to claim 8, characterized in that:

each analog-to-digital conversion chip receives the data reference signal and determines whether a preset time is reached or not, wherein the step of determining whether the preset time is reached comprises the following steps: and after each analog-to-digital conversion chip receives the data reference signal, calculating whether the level turnover frequency of the data reference signal reaches a preset frequency.

10. The synchronous acquisition device of the audio analog-to-digital conversion chip array according to claim 9, characterized in that:

the analog-to-digital conversion chip is provided with a synchronous switch, and the synchronous switch is connected between the frequency adjusting circuit and the analog-to-digital conversion circuit;

and when the level turnover frequency of the data reference signal reaches a preset frequency, the synchronous switch is switched from an off state to an on state.

Technical Field

The invention relates to the technical field of voice processing, in particular to a synchronous acquisition method of an audio analog-to-digital conversion chip array and a device for realizing the method.

Background

With the wide application of intelligent electronic devices, people have made more demands on the functions implemented by the intelligent electronic devices. For example, people want intelligent electronic devices to have functions of taking pictures, playing videos, and the like, and also need intelligent electronic devices to realize intelligent voice interaction, that is, to realize man-machine conversation. At present, electronic equipment such as smart phones, vehicle-mounted central control equipment and smart homes are widely applied to intelligent voice interaction technology.

In order to realize the intelligent voice interaction function, the intelligent electronic device needs to be provided with an audio acquisition device, for example, a plurality of audio analog-to-digital conversion chips need to be used for acquiring audio data. Based on the requirements of a speech preprocessing noise reduction algorithm and sound source positioning, multiple microphones are required for recording, so that the intelligent electronic device adopts a 4mic, 6mic or 8mic microphone array, usually, a single audio analog-to-digital conversion chip only supports 2 channels or 4 channels, and multiple audio digital-to-analog conversion chips may be required in the application of the microphone array.

Generally, the audio acquisition device includes a main control chip and a plurality of audio analog-to-digital conversion chips, and the plurality of audio analog-to-digital conversion chips form an audio analog-to-digital conversion chip array. However, the main control chip and the plurality of audio analog-to-digital conversion chips need to use the same reference clock signal to ensure synchronous transmission of data, and currently, synchronization between the main control chip and the plurality of audio analog-to-digital conversion chips is performed in the following ways: firstly, the master control chip provides a specific sampling clock signal to a plurality of audio analog-to-digital conversion chips, but the scheme increases the burden of system clock resources of the intelligent electronic equipment; firstly, the plurality of audio analog-to-digital conversion chips can only work as slave equipment depending on a synchronous signal provided by a main control chip, and the system design complexity of the intelligent electronic equipment is increased by the mode; thirdly, the intelligent electronic device needs to be provided with an additional synchronization circuit to ensure the sampling synchronization of each audio analog-to-digital conversion chip, but the area of a hardware circuit of the intelligent electronic device is increased in such a way, and the power consumption of the intelligent electronic device is also increased.

The existing scheme of some intelligent electronic devices is to arrange a phase-locked loop in each audio analog-to-digital conversion chip, and when a system cannot provide working clock signals for a plurality of audio analog-to-digital conversion chips, the phase-locked loop is used for generating the working clock signals required by the audio analog-to-digital conversion chips. The algorithm for processing the audio data needs no phase difference of the audio data collected by each audio analog-to-digital conversion chip, i.e. needs high synchronism. However, after the phase-locked loop is arranged in the audio analog-to-digital conversion chip, the start time of the analog sampling circuit of each audio analog-to-digital conversion chip is different, so that phase difference occurs between data acquired by each audio analog-to-digital conversion chip, and the effect of an audio processing algorithm is seriously affected. Moreover, since the voice preprocessing algorithm has a very high requirement on the synchronicity of the audio, the synchronicity between most of the audio analog-to-digital conversion chips cannot meet the requirement under the scheme of using a phase-locked loop to carry out clock frequency multiplication.

Another existing scheme is that data transmission is performed by a plurality of audio analog-to-digital conversion chips in a sampling time division multiplexing manner, for example, each audio analog-to-digital conversion chip includes an audio data input signal line and an audio data output signal line, the plurality of audio analog-to-digital conversion chips are sequentially arranged, the audio output signal line of a previous-stage audio analog-to-digital conversion chip is connected to the audio input signal line of a next-stage audio analog-to-digital conversion chip, the transmission of the first-stage audio analog-to-digital conversion chip is performed, and finally, the audio output signal line of the last-stage audio analog-to-digital conversion chip. However, the scheme has the problem that the audio signals collected by the multiple audio analog-to-digital conversion chips have phase difference, and the fundamental reason is that the sampling clocks of the multiple audio analog-to-digital conversion chips are not synchronous.

Disclosure of Invention

The invention mainly aims to provide a synchronous acquisition method of an audio analog-to-digital conversion chip array, which has good synchronism of output data of a plurality of audio analog-to-digital conversion chips.

The invention also aims to provide a synchronous acquisition device of the audio analog-to-digital conversion chip array, which has good output data synchronism of a plurality of audio analog-to-digital conversion chips.

In order to achieve the main purpose of the invention, the synchronous acquisition method of the audio frequency analog-to-digital conversion chip array comprises the steps that a main control chip sends a clock reference signal and a data reference signal to more than two analog-to-digital conversion chips, and each analog-to-digital conversion chip receives the data reference signal and outputs a working clock signal to an analog-to-digital conversion circuit through a frequency adjusting circuit after reaching preset time; the analog-to-digital conversion chips work by applying respective working clock signals and transmit the acquired audio data to the main control chip in a time division multiplexing mode.

According to the scheme, after the main control chip sends the data reference signals to the analog-to-digital conversion chips, each analog-to-digital conversion chip judges whether the preset time is reached or not according to the data reference signals, and the respective frequency adjusting circuits synchronously output the working clock signals after the preset time is reached. Because the data reference signals output by the main control chip to the analog-to-digital conversion chips are synchronous, and the preset time determined by the analog-to-digital conversion chips according to the data reference signals is also synchronous, the working clock signals of the analog-to-digital conversion chips are also synchronous, and the audio data acquired and transmitted by the analog-to-digital conversion chips according to the working clock signals are also synchronous, so that the problem that the audio data transmitted by the analog-to-digital conversion chips are asynchronous is solved.

In addition, because no additional synchronous circuit is needed to be arranged, the circuit area of the intelligent electronic equipment for collecting audio data is small, the power consumption is low, and the synchronism of audio data collection is improved under the condition that the cost of the intelligent electronic equipment is not obviously increased.

Preferably, each analog-to-digital conversion chip receiving the data reference signal to determine whether the preset time is reached comprises: after each analog-to-digital conversion chip receives the data reference signal, whether the level turnover frequency of the data reference signal reaches the preset frequency is calculated.

Therefore, as the data reference signals are sent by the main control chip, the data reference signals received by the analog-to-digital conversion chips are synchronous, namely the level turning states of the received data reference signals are also synchronous, whether the preset time is reached is determined by calculating the level turning times of the data reference signals, and the analog-to-digital conversion chips can synchronously transmit the working clock signals generated by the frequency adjusting circuit to the analog-to-digital conversion circuit, so that the synchronization of audio data acquisition is realized.

Moreover, each analog-to-digital conversion chip does not output the working clock signal to the analog-to-digital conversion circuit by the frequency adjustment circuit immediately after receiving the data reference signal, but outputs the working clock signal after the preset time. Therefore, after the analog-to-digital conversion chip receives the data reference signal, the frequency adjusting circuit has a certain time to adjust the working clock signal, and the working clock signal output to the analog-to-digital conversion circuit is ensured to be a clock signal with stable frequency.

The further scheme is that the analog-to-digital conversion chip is provided with a synchronous switch, and the synchronous switch is connected between the frequency adjusting circuit and the analog-to-digital conversion circuit; and when the level turnover frequency of the data reference signal reaches a preset frequency, the synchronous switch is switched from the off state to the on state.

Therefore, whether the frequency adjusting circuit outputs the working clock signal to the analog-to-digital conversion circuit or not is controlled through the state change of the synchronous switch, and the analog-to-digital conversion circuit can be ensured not to receive the working clock signal before the preset time is not reached, so that the synchronous acquisition of audio data by each analog-to-digital conversion chip is ensured.

According to a further scheme, the frequency adjusting circuit of each analog-to-digital conversion chip receives a clock reference signal sent by the main control chip, and the frequency adjusting circuit divides or multiplies the frequency of the clock reference signal to obtain a working clock signal.

Therefore, each analog-to-digital conversion chip uses the clock reference signal obtained by the output of the master control chip as the frequency division or frequency multiplication reference clock signal, so that the working clock signals obtained by each analog-to-digital conversion circuit can be ensured to be originated from the same reference clock signal, and the synchronism of the audio data output by each analog-to-digital conversion chip is ensured.

In a preferred embodiment, the transmitting the collected audio data to the main control chip in a time division multiplexing manner by the plurality of analog-to-digital conversion chips includes: and each analog-to-digital conversion chip transmits the acquired audio data to the main control chip according to a preset time sequence.

Therefore, the analog-to-digital conversion chips output the acquired audio data to the main control chip according to respective time sequences in a transmission period of a frame of audio data, the frame of audio data received by the main control chip contains the audio data acquired by the analog-to-digital conversion chips, the audio data acquired by the analog-to-digital conversion chips are not interfered with each other and are arranged according to a preset sequence, and the main control chip can quickly acquire the data acquired by the analog-to-digital conversion chips.

In a further scheme, before the master control chip sends the clock reference signal and the data reference signal to the analog-to-digital conversion chips, the time sequence of the data sent by each analog-to-digital conversion chip in one frame of audio data is set.

Therefore, the time sequence of the data sent by each analog-to-digital conversion chip in one frame of audio data is preset, so that after the main control chip receives one frame of audio data, the audio data collected by each analog-to-digital conversion chip can be rapidly identified and separated according to the preset time sequence, and the rapid acquisition of the audio data collected by each analog-to-digital conversion chip is realized.

Further, the step of transmitting the collected audio data to the main control chip by each analog-to-digital conversion chip according to a preset time sequence comprises: and each analog-to-digital conversion chip sends the collected audio data according to preset sending time in a frame of audio data transmission time period.

Therefore, the analog-to-digital conversion chips transmit the acquired audio data in respective time periods of one frame of audio data period, and the problem that the transmission time of the audio data acquired by the analog-to-digital conversion chips is overlapped is avoided.

In order to achieve the above another object, the synchronous acquisition device of the audio analog-to-digital conversion chip array provided by the present invention includes a main control chip and two or more analog-to-digital conversion chips, wherein the main control chip is configured to send a clock reference signal and a data reference signal to the plurality of analog-to-digital conversion chips; each analog-to-digital conversion chip is provided with a frequency adjusting circuit and an analog-to-digital conversion circuit, after each analog-to-digital conversion chip receives a data reference signal and reaches preset time, the frequency adjusting circuit outputs a working clock signal to the analog-to-digital conversion circuit, each analog-to-digital conversion chip works by applying the respective working clock signal, and collected audio data are transmitted to the main control chip in a time division multiplexing mode.

According to the scheme, after the main control chip sends the data reference signals to the analog-to-digital conversion chips, each analog-to-digital conversion chip judges whether the preset time is reached or not according to the data reference signals, and the respective frequency adjusting circuits synchronously output the working clock signals after the preset time is reached. Because the data reference signals output by the main control chip to the analog-to-digital conversion chips are synchronous, and the preset time determined by the analog-to-digital conversion chips according to the data reference signals is also synchronous, the working clock signals of the analog-to-digital conversion chips are also synchronous, and the audio data acquired and transmitted by the analog-to-digital conversion chips according to the working clock signals are also synchronous, so that the synchronism of the audio data transmitted by the analog-to-digital conversion chips is ensured.

Preferably, each analog-to-digital conversion chip receiving the data reference signal to determine whether the preset time is reached comprises: after each analog-to-digital conversion chip receives the data reference signal, whether the level turnover frequency of the data reference signal reaches the preset frequency is calculated.

The further scheme is that the analog-to-digital conversion chip is provided with a synchronous switch, and the synchronous switch is connected between the frequency adjusting circuit and the analog-to-digital conversion circuit; and when the level turnover frequency of the data reference signal reaches a preset frequency, the synchronous switch is switched from the off state to the on state.

Drawings

Fig. 1 is a schematic structural diagram of a synchronous acquisition device of an audio analog-to-digital conversion chip array according to an embodiment of the present invention.

Fig. 2 is a schematic structural diagram of an analog-to-digital conversion chip in an embodiment of a synchronous acquisition device of an audio analog-to-digital conversion chip array according to the present invention.

Fig. 3 is a flowchart of an embodiment of a synchronous acquisition method for an audio adc chip array according to the present invention.

FIG. 4 is a timing diagram of the clock reference signal, the data reference signal and the output signal in the embodiment of the synchronous acquisition method of the audio ADC chip array according to the present invention.

Fig. 5 is a timing diagram of a clock reference signal, a phase-locked loop output signal, a data reference signal, a count signal, and an operating clock signal in an embodiment of the synchronous acquisition method of the audio adc chip array according to the present invention.

The invention is further explained with reference to the drawings and the embodiments.

Detailed Description

The synchronous acquisition method of the audio analog-to-digital conversion chip array is applied to intelligent electronic equipment, such as an intelligent mobile phone, an intelligent vehicle-mounted central control system and the like. Preferably, the intelligent electronic device is provided with a sensor for collecting audio signals, such as a microphone, and a speaker. The synchronous acquisition device of the audio analog-to-digital conversion chip array is used for realizing the synchronous acquisition method of the audio analog-to-digital conversion chip array.

The embodiment of the synchronous acquisition device of the audio analog-to-digital conversion chip array comprises:

the present embodiment is applied to an intelligent electronic device, and referring to fig. 1, the present embodiment has a main control chip 10 and a plurality of analog-to-digital conversion chips, fig. 1 shows four analog-to-digital conversion chips, which are analog-to-digital conversion chips 11, 12, 13, and 14, and the structures of the analog-to-digital conversion chips are the same, and the working principles are also basically the same. It should be noted that fig. 1 only schematically shows four analog-to-digital conversion chips, and in practical application, more analog-to-digital conversion chips may be provided, and the number of the analog-to-digital conversion chips is not limited in this embodiment.

The main control chip 10 is responsible for configuring the analog-to-digital conversion chips 11, 12, 13, and 14 and providing data synchronization signals to the analog-to-digital conversion chips, and the analog-to-digital conversion chips 11, 12, 13, and 14 transmit the sampled audio data to the main control chip 10. Specifically, the main control chip 10 sends data synchronization signals to each analog-to-digital conversion chip through the bus, the signals for data synchronization include a clock reference signal bclk and a data reference signal lrclk, and in addition, the main control chip 10 also provides the IIC interface bus 18 to send configuration information to each analog-to-digital conversion chip, so as to configure each analog-to-digital conversion chip. For example, each analog-to-digital conversion chip is set to use a clock reference signal as a reference for generating an operating clock signal, and a data reference signal is used as a reference for controlling an analog-to-digital conversion circuit of each analog-to-digital conversion chip to start receiving the operating clock signal, so that each analog-to-digital conversion chip starts receiving the operating clock signal at the same time, and audio data collected by each analog-to-digital conversion chip can be synchronously transmitted to the main control chip.

In this embodiment, the plurality of analog-to-digital conversion chips send the audio data to the main control chip 10 in a time division multiplexing manner, that is, the main control chip 10 and the plurality of analog-to-digital conversion chips communicate with each other through a TDM (time division multiplexing) protocol. Specifically, the Master chip 10 is a time division multiplexing communication Master (TDM RX Master), and each analog-to-digital conversion chip is a time division multiplexing Slave (TDMTX Slave). Before each analog-to-digital conversion chip collects an audio signal, the main control chip 10 configures working parameters of each analog-to-digital conversion chip through the IIC interface bus 18, so that audio data between each analog-to-digital conversion chip is transmitted to the main control chip 10 through the TDM protocol. The audio data collected by each analog-to-digital conversion chip is output to the main control chip 10 through the bus, and therefore each analog-to-digital conversion chip outputs data sdin to the main control chip 10.

Referring to fig. 2, an analog-to-digital conversion chip 11 is taken as an example for explanation. The analog-to-digital conversion chip 11 is internally provided with a counter 31, a phase-locked loop 32, a synchronous switch 33, an analog-to-digital conversion circuit 34 and a protocol communication format processing circuit 35, wherein the counter 31 receives a data reference signal lrclk and is used for calculating the number of times of level inversion of the data reference signal lrclk, the phase-locked loop 32 is used as a frequency adjusting circuit of the embodiment and is used for receiving a clock reference signal bclk and dividing or multiplying the frequency of the clock reference signal bclk to obtain a working clock signal, and the working clock signal is used for providing a working clock for the analog-to-digital conversion circuit 34, so that the analog-to-digital conversion circuit 34 works by using the working clock.

The synchronous switch 33 is disposed between the phase-locked loop 32 and the analog-to-digital conversion circuit 34, and the synchronous switch 33 receives the signal output from the counter 31, and when the count value of the counter 31 reaches a preset number of times, outputs a closed control signal to the synchronous switch 33, and the synchronous switch 33 will be switched from an off state to an on state. When the synchronous switch 33 is in an off state, the operation clock signal output by the phase-locked loop 32 cannot be transmitted to the analog-to-digital conversion circuit 34 through the synchronous switch 33, and when the synchronous switch 33 is in an on state, the operation clock signal output by the phase-locked loop 32 is transmitted to the analog-to-digital conversion circuit 34 through the synchronous switch 33. Therefore, the counter 31 can control whether the analog-to-digital conversion circuit 34 receives the operation clock signal.

The analog-to-digital conversion circuit 34 converts the acquired analog signal into a digital signal, the digital signal is transmitted to the protocol communication format processing circuit 35, the protocol communication format processing circuit 35 converts the digital signal into audio data meeting the TDM communication protocol, and then the audio data is transmitted to the data bus and transmitted to the main control chip 10 through the data bus.

In order to ensure that the audio data transmitted by each analog-to-digital conversion chip are synchronized, the main control chip 10 transmits a clock reference signal bclk as a reference clock signal to each analog-to-digital conversion chip through the bus, so as to ensure that each analog-to-digital conversion chip uses the same reference clock signal to perform frequency division or frequency multiplication to obtain respective working clock signals. On the other hand, the data reference signal lrclk is sent to each analog-to-digital conversion chip, and each analog-to-digital conversion chip determines the conduction time of the synchronous switch by calculating the level turnover times of the data reference signal lrclk, so that the analog-to-digital conversion circuits of each analog-to-digital conversion chip can indirectly search respective working clock signals at the same time.

Therefore, the working clock signals of the analog-to-digital conversion chips are all based on the same reference clock signal, so that the synchronism of the working clock signals of the analog-to-digital conversion chips is ensured. Preferably, the main control chip 10 may preset frequency division or frequency multiplication values of the phase-locked loops 32 of the analog-to-digital conversion chips, for example, the frequency division values or the frequency multiplication values of the analog-to-digital conversion chips are the same, so that after receiving the same clock reference signal bclk, the phase-locked loops 32 of the analog-to-digital conversion chips perform frequency division and frequency multiplication by using the same frequency division value or frequency multiplication value, and the obtained working clock signals have the same frequency. Therefore, the embodiment can realize that each analog-to-digital conversion chip works with the same frequency of the working clock signal.

In order to realize that the audio data output by each analog-to-digital conversion chip has no phase difference, the working clock signals of each analog-to-digital conversion chip are required to be synchronous, and the synchronism of the audio data transmitted by each analog-to-digital conversion chip in each frame of audio data is also required to be ensured. Therefore, the present embodiment controls the synchronicity of the transmission of the audio data in each frame of audio data by the analog-to-digital conversion chips by setting the data reference signal lrclk.

Specifically, the clock reference signal bclk is a transmission time of single-bit data, and one transition interval of the data reference signal lrclk indicates a transmission period of one frame of audio data. Referring to fig. 3, in a transition interval of the data reference signal lrclk, each analog-to-digital conversion chip needs to transmit respective audio data corresponding to one frame of audio data to the main control chip 10. For example, a frame of audio data received by the main control chip 10 includes audio data of multiple channels (slots), the audio data of each channel is audio data transmitted by one analog-to-digital conversion chip, and the slot _ size in fig. 3 indicates the length of the audio data transmitted by one analog-to-digital conversion chip. In a frame of audio data transmission period, the four analog-to-digital conversion chips transmit respective audio data to the main control chip 10 in a time division multiplexing manner. For example, in the first frame audio data transmission period, the audio data transmitted by the analog-to-digital conversion chip 11 to the main control chip 10 is ADC1_0, the audio data transmitted by the analog-to-digital conversion chip 12 to the main control chip 10 is ADC2_0, the audio data transmitted by the analog-to-digital conversion chip 13 to the main control chip 10 is ADC3_0, the audio data transmitted by the analog-to-digital conversion chip 14 to the main control chip 10 is ADC4_0, in the second frame audio data transmission period, the audio data transmitted by the analog-to-digital conversion chip 11 to the main control chip 10 is ADC1_1, the audio data transmitted by the analog-to-digital conversion chip 12 to the main control chip 10 is ADC2_1, and so on. Therefore, the length of one data reference signal lrclk flip period is the sum of the time lengths of the four analog-to-digital conversion chips transmitting the audio data to the main control chip 10. When the level of the data reference signal lrclk is inverted to indicate that the acquisition period of the next frame of audio data starts, each analog-to-digital conversion chip immediately enters the data acquisition and transmission of the next audio data transmission period.

In practical applications, the number of the analog-to-digital conversion chips may be larger, and thus, it is necessary to divide a frame of audio data transmission period into more parts to ensure that each analog-to-digital conversion chip obtains the time for transmitting the audio data in one frame of audio data transmission period. Preferably, in one frame of audio data transmission period, the time for each analog-to-digital conversion chip to transmit audio data to the main control chip 10 is equal, that is, the slot _ size corresponding to each analog-to-digital conversion chip is equal. Of course, the slot _ size corresponding to each analog-to-digital conversion chip may also be unequal, which may be configured by the main control chip 10. In addition, the transmission period of one frame of audio data may be slightly longer than the sum of the time lengths of the four analog-to-digital conversion chips transmitting the audio data to the main control chip 10, for example, after the level of the data reference signal lrclk is inverted and the time is short, the first analog-to-digital conversion chip transmits the acquired audio data to the main control chip 10.

Each analog-to-digital conversion chip sends the acquired audio data to a preset bus in a time division multiplexing manner, for example, to a sdin/sdout signal line, and transmits the audio data to the main control chip 10 through the bus. In order to distinguish the audio data collected by each analog-to-digital conversion chip, the main control chip 10 needs to preset the time sequence of sending the audio data by each analog-to-digital conversion chip, that is, determine in which order each analog-to-digital conversion chip transmits data to the main control chip 10 in the transmission period of a frame of audio data. For example, the main control chip 10 is configured to sequentially send audio data to the main control chip 10 by the analog-to-digital conversion chips 11, 12, 13, and 14. Therefore, in a frame of audio data transmission period, the time when each analog-to-digital conversion chip transmits data to the main control chip 10, for example, after the level of the data reference signal lrclk is inverted, the analog-to-digital conversion chip 11 transmits the acquired audio data to the main control chip 10 after 2 microseconds, the time when the analog-to-digital conversion chip 11 transmits the audio data to the main control chip 10 is 10 microseconds, after the level of the data reference signal lrclk is inverted for 12 microseconds, the analog-to-digital conversion chip 12 transmits the audio data to the main control chip 10, the time when the audio data is transmitted is also 10 microseconds, after the level of the data reference signal lrclk is inverted for 22 microseconds, the analog-to-digital conversion chip 13 transmits the audio data to the main control chip 10, and so on.

As can be seen, by setting the time sequence and the transmission time for sending the acquired audio data to the main control chip 10 by each analog-to-digital conversion chip within one frame of audio data transmission period, on one hand, the time for sending the audio data to the main control chip 10 by each analog-to-digital conversion chip can be ensured not to overlap, and the problem of mutual interference of the audio data sent by each analog-to-digital conversion chip is avoided; on the other hand, it can be ensured that each analog-to-digital conversion chip can send audio data to the main control chip 10 in the same frame audio data transmission period, and the synchronization of sending audio data to the main control chip 10 by a plurality of analog-to-digital conversion chips is realized. It should be noted that, the plurality of analog-to-digital conversion chips synchronously send the audio data to the main control chip 10, which does not mean that the plurality of analog-to-digital conversion chips simultaneously send the audio data to the main control chip 10, but the plurality of analog-to-digital conversion chips transmit the audio data to the main control chip 10 according to respective time sequences in the same frame of audio data transmission period, so as to ensure that the audio data received by the main control chip 10 in one frame of audio data transmission period is the audio data transmitted by each analog-to-digital conversion chip in the frame of audio data transmission period, and the situation that the same analog-to-digital conversion chip sends the audio data to the main control chip 10 twice in one frame of audio data transmission period does not occur.

In order to ensure that the audio data transmitted by each analog-to-digital conversion chip is synchronized, the main control chip 10 not only configures the time for each analog-to-digital conversion chip to send audio data in one frame of audio data transmission period, but also needs to ensure the synchronization of the working clock signals of each analog-to-digital conversion chip. In this embodiment, after each analog-to-digital conversion chip receives the data reference signal lrclk, the synchronous switch is turned on only after a preset time, and the phase-locked loop outputs a working clock signal to the analog-to-digital conversion circuit. In order to ensure the consistency of the preset time calculated by each analog-to-digital conversion chip, in the embodiment, the counter 31 of each analog-to-digital conversion chip calculates the level inversion times of the data reference signal lrclk to determine whether the preset time is reached. For example, assuming that the level flip period of the data reference signal lrclk is 40 microseconds, if it is desired that the analog-to-digital conversion circuit of each analog-to-digital conversion chip starts to operate 200 microseconds after the main control chip 10 sends the data reference signal lrclk, the counter of each analog-to-digital conversion chip counts the level flip times of the data reference signal lrclk, for example, after 5 times, the counter outputs a closed control signal to the synchronous switch 33, and the synchronous switch 33 will be switched from an off state to an on state. When the synchronous switch 33 is switched to the on state, the analog-to-digital conversion circuit 34 receives the operation clock signal and outputs the audio data to the main control chip 10 according to the operation clock signal.

Fig. 4 shows the timing of the clock reference signal ref _ clk, the phase-locked loop output signal pll _ clk, the data reference signal lrclk, the count signal lrclk _ counter, and the operating clock signal ana _ clk transmitted by the main control chip 10. As shown in fig. 4, the working clock signal ana _ clk becomes a pulse signal after the count signal lrclk _ counter reaches a predetermined number of times, i.e., the analog-to-digital conversion circuit receives the working clock signal after the count signal lrclk _ counter reaches the predetermined number of times.

Since the data reference signal lrclk is also sent by the main control chip 10, the data reference signals lrclk received by the analog-to-digital conversion chips are the same, and the synchronization of the working clock signals of the analog-to-digital conversion chips can be simply and accurately realized by calculating the level turnover times of the data reference signals lrclk. In addition, after each analog-to-digital conversion chip is powered on to work, the clock signal output by the phase-locked loop is unstable, and after the preset time, the clock signal output by the phase-locked loop becomes stable. Therefore, the working clock signal is output to the analog-to-digital conversion circuit after the estimated time, and the working clock signal received by each analog-to-digital conversion circuit can be ensured to be stable.

The embodiment of the synchronous acquisition method of the audio analog-to-digital conversion chip array comprises the following steps:

the working flow of the synchronous acquisition device of the audio analog-to-digital conversion chip array is described below with reference to fig. 5. Firstly, step S51 is executed, the main control chip configures each analog-to-digital conversion chip, specifically, the main control chip configures an internal phase-locked loop of each analog-to-digital conversion chip to use the clock reference signal bclk as a reference clock signal of the phase-locked loop, and preferably, a frequency division value or a frequency multiplication value of the phase-locked loop may also be set.

In addition, the main control chip is also configured with a counting target value of each analog-to-digital conversion chip for the data reference signal lrclk, namely, the counter is used for starting the synchronous switch when the level of the data reference signal lrclk is turned over for several times. Then, the master control chip configures each analog-to-digital conversion chip to be in a slave mode of a TDM protocol through an IIC interface bus, and configures each analog-to-digital conversion chip to transmit the acquired audio data to the master control chip at different moments according to the TDM protocol.

Next, step S52 is executed, and the master chip configures itself to the host mode of the TDM protocol, and configures the frequency of the clock reference signal bclk and the length of the data reference signal lrclk. Then, step S53 is executed, and the main control chip provides the clock reference signal bclk and the data reference signal lrclk to each analog-to-digital conversion chip.

After receiving the clock reference signal bclk and the data reference signal lrclk sent by the main control chip, the analog-to-digital conversion chip determines whether the first time the data reference signal lrclk is received reaches a preset time, i.e., step S54 is executed, if not, the analog-to-digital conversion chip continues to wait, and if so, step S55 is executed. Judging whether the preset time is reached can be realized by calculating the turnover times of the level of the data reference signal lrclk.

After the analog-to-digital conversion chip receives the clock reference signal bclk, the phase-locked loop divides or multiplies the frequency of the clock reference signal bclk according to the clock reference signal bclk and a set frequency division value or frequency multiplication value to obtain a working clock signal. However, the operating clock signal generated by the phase-locked loop is not immediately transmitted to the analog-to-digital conversion circuit because the synchronous switch is in an off state. After the analog-to-digital conversion chip receives the data reference signal lrclk, the counter calculates the level turnover frequency of the data reference signal lrclk, after the level turnover frequency of the data reference signal lrclk reaches a preset frequency, the synchronous switch is switched to a conducting state, at this time, step S55 is executed, and the phase-locked loop outputs a working clock signal to the analog-to-digital conversion circuit.

Then, the analog-to-digital conversion chip executes step S56 to acquire an audio signal and convert the acquired audio signal into a digital signal, and then the protocol communication format processing circuit forms audio data meeting the requirements of the communication protocol. However, the adc does not immediately transmit the audio data to the main control chip, but performs step S57 to determine whether a preset time sequence is reached, that is, whether a preset time sequence is reached within a frame of audio data transmission period, if not, the adc continues to wait, and if the preset time sequence is reached, the adc outputs an audio signal to the main control chip in step S58. Therefore, the main control chip receives a frame of audio data which contains the audio data sent by each analog-to-digital conversion chip according to the preset time sequence.

And finally, executing step S59 to determine whether the audio data acquisition is finished, if so, ending the audio data acquisition process, otherwise, returning to step S56, and each analog-to-digital conversion chip continues to acquire the audio signal and sends the audio data according to the respective time sequence in each frame of audio data transmission period.

The phase-locked loop used for generating the working clock signal is arranged in each analog-to-digital conversion chip, so that the frequency of the reference clock signal can be flexibly multiplied or divided to obtain the working clock signal required by each analog-to-digital conversion circuit, and the requirement of a system clock source is simplified. In addition, the synchronous sampling device of the invention supports setting the analog-to-digital conversion chip to be in a TDM slave machine working mode, thereby facilitating the data transmission of each analog-to-digital conversion chip, reducing the complexity of the design of voice interaction products and shortening the research and development period. In addition, the invention realizes the synchronization of the clock signals of the analog-digital conversion chips by using a data reference signal lrclk counting mode, ensures that the voice algorithm accurately processes audio data, and enables users to obtain better human-computer interaction experience.

Finally, it should be emphasized that the present invention is not limited to the above-mentioned embodiments, for example, a frequency dividing circuit or a frequency multiplying circuit is used instead of a phase locked loop as a circuit for generating an operating clock signal, or a change in timing of sending audio data by each analog-to-digital conversion chip, etc., and such changes should also be included in the protection scope of the claims of the present invention.