阅读说明：本技术 一种缓存分配控制方法、装置、终端设备及存储介质 (Cache allocation control method and device, terminal equipment and storage medium ) 是由 王名为 高峰 许祥滨 林伟明 王玲 段永波 于 2020-06-01 设计创作，主要内容包括：本申请实施例适用于集成电路技术领域,提供了一种缓存分配控制方法、装置、终端设备及存储介质,所述方法包括：当检测到外接存储设备时,识别所述外接存储设备的存储类型；根据所述外接存储设备的存储类型,确定待分配给所述外接存储设备的缓存数量；按照所述待分配给所述外接存储设备的缓存数量,为所述外接存储设备分配相应数量的缓存。本实施例通过将缓存配置成可分割的形式,根据外接存储设备类型的不同,分别为各个外接存储设备分配缓存,有助于提高CPU的性能。(The embodiment of the application is applicable to the technical field of integrated circuits, and provides a cache allocation control method, a cache allocation control device, terminal equipment and a storage medium, wherein the method comprises the following steps: when the external storage equipment is detected, identifying the storage type of the external storage equipment; determining the cache quantity to be allocated to the external storage equipment according to the storage type of the external storage equipment; and distributing a corresponding amount of caches to the external storage equipment according to the number of the caches to be distributed to the external storage equipment. In the embodiment, the cache is configured to be in a divisible form, and the cache is respectively allocated to each external storage device according to different types of the external storage devices, which is beneficial to improving the performance of the CPU.)

1. A method for controlling cache allocation, comprising:

when the external storage equipment is detected, identifying the storage type of the external storage equipment;

determining the cache quantity to be allocated to the external storage equipment according to the storage type of the external storage equipment;

and distributing a corresponding amount of caches to the external storage equipment according to the number of the caches to be distributed to the external storage equipment.

2. The method of claim 1, wherein identifying the storage type of the external storage device when the external storage device is detected comprises:

when an external storage device is detected, identifying a storage object in the external storage device, wherein the storage object comprises at least one of a program object or a data object;

and determining the storage type of the external storage equipment according to the storage object in the external storage equipment.

3. The method of claim 1, wherein identifying the storage type of the external storage device when the external storage device is detected comprises:

when the external storage equipment is detected, identifying the access bandwidth of the external storage equipment;

and determining the storage type of the external storage equipment according to the access bandwidth of the external storage equipment.

4. The method of claim 1, wherein identifying the storage type of the external storage device when the external storage device is detected comprises:

when detecting the external storage device, identifying a predefined product type in a nonvolatile memory accessible to a chip CPU;

and determining the storage type of the external storage equipment according to the product type.

5. The method according to any one of claims 1 to 4, wherein the determining, according to the storage type of the external storage device, the number of buffers to be allocated to the external storage device comprises:

reading the configuration information of the external storage equipment;

obtaining cache allocation information matched with the configuration information, wherein the cache allocation information is generated according to a test result obtained by testing external storage equipment of different storage types in advance;

and determining the quantity of the caches to be allocated to the external storage equipment according to the cache allocation information.

6. The method of claim 5, wherein the cache comprises a plurality of cache memories, and wherein determining the number of caches to be allocated to the external storage device according to the cache allocation information comprises:

and determining the number of cache memories to be allocated to the storage objects in the external storage equipment according to the number of the cache memories required by different storage objects recorded in the cache allocation information.

7. The method according to claim 6, wherein said allocating a corresponding number of buffers to the external storage device according to the number of buffers to be allocated to the external storage device comprises:

and distributing a corresponding number of cache memories for the storage objects in the external storage equipment according to the number of the cache memories to be distributed to the storage objects.

8. The method of claim 7, wherein allocating a corresponding number of cache memories to the storage objects in the external storage device according to the number of cache memories to be allocated to the storage objects comprises:

determining an access interface corresponding to the storage object;

and configuring the cache memory allocated to the memory object in association with the access interface.

9. A terminal device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the cache allocation control method according to any one of claims 1 to 8 when executing the computer program.

10. A computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the cache allocation control method according to any one of claims 1 to 8.

Technical Field

The present application relates to the field of integrated circuit technologies, and in particular, to a method and an apparatus for controlling cache allocation, a terminal device, and a storage medium.

Background

Generally, a System-on-a-Chip (SoC) includes a Central Processing Unit (CPU) and a plurality of memory devices. Depending on the information stored, the memory device may be roughly divided into an instruction memory and a data memory. Common instruction memories include on-chip ROM, off-chip FLASH, and the like, and common data memories include on-chip ROM, on-chip RAM, off-chip SDRAM, off-chip FLASH, and the like. Wherein, the access speed of the on-chip ROM and the on-chip RAM is higher, and the access speed of the off-chip SDRAM and the off-chip FLASH is lower.

When the CPU is in operation, since the execution of any instruction involves the type of operation to be performed and the data to be operated on, it is often necessary to access both the instruction and the data. However, the operation performance of the CPU is limited by the slower of the instruction access speed and the data access speed, and how to balance the instruction access speed and the data access speed and maximize the performance of the CPU is a problem that needs to be solved by those skilled in the art.

Disclosure of Invention

In view of this, embodiments of the present application provide a method and an apparatus for controlling cache allocation, a terminal device, and a storage medium, which can balance instruction access speed and data access speed and improve CPU performance.

A first aspect of an embodiment of the present application provides a cache allocation control method, including:

when the external storage equipment is detected, identifying the storage type of the external storage equipment;

determining the cache quantity to be allocated to the external storage equipment according to the storage type of the external storage equipment;

and distributing a corresponding amount of caches to the external storage equipment according to the number of the caches to be distributed to the external storage equipment.

Optionally, the identifying, when an external storage device is detected, a storage type of the external storage device includes:

when an external storage device is detected, identifying a storage object in the external storage device, wherein the storage object comprises at least one of a program object or a data object;

and determining the storage type of the external storage equipment according to the storage object in the external storage equipment.

Optionally, the identifying, when an external storage device is detected, a storage type of the external storage device includes:

when the external storage equipment is detected, identifying the access bandwidth of the external storage equipment;

and determining the storage type of the external storage equipment according to the access bandwidth of the external storage equipment.

Optionally, the identifying, when an external storage device is detected, a storage type of the external storage device includes:

when detecting the external storage device, identifying a predefined product type in a nonvolatile memory accessible to a chip CPU;

and determining the storage type of the external storage equipment according to the product type.

Optionally, the determining, according to the storage type of the external storage device, the number of caches to be allocated to the external storage device includes:

reading the configuration information of the external storage equipment;

obtaining cache allocation information matched with the configuration information, wherein the cache allocation information is generated according to a test result obtained by testing external storage equipment of different storage types in advance;

and determining the quantity of the caches to be allocated to the external storage equipment according to the cache allocation information.

Optionally, the cache includes a plurality of cache memories, and determining, according to the cache allocation information, the number of caches to be allocated to the external storage device includes:

and determining the number of cache memories to be allocated to the storage objects in the external storage equipment according to the number of the cache memories required by different storage objects recorded in the cache allocation information.

Optionally, the allocating, according to the number of the caches to be allocated to the external storage device, a corresponding number of caches to the external storage device includes:

and distributing a corresponding number of cache memories for the storage objects in the external storage equipment according to the number of the cache memories to be distributed to the storage objects.

Optionally, the allocating, according to the number of the cache memories to be allocated to the storage object, a corresponding number of cache memories to the storage object in the external storage device includes:

determining an access interface corresponding to the storage object;

and configuring the cache memory allocated to the memory object in association with the access interface.

A second aspect of the embodiments of the present application provides a cache allocation control apparatus, including:

the identification module is used for identifying the storage type of the external storage equipment when the external storage equipment is detected;

the determining module is used for determining the cache quantity to be allocated to the external storage equipment according to the storage type of the external storage equipment;

and the distribution module is used for distributing the corresponding number of caches to the external storage equipment according to the number of the caches to be distributed to the external storage equipment.

A third aspect of embodiments of the present application provides a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the cache allocation control method according to any one of the above first aspects when executing the computer program.

A fourth aspect of embodiments of the present application provides a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, the computer program implements the cache allocation control method according to any one of the first aspect.

A fifth aspect of embodiments of the present application provides a computer program product, which, when running on a terminal device, causes the terminal device to execute the cache allocation control method according to any one of the first aspect.

Compared with the prior art, the embodiment of the application has the following advantages:

according to the embodiment of the application, when the external storage device is detected, the storage type of the external storage device can be firstly identified, and the number of the caches to be allocated to the external storage device is determined according to the storage type, so that the corresponding number of the caches can be allocated to the external storage device according to the number of the caches. In the embodiment, the cache is configured into a divisible form, and caches with different proportions or specific quantities are respectively allocated to the external storage devices according to different types of the external storage devices, so that the performance of the CPU is improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings used in the embodiments or the description of the prior art will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.

Fig. 1 is a schematic flowchart illustrating steps of a cache allocation control method according to an embodiment of the present application;

FIG. 2 is a flow chart illustrating steps of another cache allocation control method according to an embodiment of the present application;

FIG. 3 is a flowchart illustrating steps of another cache allocation control method according to an embodiment of the present application;

fig. 4 is a schematic diagram of a cache allocation control apparatus according to an embodiment of the present application;

fig. 5 is a schematic diagram of a terminal device according to an embodiment of the present application.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

In general, in chip design, the core function of a chip can be designed in the form of an on-chip memory. That is, a general function of a certain chip that can be applied to a plurality of different products is designed in the chip, and personalized development for different products can be handled in the form of an off-chip memory. Generally, on-chip memory has a small capacity but a fast access speed, while off-chip memory has a large capacity and can be changed, but the access speed is relatively slow. In practical tests, the access speed of the on-chip memory can reach more than 30 times of the access speed of the off-chip memory.

Therefore, in order to balance the access speeds of different memories, the embodiment may configure the cache in a divisible form, and test the number of caches required to obtain optimal performance when different memories exist, so that when the existence of the off-chip memory is detected, the off-chip memory may be allocated according to the corresponding number of caches.

The technical solution of the present application will be described below by way of specific examples.

Referring to fig. 1, a schematic flow chart illustrating steps of a cache allocation control method according to an embodiment of the present application is shown, which may specifically include the following steps:

s101, when detecting an external storage device, identifying the storage type of the external storage device;

it should be noted that the method may be applied to a terminal device, that is, the execution subject of the embodiment is the terminal device. The terminal device may be a certain product produced based on a certain SoC chip, such as a certain electronic device or other devices. The terminal equipment can improve the running efficiency of the CPU by distributing the cache.

In general, a product produced based on a certain SoC chip may be a variety of different types of products or devices. For example, for this type of SoC chip, a chip manufacturer may write the most core and general program or algorithm into the chip, and may write other algorithms or programs individually required by different customers into other storage devices, and associate the storage devices with the SoC chip, so as to flexibly configure the SoC chip for different customers.

In this embodiment, the external storage device may be a device written with a corresponding program or algorithm according to the actual needs of the device manufacturer.

After the SoC chip is powered on, if it is detected that an external storage device exists, the storage type of the external storage device may be identified first.

Generally, depending on the objects stored, a storage device can be roughly divided into an instruction storage device, a data storage device, or a device capable of storing both instructions and data.

It should be noted that the external storage device involved in the embodiment of the present application may include all memories except the CPU cache memory, such as common instruction memory (on-chip ROM, off-chip FLASH, etc.), common data memory (on-chip ROM, on-chip RAM, off-chip SDRAM, off-chip FLASH, etc.), and the like, including common data memory types. All memory that the CPU needs to access through the cache memory, including all memory on-chip and off-chip.

In this embodiment of the application, identifying the storage type of the external storage device may be performed by identifying a storage object of the external storage device, identifying an access bandwidth of the external storage device, or identifying a predefined product type in a nonvolatile memory accessible to a chip CPU when the external storage device is detected, and then determining the storage type of the external storage device according to the storage object, the access bandwidth, or the product type.

S102, determining the cache quantity to be allocated to the external storage equipment according to the storage type of the external storage equipment;

in this embodiment, the cache may be configured to be in a divisible form, and according to different storage types of the external storage device, how many caches need to be allocated to the device may be determined according to respective storage types.

For example, for an instruction storage device storing code to be executed and a data storage device storing only video data, a general buffer may be allocated to each of the two storage devices to ensure the balance of the access speeds of instructions and data.

S103, distributing a corresponding amount of caches to the external storage equipment according to the number of the caches to be distributed to the external storage equipment.

In this embodiment, after determining how many caches need to be allocated to the external storage device, the corresponding caches may be allocated to the external storage device.

In the embodiment of the application, when the external storage device is detected, the storage type of the external storage device may be firstly identified, and the number of the caches to be allocated to the external storage device is determined according to the storage type, so that the corresponding number of the caches may be allocated to the external storage device according to the number of the caches. In the embodiment, the cache is configured into a divisible form, and caches with different proportions or specific quantities are respectively allocated to the external storage devices according to different types of the external storage devices, so that the performance of the CPU is improved.

Referring to fig. 2, a schematic flow chart illustrating steps of another cache allocation control method according to an embodiment of the present application is shown, which may specifically include the following steps:

s201, when an external storage device is detected, identifying a storage object in the external storage device;

in this embodiment, the external storage device may be an off-chip device. The chip inside and the chip outside are two concepts in the field of integrated circuits, and the chip inside refers to the inside of the integrated circuit made into a chip, which is called the chip inside for short; the off-chip is a short for external device, which refers to a device outside the integrated circuit chip. The connection between the ic chip and the external device generally needs to be realized through a special interface circuit and a bus.

By externally connecting other storage equipment to the chip, various different terminal products can be produced based on the same chip. For example, a chip may be disposed on a circuit board, and then different resources may be attached to the periphery of the chip to form a plurality of different products. The general codes required by different products can be written into the chip, and the codes corresponding to the additional functions required by the products can be written into the external device according to different product types. In this case, the definition mode of the product type may be that a specific code is written into a nonvolatile memory accessible to the CPU of the chip through a production phase, the CPU reads and accesses the specific code after being powered on to obtain the corresponding product type, and then the CPU may adjust the cache allocation modes of different external storage devices according to the demand characteristics of different product types for different memories, in combination with the detected information such as the storage object and access bandwidth of the external storage device.

After the chip is powered on, if the existence of the external storage device is detected, the storage object in the external storage device can be firstly identified. In this embodiment, the storage object may include a program object, a data object, or both.

S202, determining the storage type of the external storage equipment according to the storage object in the external storage equipment;

in this embodiment, the external storage device may be divided into devices that only store program objects, such as devices that store executable programs or codes, according to different storage objects in the external storage device; or devices that store only data objects, such as devices that store only some picture data, video data, and no other executable programs or code; or a device that can store both program objects and data objects, such as a device that stores not only video data but also other executable programs.

S203, reading the configuration information of the external storage equipment;

in this embodiment, the configuration information of the external storage device may be factory information written into the chip when the chip is shipped, and it can be known from the configuration information what product the current chip is applied to, and what configuration needs to be cached on the product, which is helpful for improving the performance of the CPU.

S204, obtaining cache allocation information matched with the configuration information, wherein the cache allocation information is generated according to test results obtained by testing external storage equipment of different storage types in advance;

in this embodiment, for different products to which the chip is applied, the external storage device may be tested to know which cache configuration mode is the configuration mode in which the product can obtain the optimal performance.

In specific implementation, for a certain product, a program or code for implementing certain specific functions of the product may be written into an external storage device, and then the external storage device may be connected. Then, by testing the running performance of the CPU in different cache configuration modes, it can be known which cache configuration mode should be adopted when the chip of the product is connected with the storage device, and the optimal performance can be obtained.

For example, if the chip cache capacity is 32kb cache, a 1kb cache may be allocated as an instruction cache, a 31kb cache may be allocated as a data cache, and the chip performance may be tested to obtain a performance result; secondly, redistributing a 2kb cache as an instruction cache and a 30kb cache as a data cache, and testing the performance of the chip to obtain another performance result; according to the method, at least 32 performance results can be tested, the cache allocation mode with the optimal performance can be identified from the 32 performance results and written into the configuration information, and after the chips are produced in batches, similar performance tests are not required to be carried out again, and the cache allocation mode can be directly configured according to the indication of the configuration information to achieve the optimal performance effect.

S205, determining the number of caches to be allocated to the external storage equipment according to the cache allocation information;

in this embodiment, after the type of the external storage device is identified, the number of caches to be allocated to the external storage device may be determined according to the cache allocation information in the configuration information.

For example, a 1kb cache may be allocated as an instruction cache and a 31kb cache as a data cache.

S206, distributing a corresponding amount of caches to the external storage equipment according to the number of the caches to be distributed to the external storage equipment.

In the embodiment of the present application, according to different storage types of the external storage device, a cache allocation manner with optimal CPU performance when the external storage device is externally connected with a corresponding type of device can be obtained through testing and written into the configuration information, so that after a certain type of external storage device is detected, the allocation manner can be directly read from the configuration information, and cache allocation is performed according to the allocation manner. According to the embodiment, the cache allocation modes corresponding to different external storage devices are obtained through testing, so that the caches are allocated flexibly, the use under different scenes can be dealt with, and the CPU performance is improved.

Referring to fig. 3, a schematic flow chart illustrating steps of another cache allocation control method according to an embodiment of the present application is shown, which may specifically include the following steps:

s301, when an external storage device is detected, identifying a storage object in the external storage device;

s302, determining the storage type of the external storage device according to the storage object in the external storage device;

s303, reading configuration information of the external storage equipment;

s304, obtaining cache allocation information matched with the configuration information, wherein the cache allocation information is generated according to test results obtained by testing external storage equipment of different storage types in advance;

it should be noted that steps S301 to S304 in this embodiment are similar to steps S201 to S204 in the foregoing embodiment, and reference may be made to each other, which is not limited in this embodiment.

S305, determining the number of cache memories to be allocated to the storage objects in the external storage equipment according to the number of the cache memories required by different storage objects recorded in the cache allocation information;

in this embodiment, the cache may include a plurality of cache memories. That is, the cache is configured in the form of a memory cluster, and is dynamically allocated for different application objects and scenes.

In a specific implementation, the allocation manner configured in the cache allocation information may refer to the number of cache memories required for different storage objects in the external storage device.

For example, for an external storage device that stores both program objects and data objects, half of the cache memory may be allocated to the program objects and the other half of the cache memory may be allocated to the other data objects.

S306, determining an access interface corresponding to the storage object;

in this embodiment, after determining how many cache memories need to be allocated to the storage objects in the external storage device, the corresponding number of cache memories may be allocated to different storage objects in the external storage device according to the number of cache memories to be allocated to different storage objects.

In a specific implementation, access interfaces corresponding to different storage objects may be determined. For example, which are the instruction interfaces for the program objects and which are the data interfaces for the data objects.

It should be noted that, in a typical implementation, the instruction interface and the data interface may be the same physical interface. However, the physical location of the memory may be differentiated according to the address field to be saved or the instruction to be accessed by the CPU. The above process can be analogized to the meaning of "port" in the internet, that is, the physical ports are the same, but can be distinguished according to the difference of target "port" when data is distributed.

S307, configuring the cache memory allocated to the storage object in association with the access interface.

In this embodiment, when allocating caches to different storage objects, the cache memory that needs to be allocated to the storage object may be configured in association with the access interface corresponding to the cache memory.

As an example of this embodiment, if a product produced based on a certain chip needs to support both the operation mode of on-chip ROM + on-chip RAM and the operation mode of off-chip FLASH + on-chip RAM.

Then, when the working mode of on-chip ROM + on-chip RAM is supported, since the on-chip ROM is a private memory of the CPU and the access bandwidth of the on-chip ROM interface meets the requirement of real-time reading of the CPU, the cache function does not need to be used. In this case, the optimal cache allocation scheme is to divide all memories in the cache into on-chip RAM access interfaces to ensure that the access speeds of instructions and data are balanced.

When the off-chip FLASH + on-chip RAM mode is supported, the access bandwidth of the off-chip FLASH is usually significantly smaller than that of the on-chip RAM, or the off-chip FLASH is less efficient, the access speed is slower, and the off-chip FLASH often contains both program objects (instructions) and data objects (data). Therefore, the optimal solution in this case is to divide half of the total cache memory into the instruction interface of the off-chip FLASH and the other half into the data interface of the off-chip FLASH.

In the embodiment of the application, the cache can be configured into a cache memory cluster, so that the cache memory can be flexibly allocated to the storage objects according to the storage objects stored by the external storage device, and the performance of the CPU is improved.

It should be noted that, the sequence numbers of the steps in the foregoing embodiments do not mean the execution sequence, and the execution sequence of each process should be determined by the function and the inherent logic of the process, and should not constitute any limitation on the implementation process of the embodiments of the present application.

Referring to fig. 4, a schematic diagram of a cache allocation control apparatus according to an embodiment of the present application is shown, which may specifically include the following modules:

the identification module 401 is configured to identify a storage type of an external storage device when the external storage device is detected;

a determining module 402, configured to determine, according to a storage type of the external storage device, a cache amount to be allocated to the external storage device;

the allocating module 403 is configured to allocate a corresponding number of caches to the external storage device according to the number of caches to be allocated to the external storage device.

In this embodiment, the identification module 401 may specifically include the following sub-modules:

the storage object identification submodule is used for identifying a storage object in the external storage device when the external storage device is detected, wherein the storage object comprises at least one of a program object or a data object;

and the first storage type determining submodule is used for determining the storage type of the external storage equipment according to the storage object in the external storage equipment.

In this embodiment, the identification module 401 may further include the following sub-modules:

the access bandwidth identification submodule is used for identifying the access bandwidth of the external storage device when the external storage device is detected;

and the second storage type determining submodule is used for determining the storage type of the external storage equipment according to the access bandwidth of the external storage equipment.

In this embodiment, the identification module 401 may further include the following sub-modules:

the product type identification submodule is used for identifying the product type predefined in the nonvolatile memory accessible to the CPU of the chip when the external storage equipment is detected;

and the third storage type determining submodule is used for determining the storage type of the external storage equipment according to the product type.

In this embodiment of the application, the determining module 402 may specifically include the following sub-modules:

the configuration information reading submodule is used for reading the configuration information of the external storage equipment;

the cache allocation information acquisition submodule is used for acquiring cache allocation information matched with the configuration information, and the cache allocation information is generated according to a test result obtained by testing external storage equipment of different storage types in advance;

and the cache quantity determining submodule is used for determining the cache quantity to be allocated to the external storage equipment according to the cache allocation information.

In this embodiment of the present application, the cache includes a plurality of cache memories, and the cache number determination submodule may specifically include the following units:

and the cache memory number determining unit is used for determining the number of cache memories to be allocated to the storage objects in the external storage device according to the number of cache memories required by different storage objects recorded in the cache allocation information.

In this embodiment, the allocating module 403 may specifically include the following sub-modules:

and the cache memory allocation submodule is used for allocating corresponding number of cache memories to the storage objects in the external storage equipment according to the number of the cache memories to be allocated to the storage objects.

In this embodiment of the present application, the cache memory allocation sub-module may specifically include the following units:

the access interface determining unit is used for determining an access interface corresponding to the storage object;

and the association configuration unit is used for associating and configuring the cache memory allocated to the storage object with the access interface.

For the apparatus embodiment, since it is substantially similar to the method embodiment, it is described relatively simply, and reference may be made to the description of the method embodiment section for relevant points.

Referring to fig. 5, a schematic diagram of a terminal device according to an embodiment of the present application is shown. As shown in fig. 5, the terminal device 500 of the present embodiment includes: a processor 510, a memory 520, and a computer program 521 stored in the memory 520 and executable on the processor 510. The processor 510 implements the steps in various embodiments of the above-described cache allocation control method, such as steps S101 to S103 shown in fig. 1, when executing the computer program 521. Alternatively, the processor 510, when executing the computer program 521, implements the functions of each module/unit in each device embodiment described above, for example, the functions of the modules 401 to 403 shown in fig. 4.

Illustratively, the computer program 521 may be partitioned into one or more modules/units that are stored in the memory 520 and executed by the processor 510 to accomplish the present application. The one or more modules/units may be a series of computer program instruction segments capable of performing specific functions, which may be used for describing the execution process of the computer program 521 in the terminal device 500. For example, the computer program 521 may be divided into an identification module, a determination module, and an assignment module, and each module has the following specific functions:

the identification module is used for identifying the storage type of the external storage equipment when the external storage equipment is detected;

the determining module is used for determining the cache quantity to be allocated to the external storage equipment according to the storage type of the external storage equipment;

and the distribution module is used for distributing the corresponding number of caches to the external storage equipment according to the number of the caches to be distributed to the external storage equipment.

The terminal device 500 may include, but is not limited to, a processor 510, a memory 520. Those skilled in the art will appreciate that fig. 5 is only an example of the terminal device 500, and does not constitute a limitation to the terminal device 500, and may include more or less components than those shown, or combine some components, or different components, for example, the terminal device 500 may further include an input-output device, a network access device, a bus, etc.

The Processor 510 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The storage 520 may be an internal storage unit of the terminal device 500, such as a hard disk or a memory of the terminal device 500. The memory 520 may also be an external storage device of the terminal device 500, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and so on, provided on the terminal device 500. Further, the memory 520 may also include both an internal storage unit and an external storage device of the terminal device 500. The memory 520 is used for storing the computer program 521 and other programs and data required by the terminal device 500. The memory 520 may also be used to temporarily store data that has been output or is to be output.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same. Although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.