阅读说明：本技术 一种具有背面双mos结构的快速关断rc-igbt器件 (Quick turn-off RC-IGBT device with back double-MOS structure ) 是由 陈伟中 黄垚 黄元熙 李顺 黄义 贺利军 张红升 于 2020-07-27 设计创作，主要内容包括：本发明涉及一种具有背面双MOS结构的快速关断RC-IGBT器件,属于半导体技术领域。该器件包括栅极接触区1、发射极接触区2、金属场板3、集电极接触区4、发射极5、元胞区P型阱6、过渡区P型阱7、第一场限环8、第二场限环9、第三场限环10、N型集电极11、N型缓冲层12、P型集电极13、N型漂移区14、栅氧化层15、场氧化层16、集电极氧化层17、场截止环接触区18、场截止环19、集电极P-base20。本发明在保证消除正向导通时的负阻效应的前提下,具有相对较快的关断速度和较低的Von、良好的反向导通性能及600V以上的耐压能力,提高了器件的工作稳定性和电流能力。(The invention relates to a quick turn-off RC-IGBT device with a back double-MOS structure, belonging to the technical field of semiconductors. The device comprises a grid contact region 1, an emitter contact region 2, a metal field plate 3, a collector contact region 4, an emitter 5, a cell region P-type well 6, a transition region P-type well 7, a first field limiting ring 8, a second field limiting ring 9, a third field limiting ring 10, an N-type collector 11, an N-type buffer layer 12, a P-type collector 13, an N-type drift region 14, a grid oxide layer 15, a field oxide layer 16, a collector oxide layer 17, a field stop ring contact region 18, a field stop ring 19 and a collector P-base 20. On the premise of ensuring that the negative resistance effect during forward conduction is eliminated, the invention has relatively high turn-off speed, low Von, good reverse conduction performance and over 600V withstand voltage capability, and improves the working stability and current capability of the device.)

1. A fast turn-off RC-IGBT device with a back double-MOS structure is characterized in that: comprises a cell portion, a transition region portion, a terminal portion and a collector portion;

the field stop ring structure comprises a grid contact region (1), an emitter contact region (2), a metal field plate (3), a collector contact region (4), an emitter (5), a cell region P-type well (6), a transition region P-type well (7), a first field limiting ring (8), a second field limiting ring (9), a third field limiting ring (10), an N-type collector (11), an N-type buffer layer (12), a P-type collector (13), an N-type drift region (14), a gate oxide layer (15), a field oxide layer (16), a collector oxide layer (17), a field stop ring contact region (18), a field stop ring (19) and a collector P-base (20);

1) the cellular part: five cellular structures with the same technical parameters are sequentially arranged from left to right, and each cellular structure comprises a grid (1), an emitter contact area (2), an emitter (5) and a cellular region P-type well (6); the rightmost cellular structure is close to the transition region P-type well (7); the upper surface of the emitter (5) is partially covered by the gate oxide layer (15), and the other part of the upper surface of the emitter is covered by the emitter contact region (2); the gate oxide layer (15) and the emitter contact area (2) are shared by two adjacent emitters (5); the upper surfaces of five completely identical cell region P-type wells (6) which are arranged side by side are flush with the upper surface of the N-type drift region (14), and the rest surfaces of the cell region P-type wells (6) are completely surrounded by the N-type drift region (14); the upper surfaces of the emitter (5) and the transition region P-type well (7) are flush with the cell region P-type well (6), and the rest surfaces are tightly surrounded by the cell region P-type well (6);

the gate contact region (1) is positioned on the gate oxide layer (15) and is in dielectric isolation with the emitter contact region (2), the N-type drift region (14), the cell region P-type well (6), the transition region P-type well (7) and the emitter (5); the left side and the right side of the emitter contact region (2) are closely adjacent to the gate oxide layer (15) or the field oxide layer (16) and cover the upper surfaces of the emitter (5), the cell region P-type well (6) or the transition region P-type well (7);

2) transition zone part: the transition region P-type well (7) is close to the rightmost end cellular P-type well (6), the rightmost sixth emitter (5) is located on the upper surface of the transition region P-type well (7), and the gate oxide layer (15) and the emitter contact region (2) cover the upper surface of the emitter (5); the upper surface of the transition region P-type well (7) is flush with the upper surface of the N-type drift region (14), and the rest surfaces of the transition region P-type well (7) are completely surrounded by the N-type drift region (14); the gate oxide layer (15) partially covers the upper surface of the N-type drift region (14), the rest part of the gate oxide layer respectively covers the upper surface of the emitter (5), and the upper surfaces of the cell region P-type well (6) or the transition region P-type well (7);

3) terminal portion: three same metal field plates (3) are sequentially arranged from left to right and respectively cover the middle parts of the surfaces of a first field limiting ring (8), a second field limiting ring (9) and a third field limiting ring (10) which are arranged below the same metal field plates, and the surfaces of the rest parts of the metal field plates (3) are in contact with a field oxide layer (16) and are not in direct contact with an N-type drift region (14); a field stop ring (19) is arranged at the rightmost side of the terminal; the upper surfaces of the first field limiting ring (8), the second field limiting ring (9) and the third field limiting ring (10) are flush with the upper surface of the N-type drift region (14), and the rest surfaces are completely surrounded by the N-type drift region (14); the field oxide layer (16) covers the upper surface of the right end of the P-type trap (7) in the transition region, the upper surfaces of the N-type drift region (14), the first field limiting ring (8), the second field limiting ring (9) and the third field limiting ring (10) and two sides of the upper surface of the N-type collector (11); the middle part of the upper surface of the field stop ring (19) is connected with a field stop ring contact region (18) in an upper field oxide layer (16) and is not directly contacted with the N-type drift region (14);

4) a collector portion: the upper surface and the right side surface of the left N-type collector (11) are in contact with the collector P-base region (20), and the upper surface and the left side surface of the right N-type collector (11) are in contact with the collector P-base region (20); the lower parts of the two N-type collectors (11) are in contact with a collector contact region (4); the upper surface of the left P-type collector (13) is in contact with the lower surface of the N-type buffer layer (12), the upper half part of the right side is in contact with a collector P-base region (20), and the lower half part of the right side is in contact with an N-type collector (11); the upper surface of the right P-type collector (13) is in contact with the lower surface of the N-type buffer layer (12), the upper half part of the left side is in contact with a collector P-base region (20), and the lower half part of the left side is in contact with an N-type collector (11); the left side and the right side of the middle P-type collector (13) are in contact with a collector oxide layer (17), the lower side of the middle P-type collector is in contact with a collector contact region (4), and the upper surface of the middle P-type collector is covered by an N-type buffer layer (12); the left part of the upper surface of the left collector oxide layer (17) is in contact with an N-type collector (11), the right part of the upper surface of the left collector oxide layer is in contact with a collector P-base (20), and the rest two sides of the upper surface of the left collector oxide layer are surrounded by a collector contact region (4); the right part of the upper surface of the right collector oxide layer (17) is in contact with an N-type collector (11), the left part of the upper surface of the right collector oxide layer is in contact with a collector P-base (20), and the rest two sides of the upper surface of the right collector oxide layer are surrounded by a collector contact region (4).

2. A fast turn-off RC-IGBT device with backside dual MOS structure according to claim 1, characterized in that: the left part, the middle part and the right part of the P-type collector (13) completely cover the upper surface of the collector contact region (4) and are in a shape of a middle depression; the N-type buffer layer (12) is also in a shape with a concave middle part; the N-type collector (11), the collector P-base (20) and the collector oxide layer (17) are divided into a left part and a right part which are symmetrically distributed by a perpendicular bisector at a concave position; the N-type buffer layer (12) is partially covered on the surface of the collector P-base (20); the N-type drift region (14) completely covers the upper surface of the whole concave N-type buffer layer (12).

3. A fast turn-off RC-IGBT device with backside dual MOS structure according to claim 1 or 2 characterized in that: the N-type drift region (14) takes P-type silicon as a substrate and needs certain processes such as etching, oxidation, ion implantation and the like.

4. A fast turn-off RC-IGBT device with backside dual MOS structure according to claim 1, characterized in that: the material of the gate contact region (1) comprises doped polysilicon.

5. A fast turn-off RC-IGBT device with backside dual MOS structure according to claim 1, characterized in that: the material of the emitter contact region (2) and the collector contact region (4) comprises aluminum silicon or aluminum silicon copper.

Technical Field

The invention belongs to the technical field of semiconductors, and relates to a quick turn-off RC-IGBT device with a back double-MOS structure.

Background

An Insulated Gate Bipolar Transistor (IGBT) is a composite fully-controlled voltage-driven power semiconductor device composed of a BJT (Bipolar Junction Transistor) Bipolar Transistor and a MOSFET (Metal-Oxide-semiconductor field-Effect Transistor) Insulated Gate field-Effect Transistor, and thus has the advantages of both high input impedance of the MOSFET and low on-state voltage drop of the BJT. The IGBT integrates the advantages of the two devices, and has small driving power and reduced saturation voltage. Therefore, it will become one of the core components of the smart power integrated circuit, and is widely applied in the fields of household electrical appliances, environmental protection automobiles, industrial production and the like, and is a semiconductor power device with great potential in the future market. However, the turn-off speed of the IGBT is much slower than that of a lateral double-diffused metal-oxide semiconductor field effect transistor (LDMOS), which results in large switching loss, and this seriously affects the application of the IGBT in a power integrated circuit. In addition, the IGBT structure is equivalent to two back-to-back diodes when conducting in reverse direction, and a PN junction formed by a P-type collector of the collector and an N-type buffer layer is always in a reverse bias state, so the IGBT does not have reverse conductivity. To circumvent this disadvantage, a free Wheeling diode fwd (free Wheeling diode) is usually connected in anti-parallel for protection in IGBT typical inverter circuit applications. However, conventional RC-IGBT devices also have some inherent disadvantages: first, because of the introduction of the N-type collector, the flow of electrons towards the collector contact region is blocked due to the fact that the heavily doped P-type collector is a high barrier for electrons flowing out of the emitter. Electrons flow first through the N-type buffer layer to the N-type collector portion of the collector, since an electron flow occurs between the N-type buffer layer and the P-type collectorA potential difference V_PN. This potential difference becomes the key for switching the conduction mode, only the electrons injected by the emitter participate in conduction when it is lower than the threshold voltage, and the RC-IGBT is in the unipolar conduction mode. While V is the value when the electron current flowing in the N-type buffer layer increases_PNWhen the threshold voltage is reached, the PN junction formed by the N-type buffer layer and the P-type collector electrode is opened, the P-type collector electrode injects holes into the drift region, the conversion of the conduction mode is realized, the negative resistance effect is caused in the process, the current and voltage are suddenly changed on the output curve, and the dynamic characteristic of the device is greatly influenced. This phenomenon can also hinder full turn-on of other devices in the circuitry when RC-LIGBTs are used in parallel at low temperatures.

Currently, there are three main methods for increasing the turn-off speed of the IGBT:

1) the service life of non-equilibrium carriers in the N-type drift region is reduced, and the recombination rate is increased to improve the turn-off speed. Generally, the lifetime of the non-equilibrium carriers in the drift region is reduced, and the total number of the non-equilibrium carriers is also reduced, so that the method causes the on-state voltage drop to be increased, and the method has the problem of the compromise between the off-state speed and the on-state voltage drop;

2) controlling a minority carrier injection level from the collector to the N-type drift region to achieve a compromise of on-resistance and off-time;

3) the collector provides an unbalanced carrier extraction channel, the total number of unbalanced carriers in the drift region is rapidly reduced during turn-off, so that the turn-off speed of the device is improved, and negative resistance effect is easy to occur during the turn-on process due to the conversion of the carriers from a unipolar turn-on mode to a bipolar turn-on mode.

There are two main ideas for eliminating the negative resistance effect: reducing the inherent resistance value of the N-type drift region before the conductance modulation occurs; secondly, increasing the resistance value above the P-type collector to ensure that the resistance value can reach the voltage drop enough for opening a PN junction formed by the P-type collector and the N-type buffer layer under very small current;

the optimization of turn-off loss and negative resistance effect based on the above method is aimed at. As shown in FIGS. 1 to 5: conventional collector short-circuited RC-IGBTThe structure of the RC-IGBT device is schematically represented, wherein the RC-IGBT device is formed by combining mass isolation and junction isolation, a tunnel injection type RC-IGBT device, a collector trench gate MCT type RC-IGBT device and a double-anode RC-IGBT device. In the existing design, the freewheeling diodes of the devices are longitudinally integrated in the cell regions, and the P-body of the cell region is used for providing a hole for the anode of the freewheeling diode, so that the voltage drop above the P-type collector is large when the freewheeling diode is turned off, the trailing current is long, the breakdown voltage BV is not ideal, and the turn-off loss E is high_offOr forward conduction voltage drop V_onAnd the like.

Disclosure of Invention

In view of the above, the present invention is directed to a fast turn-off RC-IGBT device with a back-side dual MOS structure, which can effectively eliminate the negative resistance effect and reduce V_onAnd E_off。

In order to achieve the purpose, the invention provides the following technical scheme:

a fast turn-off RC-IGBT device with a back double MOS structure comprises a cell part, a transition region part, a terminal part and a collector part;

the field stop ring structure comprises a grid contact region (1), an emitter contact region (2), a metal field plate (3), a collector contact region (4), an emitter (5), a cell region P-type well (6), a transition region P-type well (7), a first field limiting ring (8), a second field limiting ring (9), a third field limiting ring (10), an N-type collector (11), an N-type buffer layer (12), a P-type collector (13), an N-type drift region (14), a gate oxide layer (15), a field oxide layer (16), a collector oxide layer (17), a field stop ring contact region (18), a field stop ring (19) and a collector P-base (20);

1) the cellular part: five cellular structures with the same technical parameters are sequentially arranged from left to right, and each cellular structure comprises a grid (1), an emitter contact area (2), an emitter (5) and a cellular region P-type well (6); the rightmost cellular structure is close to the transition region P-type well (7); the upper surface of the emitter (5) is partially covered by the gate oxide layer (15), and the other part of the upper surface of the emitter is covered by the emitter contact region (2); the gate oxide layer (15) and the emitter contact area (2) are shared by two adjacent emitters (5); the upper surfaces of five completely identical cell region P-type wells (6) which are arranged side by side are flush with the upper surface of the N-type drift region (14), and the rest surfaces of the cell region P-type wells (6) are completely surrounded by the N-type drift region (14); the upper surfaces of the emitter (5) and the transition region P-type well (7) are flush with the cell region P-type well (6), and the rest surfaces are tightly surrounded by the cell region P-type well (6);

the gate contact region (1) is positioned on the gate oxide layer (15) and is in dielectric isolation with the emitter contact region (2), the N-type drift region (14), the cell region P-type well (6), the transition region P-type well (7) and the emitter (5); the left side and the right side of the emitter contact region (2) are closely adjacent to the gate oxide layer (15) or the field oxide layer (16) and cover the upper surfaces of the emitter (5), the cell region P-type well (6) or the transition region P-type well (7);

2) transition zone part: the transition region P-type well (7) is close to the rightmost end cellular P-type well (6), the rightmost sixth emitter (5) is located on the upper surface of the transition region P-type well (7), and the gate oxide layer (15) and the emitter contact region (2) cover the upper surface of the emitter (5); the upper surface of the transition region P-type well (7) is flush with the upper surface of the N-type drift region (14), and the rest surfaces of the transition region P-type well (7) are completely surrounded by the N-type drift region (14); the gate oxide layer (15) partially covers the upper surface of the N-type drift region (14), the rest part of the gate oxide layer respectively covers the upper surface of the emitter (5), and the upper surfaces of the cell region P-type well (6) or the transition region P-type well (7);

3) terminal portion: three same metal field plates (3) are sequentially arranged from left to right and respectively cover the middle parts of the surfaces of a first field limiting ring (8), a second field limiting ring (9) and a third field limiting ring (10) which are arranged below the same metal field plates, and the surfaces of the rest parts of the metal field plates (3) are in contact with a field oxide layer (16) and are not in direct contact with an N-type drift region (14); a field stop ring (19) is arranged at the rightmost side of the terminal; the upper surfaces of the first field limiting ring (8), the second field limiting ring (9) and the third field limiting ring (10) are flush with the upper surface of the N-type drift region (14), and the rest surfaces are completely surrounded by the N-type drift region (14); the field oxide layer (16) covers the upper surface of the right end of the P-type trap (7) in the transition region, the upper surfaces of the N-type drift region (14), the first field limiting ring (8), the second field limiting ring (9) and the third field limiting ring (10) and two sides of the upper surface of the N-type collector (11); the middle part of the upper surface of the field stop ring (19) is connected with a field stop ring contact region (18) in an upper field oxide layer (16) and is not directly contacted with the N-type drift region (14);

4) a collector portion: the upper surface and the right side surface of the left N-type collector (11) are in contact with the collector P-base region (20), and the upper surface and the left side surface of the right N-type collector (11) are in contact with the collector P-base region (20); the lower parts of the two N-type collectors (11) are in contact with a collector contact region (4); the upper surface of the left P-type collector (13) is in contact with the lower surface of the N-type buffer layer (12), the upper half part of the right side is in contact with a collector P-base region (20), and the lower half part of the right side is in contact with an N-type collector (11); the upper surface of the right P-type collector (13) is in contact with the lower surface of the N-type buffer layer (12), the upper half part of the left side is in contact with a collector P-base region (20), and the lower half part of the left side is in contact with an N-type collector (11); the left side and the right side of the middle P-type collector (13) are in contact with a collector oxide layer (17), the lower side of the middle P-type collector is in contact with a collector contact region (4), and the upper surface of the middle P-type collector is covered by an N-type buffer layer (12); the left part of the upper surface of the left collector oxide layer (17) is in contact with an N-type collector (11), the right part of the upper surface of the left collector oxide layer is in contact with a collector P-base (20), and the rest two sides of the upper surface of the left collector oxide layer are surrounded by a collector contact region (4); the right part of the upper surface of the right collector oxide layer (17) is in contact with an N-type collector (11), the left part of the upper surface of the right collector oxide layer is in contact with a collector P-base (20), and the rest two sides of the upper surface of the right collector oxide layer are surrounded by a collector contact region (4).

Optionally, the left, middle and right parts of the P-type collector (13) completely cover the upper surface of the collector contact region (4) and are in a shape of a middle recess; the N-type buffer layer (12) is also in a shape with a concave middle part; the N-type collector (11), the collector P-base (20) and the collector oxide layer (17) are divided into a left part and a right part which are symmetrically distributed by a perpendicular bisector at a concave position; the N-type buffer layer (12) is partially covered on the surface of the collector P-base (20); the N-type drift region (14) completely covers the upper surface of the whole concave N-type buffer layer (12).

Optionally, the N-type drift region (14) uses P-type silicon as a substrate, and certain processes such as etching, oxidation, ion implantation and the like are required.

Optionally, the material of the gate contact region (1) comprises doped polysilicon.

Optionally, the material of the emitter contact region (2) and the collector contact region (4) comprises aluminum silicon or aluminum silicon copper.

The invention has the beneficial effects that: the device is realized by integrating a freewheeling diode with an MOS structure in a transition region of the device and combining the design of a field limiting ring and a metal field plate technology, and meanwhile, an N-type collector of the MOS structure integrated in the transition region provides a quick short-circuit channel for non-equilibrium carriers to reduce turn-off loss E_offThe low-resistance channel from the N-type buffer layer to the N-type collector is blocked by the collector P-base, the short-circuit resistance of the P-type collector is increased, and the conductance modulation effect of the P-type collector is advanced, so that the negative resistance effect is favorably inhibited, and the conduction voltage drop V is reduced_on. In addition, the breakdown voltage of the device is almost as excellent as that of the traditional RC-IGBT. Therefore, the invention can reduce the total loss of the device during the working period and improve the working stability of the device. The invention has the following specific advantages:

1) and an additional driving circuit is not needed, so that the complexity of a peripheral circuit of the device and the packaging difficulty are reduced.

2) When the MOS structure of the transition region is turned off, the MOS structure of the transition region provides a fast N-type drift region electron extraction channel, and trailing current is effectively reduced, so that the turn-off loss E is reduced_offThe reduction is advantageous.

3) When conducting in forward direction, the low resistance channel of electrons under the condition of low current blocked by collector P-base increases the voltage drop of P-type collector to advance the conductance modulation effect, thus effectively inhibiting negative resistance effect and reducing conducting voltage drop V_on。

4) When the collector is conducted in the reverse direction, electrons emitted by the heavily doped N-type collectors in the forward bias states can submerge the P-base layer of the lightly doped collector. Flows to the P-type trap of the transition region as a freewheeling diode, and therefore has a reverse conduction voltage drop V_RLower.

Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the means of the instrumentalities and combinations particularly pointed out hereinafter.

Drawings

For the purposes of promoting a better understanding of the objects, aspects and advantages of the invention, reference will now be made to the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a schematic structural diagram of a conventional RC-IGBT device in the prior art;

FIG. 2 is a schematic structural diagram of an RC-IGBT device combining dielectric isolation and junction isolation in the prior art;

FIG. 3 is a schematic structural diagram of a tunnel injection type RC-IGBT device in the prior art;

FIG. 4 is a schematic structural diagram of a collector trench gate MCT type RC-IGBT device in the prior art;

FIG. 5 is a schematic structural diagram of a prior art double anode RC-IGBT device;

fig. 6 is a schematic structural diagram of embodiment 1 of the RC-IGBT device provided by the present invention;

fig. 7 is a schematic structural diagram of embodiment 2 of the RC-IGBT device provided by the present invention;

FIG. 8 shows RC-IGBT devices, DARC-IGBT devices and Con-RC-IGBT devices provided by the present invention in Nd-1 × 10¹⁴cm^-3A time breakdown voltage simulation comparison graph;

FIG. 9 shows the breakdown state of the RC-IGBT device, DARC-IGBT and Con-RC-IGBT device provided by the invention under Nd-1 × 10¹⁴cm^-3Two-dimensional electric field intensity contrast diagram at positions of time Y ═ 6 μm and Y ═ 15 μm

FIG. 10 shows the RC-IGBT device, DARC-IGBT and Con-RC-IGBT device provided by the present invention when Nd is 9 × 10¹³cm^-3To 1.3X 10¹⁴cm^-3A comparison graph of I-V characteristic curves in a reverse conduction state;

FIG. 11 shows the RC-IGBT device, DARC-IGBT and Con-RC-IGBT device provided by the present invention when Nd is 7 × 10¹³cm^-3To 3X 10¹⁴cm^-3Comparing I-V characteristic curves in a reverse conducting state;

FIG. 12 shows RC-IGBT devices, DARC-IGBT devices and Con-RC-IGBT devices provided by the present invention with Nd of 1 × 10¹⁴cm^-3A time-off characteristic curve comparison graph;

FIG. 13 is a schematic diagram of a main process flow of the RC-IGBT device provided by the present invention;

reference numerals: 1-grid contact region, 2-emitter contact region, 3-metal field plate, 4-collector contact region, 5-emitter, 6-cell region P-type well, 7-transition region P-type well, 8-first field limiting ring, 9-second field limiting ring, 10-third field limiting ring, 11-N type collector, 12-N type buffer layer, 13-P type collector, 14-N type drift region, 15-gate oxide layer, 16-field oxide layer, 17-collector oxide layer, 18-field stop ring contact region, 19-field stop ring, 20-collector P-base, 21-SiO₂The solar cell comprises a barrier layer, a 22-P-float layer, a 23-heavily doped N-type layer, a 24-heavily doped P-type layer, a 25-N-type polysilicon gate, a 26-P-type collector well and a 27-second anode.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention in a schematic way, and the features in the following embodiments and examples may be combined with each other without conflict.

Wherein the showings are for the purpose of illustrating the invention only and not for the purpose of limiting the same, and in which there is shown by way of illustration only and not in the drawings in which there is no intention to limit the invention thereto; to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.

The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar components; in the description of the present invention, it should be understood that if there is an orientation or positional relationship indicated by terms such as "upper", "lower", "left", "right", "front", "rear", etc., based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not an indication or suggestion that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes, and are not to be construed as limiting the present invention, and the specific meaning of the terms may be understood by those skilled in the art according to specific situations.