阅读说明：本技术 一种信号的边沿检测装置 (Signal edge detection device ) 是由 彭小卫 于 2019-04-22 设计创作，主要内容包括：本申请公开了一种信号的边沿检测装置,涉及电子电路领域,用以解决现有技术中检测方法比较单一的问题。本申请提供一种信号的边沿检测装置,所述装置包括：由指定数量的逻辑门器件构成的延时单元,以及检测单元；所述延时单元用于接收信号,并输出延迟指定时长的延时信号；所述检测单元用于对所述延迟信号和所述信号进行处理,得到检测信号；所述检测信号包括上升沿信号或下降沿信号。这样,通过使用一些逻辑门得到检测信号,在不需要时钟的情况下,即可完成对信号的边沿检测。(The application discloses an edge detection device of a signal, relates to the field of electronic circuits, and is used for solving the problem that a detection method in the prior art is single. The present application provides an edge detection apparatus for a signal, the apparatus comprising: the delay unit is composed of a specified number of logic gate devices, and the detection unit; the delay unit is used for receiving the signal and outputting a delay signal for delaying a specified duration; the detection unit is used for processing the delay signal and the signal to obtain a detection signal; the detection signal includes a rising edge signal or a falling edge signal. Thus, by using some logic gates to obtain the detection signal, the edge detection of the signal can be completed without a clock.)

1. An edge detection apparatus for a signal, the apparatus comprising: the delay unit is composed of a specified number of logic gate devices, and the detection unit;

the delay unit is used for receiving the signal and outputting a delay signal for delaying a specified duration;

the detection unit is used for processing the delay signal and the signal to obtain a detection signal; the detection signal includes a rising edge signal or a falling edge signal.

2. The apparatus of claim 1, wherein the logic gate device comprises at least one of: and gate, or gate, not gate.

3. The apparatus of claim 2, wherein if the delay unit is composed of at least 2 AND gates connected in series;

the signal is input to at least two input ends of a first AND gate connected in series;

except the first AND gate, the input end of each AND gate in the delay unit receives the output signal of the last AND gate.

4. The apparatus of claim 3, wherein the number of the input terminals of each AND gate in the delay unit is not less than 2, and the input signals input by the input terminals are the same.

5. The apparatus of claim 2, wherein if the delay unit is composed of at least 2 or gates connected in series;

the signal is input to one input end of a first OR gate in series connection;

except the first OR gate, the input end of each OR gate in the delay unit receives the output signal of the last OR gate.

6. The apparatus of claim 5, wherein the number of inputs of each OR gate in the delay unit is not less than 2, and 0 is input to other inputs except the input receiving the output signal of the last OR gate and the input receiving the signal.

7. The apparatus of claim 2, wherein if the delay unit is composed of at least 2 not gates connected in series; wherein, the number of the NOT gates is an even number;

the signal is input to the input end of a first NOT gate in series connection;

except the first NOT gate, the input end of each NOT gate in the delay unit receives the output signal of the last NOT gate.

8. The apparatus of claim 2, wherein if the delay unit is composed of at least 2 not gates, at least 1 and gate, and at least 1 or gate in series; wherein, the number of the NOT gates is an even number;

the signal is input to the input end of a first logic gate connected in series in the delay unit;

except the first logic gate, the input end of each logic gate in the delay unit receives the output signal of the last logic gate.

9. The apparatus of claim 1, wherein the detection unit comprises a first AND gate, a second AND gate, a first NOT gate, and a second NOT gate;

the first NOT gate is used for receiving the delay signal and outputting a first NOT gate output signal;

the first AND gate is used for receiving the signal and the first NOT gate output signal and outputting a rising edge signal;

the second NOT gate is used for receiving the signal and outputting a second NOT gate output signal;

and the second AND gate is used for receiving the delay signal and the second NOT gate output signal and outputting a falling edge signal.

10. A wake-up device, characterized in that the device comprises: an edge detector and chip for the signal of claim 1;

the signal edge detection device is used for sending awakening information to the chip if detecting a detection signal;

and the chip is used for entering an awakening state after receiving the awakening information sent by the edge detection device of the signal.

Technical Field

The present application relates to the field of electronic circuits, and more particularly, to an edge detector for signals.

Background

With the rapid development of semiconductor technology, the performance requirements of chips are higher and higher, the scale is larger and larger, and the power consumption of the chips is also rapidly increased. To provide product competitiveness, low power designs are becoming increasingly important, especially for battery powered mobile devices. After the chip enters low power consumption, the lower the power consumption, the better the chip can be on the premise of ensuring the awakening.

Under the condition of waking up by using an external key, a low-power-consumption clock is used for detecting the rising edge or the falling edge of a signal in the prior art, and once the change is detected, the chip is immediately woken up. However, in the prior art, the method for edge detection of signals by using a low-power-consumption clock needs to use a clock generator, and the detection method is relatively single.

Disclosure of Invention

The embodiment of the application provides a signal edge detection device, and provides a new method for edge detection of signals, so as to solve the problem that the detection method in the prior art is single.

In order to achieve the purpose, the invention provides the following technical scheme:

an edge detection apparatus for a signal, the apparatus comprising: the delay unit is composed of a specified number of logic gate devices, and the detection unit;

the delay unit is used for receiving the signal and outputting a delay signal for delaying a specified duration;

the detection unit is used for processing the delay signal and the signal to obtain a detection signal; the detection signal includes a rising edge signal or a falling edge signal.

The edge detection device of the signal comprises a delay unit and a detection unit, wherein the signal outputs a delay signal through the delay unit, and the output delay signal and the signal pass through the detection unit to obtain a detection signal. Thus, by using some logic gates to obtain the detection signal, the edge detection of the signal can be completed without a clock.

Further, the logic gate device comprises at least one of: and gate, or gate, not gate.

Further, if the delay unit is formed by connecting at least 2 AND gates in series;

the signal is input to at least two input ends of a first AND gate connected in series;

except the first AND gate, the input end of each AND gate in the delay unit receives the output signal of the last AND gate.

Furthermore, the number of the input ends of each and gate in the delay unit is not less than 2, and the input signals input by each input end are the same.

Further, if the delay unit is formed by connecting at least 2 or gates in series;

the signal is input to one input end of a first OR gate in series connection;

except the first OR gate, the input end of each OR gate in the delay unit receives the output signal of the last OR gate.

Further, the number of the input terminals of each or gate in the delay unit is not less than 2, and except for the input terminal receiving the output signal of the last or gate and the input terminal receiving the signal, 0 is input to the other input terminals.

Further, if the delay unit is formed by connecting at least 2 NOT gates in series; wherein, the number of the NOT gates is an even number;

the signal is input to the input end of a first NOT gate in series connection;

except the first NOT gate, the input end of each NOT gate in the delay unit receives the output signal of the last NOT gate.

Further, if the delay unit is formed by connecting at least 2 not gates, at least 1 and gate and at least 1 or gate in series; wherein, the number of the NOT gates is an even number;

the signal is input to the input end of a first logic gate connected in series in the delay unit;

except the first logic gate, the input end of each logic gate in the delay unit receives the output signal of the last logic gate.

Further, the detection unit comprises a first and gate, a second and gate, a first not gate and a second not gate;

the first NOT gate is used for receiving the delay signal and outputting a first NOT gate output signal;

the first AND gate is used for receiving the signal and the first NOT gate output signal and outputting a rising edge signal;

the second NOT gate is used for receiving the signal and outputting a second NOT gate output signal;

and the second AND gate is used for receiving the delay signal and the second NOT gate output signal and outputting a falling edge signal.

The present invention also provides a wake-up apparatus, the apparatus comprising: an edge detector and chip for the signal as recited in claim 1;

the signal edge detection device is used for sending awakening information to the chip if detecting a detection signal;

and the chip is used for entering an awakening state after receiving the awakening information sent by the edge detection device of the signal.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:

FIG. 1 is a schematic diagram illustrating an implementation principle of edge detection in the prior art according to an embodiment of the present application;

FIG. 2 is a diagram illustrating a waveform of a prior art rising edge detection in an embodiment of the present application;

FIG. 3 is a diagram illustrating a falling edge detection waveform in the prior art in an embodiment of the present application;

FIG. 4 is a diagram of an edge detection apparatus for detecting a signal according to an embodiment of the present application;

FIG. 5 is a block diagram of an edge detection apparatus for detecting a signal of a delay unit formed by connecting at least 2 AND gates in series according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of a delay unit formed by at least 2 and gates connected in series in the embodiment of the present application;

FIG. 7 is a diagram of an edge detection apparatus for detecting a signal of a delay cell formed by at least 2 OR gates connected in series according to an embodiment of the present invention;

FIG. 8 is a schematic structural diagram of a delay unit formed by at least 2 OR gates connected in series in the embodiment of the present application;

FIG. 9 is a block diagram of an edge detection apparatus for detecting a signal of a delay unit formed by connecting at least 2 NOT gates in series according to an embodiment of the present invention;

FIG. 10 is a diagram of an edge detection apparatus for detecting a signal of a delay cell formed by a plurality of logic gates connected in series according to an embodiment of the present invention;

FIG. 11 is a schematic diagram of a rising edge detection waveform of an edge detection apparatus for signals in an embodiment of the present application;

fig. 12 is a schematic diagram of a falling edge detection waveform of the edge detection apparatus of the signal in the embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

At present, in the prior art, a low-power-consumption clock is used for detecting a rising edge or a falling edge of a signal, and once a change is detected, a chip is immediately awakened. As shown in fig. 1, it is a schematic diagram of an edge detection in the prior art. And the delay of the signals is realized through two stages of D trigger register. The pulse is a signal, clk is a low-power-consumption clock, rst _ n is a reset signal, pos _ edge is a detected rising edge signal, neg _ edge is a detected falling edge signal, s1 is a process signal output by the D flip-flop 1 receiving a signal and a clock signal, s2 is a process signal output by the D flip-flop 2 receiving an s1 process signal and a clock signal, s3 is a process signal output by the s2 process signal through the not gate 1, and s4 is a process signal output by the signal through the not gate 2.

If rising edge detection is used, the resulting waveform diagram is shown in FIG. 2. When a signal is input, s1 is obtained by the output of the D flip-flop 1, s1 is input to the D flip-flop 2, s2 is obtained by the output, s3 is obtained by the output of the s2 through the not gate 1, and the pos _ edge signal is obtained by passing the sum of s3 and the signal through the and gate 1.

If falling edge detection is used, the resulting waveform diagram is shown in FIG. 3. When a signal is input, s1 is output through the D flip-flop 1, s1 is input into the D flip-flop 2, s2 is output, s4 is output through the NOT gate 2, and s2 and s4 are output through the AND gate 2, so that a neg _ edge signal is obtained.

However, in the prior art, since a clock generator is needed when performing edge detection, and the clock causes the gate to flip, the chip still generates much power consumption when operating with low power consumption. The invention provides a signal edge detection device, which is used for solving the problem that the detection method in the prior art is single, and simultaneously, because the edge detection is realized by using some logic gates, a clock is not needed, so that the power consumption of a chip in a low power consumption mode can be reduced to the minimum. The device comprises: the delay unit is composed of a specified number of logic gate devices, and the detection unit;

the delay unit is used for receiving the signal and outputting a delay signal for delaying a specified duration;

the detection unit is used for processing the delay signal and the signal to obtain a detection signal; the detection signal includes a rising edge signal or a falling edge signal.

The edge detection device of the signal comprises a delay unit and a detection unit, wherein the signal outputs a delay signal through the delay unit, and the output delay signal and the signal pass through the detection unit to obtain a detection signal. Thus, by using some logic gates to obtain the detection signal, the edge detection of the signal can be completed without a clock. Meanwhile, the power consumption of the chip in the low power consumption mode can be reduced to the minimum because the clock is not needed.

Wherein the edge detection means of said signal is shown in fig. 4. Where, pulse is a signal, pos _ edge is a detected rising edge signal, neg _ edge is a detected falling edge signal, s1 is a delay signal output by the delay unit, s2 is a first not gate output signal output by s1 through the first not gate, and s3 is a second not gate output signal output by the second not gate.

In the embodiment of the present application, the delay unit is composed of a specified number of logic gate devices, and the logic gate devices include at least one of the following: and gate, or gate, not gate.

In order to effectively wake up the chip system, the delay unit may be formed by serially connecting a plurality of logic gate devices. Due to the influence of factors such as process and applied voltage, the delay of each logic gate is different, and the delay of a single logic gate is small. The multi-gate inverter can be formed by connecting a plurality of AND gates in series, a plurality of OR gates in series, a plurality of NOT gates in series, a plurality of AND gates and OR gates in series, a plurality of AND gates and NOT gates in series, and a plurality of OR gates and NOT gates in series.

It should be noted that, if there are not gates in the delay unit, it is necessary to ensure that the number of the not gates is even.

In the embodiment of the present application, if the delay unit is formed by connecting at least 2 and gates in series, a schematic diagram of the implementation of clock-free edge detection is shown in fig. 5.

The signal is input to at least two input ends of a first AND gate connected in series;

except the first AND gate, the input end of each AND gate in the delay unit receives the output signal of the last AND gate.

As shown in fig. 6, the number of the input terminals of each and gate in the delay unit is not less than 2, and the number of the input terminals of each and gate in the delay unit may be 2, 3, or multiple. Of course, the inputs of the and gates in the delay unit may all be the same, for example, the inputs of the and gates are all 2. And the input signals input by the input ends are the same. Therefore, the delay unit formed by connecting a plurality of AND gates in series still realizes the edge detection of signals under the condition of not needing clocks, and reduces the power consumption of the chip under a low power consumption mode to the minimum.

In the embodiment of the present application, if the delay unit is formed by connecting at least 2 or gates in series, the schematic diagram of the implementation of clock-free edge detection is shown in fig. 7.

The signal is input to one input end of a first OR gate in series connection;

except the first OR gate, the input end of each OR gate in the delay unit receives the output signal of the last OR gate.

As shown in fig. 8, the number of the input ends of each or gate in the delay unit is not less than 2, and the number of the input ends of each and gate in the delay unit may be 2, 3, or multiple. Of course, the inputs of the or gates in the delay units may all be the same, for example, the inputs of the or gates are all 2. And the other input terminals input 0, except for the input terminal receiving the output signal of the last or gate and the input terminal receiving the signal. Therefore, the delay unit formed by connecting a plurality of OR gates in series still realizes the edge detection of signals under the condition of not needing a clock, and reduces the power consumption of the chip under the low power consumption mode to the minimum.

In the embodiment of the present application, if the delay unit is formed by connecting at least 2 not gates in series, the schematic diagram of the implementation of clock-free edge detection is shown in fig. 9; wherein, the number of the NOT gates is an even number;

the signal is input to the input end of a first NOT gate in series connection;

except the first NOT gate, the input end of each NOT gate in the delay unit receives the output signal of the last NOT gate.

Thus, the edge detection of the signal is still realized by the delay unit formed by connecting a plurality of NOT gates in series under the condition of not needing a clock, and the power consumption of the chip in a low power consumption mode is reduced to the minimum.

In the embodiment of the present application, if the delay unit is formed by connecting at least 2 not gates, at least 1 and gate, and at least 1 or gate in series, the schematic diagram of the implementation of clock-free edge detection is shown in fig. 10; wherein, the number of the NOT gates is an even number;

the signal is input to the input end of a first logic gate connected in series in the delay unit;

except the first logic gate, the input end of each logic gate in the delay unit receives the output signal of the last logic gate.

Thus, the edge detection of the signal is still realized by the delay unit formed by connecting a plurality of NOT gates in series under the condition of not needing a clock, and the power consumption of the chip in a low power consumption mode is reduced to the minimum.

After the signal passes through the delay unit to output the delay signal, the detection signal is obtained through the detection unit. The detection unit comprises a first AND gate, a second AND gate, a first NOT gate and a second NOT gate;

the first and gate and the first not gate constitute rising edge detection, and if the rising edge detection is used, the obtained waveform diagram is shown in fig. 11.

The first NOT gate is used for receiving the delay signal and outputting a first NOT gate output signal;

the first AND gate is used for receiving the signal and the first NOT gate output signal and outputting a rising edge signal;

the second and gate and the second not gate constitute falling edge detection, and if falling edge detection is used, the obtained waveform diagram is shown in fig. 12.

The second NOT gate is used for receiving the signal and outputting a second NOT gate output signal;

and the second AND gate is used for receiving the delay signal and the second NOT gate output signal and outputting a falling edge signal.

The present application further provides a wake-up apparatus, the apparatus comprising: edge detection devices and chips for signals as described above;

the signal edge detection device is used for sending awakening information to the chip if detecting a detection signal;

and the chip is used for entering an awakening state after receiving the awakening information sent by the edge detection device of the signal.

Therefore, under the condition of not needing a clock, the edge detection device of the signal obtains the detection signal, realizes the edge detection of the signal and reduces the power consumption of the chip under the low power consumption mode to the minimum.

It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.