阅读说明：本技术 一种上电时序检测装置及方法 (Power-on time sequence detection device and method ) 是由 许龙飞 康明勇 毛明春 于 2020-07-09 设计创作，主要内容包括：本发明提供了一种结构简单、成本低且时间分辨率高的上电时序检测装置及方法。本发明所述上电时序检测装置包括2n路缓冲器(1)、n路模拟开关(2)、n路比较器(3)、n路DAC(4)、1路ADC(5)和MCU(6)；其检测方法为：输入上电时序待测信号到比较器；MCU通过DAC设置好每个输入通道的触发电压,并在第一个通道触发的时刻开启计时器；在每个通道被触发时记录相应的时间；通过模拟开关和ADC检测上电时序待测信号的波形；以任意两个时间差和波形幅值大小作为上电时序的判定依据,测得设备的上电时序。本发明可应用于测试领域。(The invention provides a power-on time sequence detection device and a power-on time sequence detection method which are simple in structure, low in cost and high in time resolution. The power-on time sequence detection device comprises 2n paths of buffers (1), n paths of analog switches (2), n paths of comparators (3), n paths of DACs (4), 1 path of ADC (5) and an MCU (6); the detection method comprises the following steps: inputting a power-on sequence signal to be detected to a comparator; the MCU sets the trigger voltage of each input channel through the DAC, and starts a timer at the moment of triggering the first channel; recording the corresponding time when each channel is triggered; detecting the waveform of a signal to be detected in the power-on time sequence through an analog switch and an ADC (analog-to-digital converter); and measuring the power-on time sequence of the equipment by taking any two time differences and the amplitude of the waveform as the judgment basis of the power-on time sequence. The invention can be applied to the field of testing.)

1. A power-on time sequence detection device is set to detect a signal to be detected of a power-on time sequence on n circuits, and is characterized in that: the device comprises 2n paths of buffers (1), n paths of analog switches (2), n paths of comparators (3), n paths of DACs (4), 1 path of ADCs (5) and an MCU (6), wherein each two paths of buffers (1) are respectively correspondingly connected with one path of input signals to be tested, the output end of the n paths of buffers (1) is connected with the input end of the n paths of analog switches (2), the output end of the other n paths of buffers (1) is connected with the positive phase input end of the n paths of comparators (3), the output end of the n paths of analog switches (2) is connected with the input end of the ADC (5), the ADC (5) is connected with an SPI port of the MCU (6), the channel selection bits (A0, A1 and A2) of the analog switches (2) are connected with GPIO ports (GPIO _0, GPIO _1, GPIO _ 2) of the MCU (6), and the input end of the n paths of the DACs (4) is connected with the MCU (6), the output ends of the n paths of DACs (4) are respectively connected with the negative phase input ends of the n paths of comparators (3), the output ends of the n paths of comparators (3) are connected with the trigger points of the MCU (6), the MCU (6) is connected with a peripheral upper computer, and n is the number of signals to be detected of the power-on time sequence.

2. The power-on timing detecting apparatus according to claim 1, wherein: the power-on time sequence signal to be detected is a power-on voltage signal.

3. A method for detecting a power-on sequence of a device by using the power-on sequence detecting apparatus as claimed in claim 1, the method comprising the steps of:

a. the n paths of signals to be detected of the electrical time sequence are respectively input into n input channels, and reach the positive phase input end of the comparator (3) after being buffered by the buffer (1);

b. the MCU (6) sets the trigger voltage of each input channel through n paths of the DAC (4), and starts a timer at the moment when the first channel is triggered;

c. when the second channel is triggered, recording the current time T1, when the third channel is triggered, recording the current time as T2, and accordingly, recording the current time as Tn-1 until the nth channel is triggered, and respectively obtaining the times T2, T3, … and Tn-1, wherein n is the number of signals to be tested in the power-on time sequence;

d.n paths of power-on time sequence signals to be detected after being buffered by the buffer (1) enter n paths of analog switches (2), the MCU (6) selects an input channel of the signals through the channel selection bits (A0, A1 and A2), then the ADC (5) is started through the SPI to perform analog-to-digital conversion and read an analog-to-digital conversion value, then the analog-to-digital conversion value is stored in the upper computer, and the upper computer restores the waveforms of the n paths of power-on time sequence signals to be detected by analyzing data after data acquisition is completed;

e. at the moment, the power-on time sequence of the equipment is measured by taking any two time differences and the amplitude of the waveform as the judgment basis of the power-on time sequence.

Technical Field

The invention relates to the field of testing, in particular to a power-on time sequence detection device and method.

Background

With the advancement of technology and the application of large-scale integrated circuits, the power-on timing of a chip becomes an important detection index of a product. When the work performance of a product is tested, the power-on time sequence of the tested product is often required to be measured so as to detect whether the power supply of the tested product works normally. The abnormal power-on time sequence of the chip can cause abnormal work and even damage of the product, so the power-on time sequence of the product needs to be detected.

Disclosure of Invention

The technical problem to be solved by the invention is to overcome the defects of the prior art and provide a power-on time sequence detection device with simple structure, low cost and high time resolution.

The invention also provides a method for detecting the electric time sequence by using the power-on time sequence detection device, which has the advantages of simple process, high test precision and low cost.

The technical scheme adopted by the power-on time sequence detection device is that the power-on time sequence detection device is set to detect n paths of power-on time sequence signals to be detected and comprises 2n paths of buffers, n paths of analog switches, n paths of comparators, n paths of DACs, 1 path of ADCs and an MCU, wherein each two paths of buffers are respectively and correspondingly connected with one path of input signals to be detected, the output ends of the n paths of buffers are connected with the input ends of the n paths of analog switches, the output ends of the n paths of buffers are connected with the positive input ends of the n paths of comparators, the output ends of the n paths of analog switches are connected with the input ends of the ADCs, the ADCs are connected with SPI ports of the MCU, the channel selection bits of the analog switches are connected with GPIO ports of the MCU, the input ends of the n paths of DACs are connected with the MCU, and the output ends of the n paths of DACs are respectively connected with the negative input ends of the n paths of the comparators, the output ends of the n paths of comparators are connected with the trigger points of the MCU, the MCU is connected with a peripheral upper computer, and n is the number of signals to be tested of the power-on time sequence.

Further, the power-on time sequence signal to be tested is a power-on voltage signal.

The method for detecting the power-on time sequence of the equipment by using the power-on time sequence detection device comprises the following steps:

a. the n paths of signals to be detected of the on-line time sequence are respectively input into n input channels, and reach the positive phase input end of the comparator after being buffered by the buffer;

b. the MCU sets the trigger voltage of each input channel through n paths of DACs, and starts a timer at the moment when the first channel is triggered;

c. when the second channel is triggered, recording the current time T1, when the third channel is triggered, recording the current time as T2, and accordingly, recording the current time as Tn-1 until the nth channel is triggered, and respectively obtaining the times T2, T3, … and Tn-1, wherein n is the number of signals to be tested in the power-on time sequence;

d.n paths of power-on time sequence signals to be detected after being buffered by the buffer enter n paths of analog switches, the MCU selects an input channel of the signals through the channel, then starts the ADC through the SPI to perform analog-to-digital conversion and reads the value of the analog-to-digital conversion, then the value of the analog-to-digital conversion is stored in the upper computer, and the upper computer recovers the waveform of the n paths of power-on time sequence signals to be detected through analyzing data after data acquisition is completed;

e. at the moment, the power-on time sequence of the equipment is measured by taking any two time differences and the amplitude of the waveform as the judgment basis of the power-on time sequence.

The invention has the beneficial effects that: in the invention, a buffer is utilized to buffer, filter and denoise a power-on sequence signal to be detected, an MCU sets a trigger voltage of each input channel through n paths of DACs, a timer is started at the moment of triggering of a first channel, the current time T1 is recorded when a second channel is triggered, the current time T2 is recorded when a third channel is triggered, and accordingly, n-1 times are obtained until the nth channel is triggered; after a signal is input into an analog switch, an MCU selects an input channel of the signal through a channel selection bit, then starts an ADC through an SPI (serial peripheral interface) to perform analog-to-digital conversion and read an analog-to-digital conversion value, then stores the analog-to-digital conversion value into an upper computer, and after data acquisition is finished, the upper computer recovers the waveform of a signal to be tested of a power-on time sequence through analyzing data, and at the moment, the power-on time sequence of the equipment is tested by taking any two time differences and the amplitude of the waveform as the judgment basis of the power-on time; the invention solves the time measurement problem under high time resolution by adopting a hardware triggering mode, and can realize accurate measurement of the power-on time sequence on the premise of not increasing the ADC sampling rate. The hardware triggering mode is adopted, so that higher time resolution can be realized, the sampling rate of the ADC does not need to be increased, and the hardware cost and the design difficulty are reduced.

Drawings

Fig. 1 is a block diagram of the principle architecture of the present invention.

Detailed Description

As shown in fig. 1, the present invention sets the power-on timing detecting apparatus to detect n paths of power-on timing signals to be detected. The power-on time sequence signal to be detected is a power-on voltage signal. In this embodiment, the value of n is 8, that is, the power-on timing sequence detection is performed on 8 channels of signals to be detected. The device comprises 16 paths of buffers 1, 8 paths of analog switches 2, 8 paths of comparators 3, 8 paths of DAC 4, 1 path of ADC 5 and an MCU6, wherein each two paths of buffers 1 are respectively correspondingly connected with one path of input signals to be tested, the output end of the 8 paths of buffers 1 is connected with the input end of the 8 paths of analog switches 2, in addition, the output end of the 8 paths of buffers 1 is connected with the positive phase input end of the 8 paths of comparators 3, the output end of the 8 paths of analog switches 2 is connected with the input end of the ADC 5, the ADC 5 is connected with the SPI port of the MCU6, the channel selection bits A0, A1 and A2 of the analog switches 2 are connected with the GPIO ports GPIO _0, GPIO _1 and GPIO _2 of the MCU6, the input end of the 8 paths of DAC 4 is connected with the MCU6, and the output ends of the 8 paths of DAC 4 are respectively connected with the negative phase input ends of the 8 paths of the comparators 3, the output end of the comparator 3 is connected with the trigger point of the MCU6, and the MCU6 is connected with a peripheral upper computer.

In the invention, the buffer 1 is used for impedance transformation, and the chip model is OPA 4354; the analog switch 2 is used for selecting an input channel, and the chip model of the analog switch is SN74LV 4051; the comparator 3 is used for input signal amplitude detection, and the chip model is TLV 3502; the DAC 4 is used for setting a trigger threshold, and the chip model is AD 5629; the ADC 5 is used for analog-to-digital conversion, and the chip model is AD 7175; the MCU6 is used for selecting an input channel, setting a trigger threshold, reading an ADC value and communicating with an upper computer, and the chip model of the MCU is STM32F 407.

The method for detecting the power-on time sequence of the equipment by the power-on time sequence detection device comprises the following steps:

a. the 8 paths of signals to be detected of the electrical time sequence are respectively input into 8 input channels, and reach the positive phase input end of the comparator 3 after being buffered by the buffer 1;

b. the MCU6 sets the trigger voltage of each input channel through 8 paths of the DAC 4 and starts a timer at the moment of triggering the first channel;

c. when the second channel is triggered, recording the current time T1, when the third channel is triggered, recording the current time T2, and accordingly, recording the current time T7 until the 8 th channel is triggered, and respectively obtaining the time T2, the time T3, the time T … and the time T7;

d.8 paths of power-on time sequence signals to be detected after being buffered by the buffer 1 enter 8 paths of analog switches 2, the MCU6 selects input channels of the signals through the channel selection bits A0, A1 and A2, then the ADC 5 is started through the SPI to perform analog-to-digital conversion and read analog-to-digital conversion values, then the analog-to-digital conversion values are stored in the upper computer, and the upper computer recovers waveforms of the 8 paths of power-on time sequence signals to be detected through analyzing data after data acquisition is completed;

e. at the moment, the power-on time sequence of the equipment is measured by taking any two time differences and the amplitude of the waveform as the judgment basis of the power-on time sequence.

The invention solves the time measurement problem under high time resolution by adopting a hardware triggering mode, and can realize accurate measurement of the power-on time sequence on the premise of not increasing the ADC sampling rate. The hardware triggering mode is adopted, so that higher time resolution can be realized, the sampling rate of the ADC does not need to be increased, and the hardware cost and the design difficulty are reduced.