阅读说明：本技术 静电放电防护结构 (Electrostatic discharge protection structure ) 是由 德瑞坦·瑟娄 多米尼克·约翰·古德威尔 艾瑞克·伯尼尔 于 2016-10-27 设计创作，主要内容包括：提供了用于基于光子平台的光电二极管系统的静电放电防护结构。具体地,本申请提供了光电二极管组件,该光电二极管组件包括：光电二极管(如Si或SiGe光电二极管)；波导(212)(如硅波导)；以及防护结构,其中,该防护结构包括二极管,该防护结构围绕Si或SiGe光电二极管的全部周围或基本上全部周围延伸并且允许来自硅波导(212)的光传播到Si或SiGe光电二极管中。(An electrostatic discharge protection structure for a photonic platform based photodiode system is provided. Specifically, the present application provides a photodiode assembly comprising: photodiodes (e.g., Si or SiGe photodiodes); a waveguide (212) (e.g., a silicon waveguide); and a guard structure, wherein the guard structure comprises a diode, the guard structure extending around all or substantially all of a circumference of the Si or SiGe photodiode and allowing light from the silicon waveguide (212) to propagate into the Si or SiGe photodiode.)

1. A photodiode assembly comprising:

the photodiode comprises a p-doped region, an n-doped region and an intrinsic region positioned between the p-doped region and the n-doped region, wherein the three regions are positioned on different planes;

a waveguide in communication with the photodiode;

and the protective structure surrounds the photodiode and is positioned in a different plane from at least one of the p-doped region, the n-doped region and the intrinsic region, wherein the protective structure is a diode structure.

2. The photodiode assembly of claim 1, wherein the shielding structure is any one of the following structures:

a lateral junction diode guard ring, a silicon-on-insulator (SOI) gated diode guard ring, and a double-well field effect diode guard ring.

3. The photodiode assembly of claim 1 or 2, wherein the guard structure comprises a heavily doped silicon p-region for charge transport.

4. The photodiode assembly of any of claims 1-3, wherein the guard structure has an opening corresponding to an entrance of the waveguide to the photodiode.

5. The photodiode assembly of claim 4, wherein the opening and the inlet correspond in a direction perpendicular to a plane of the waveguide.

6. The photodiode assembly of claim 4 or 5, wherein the number of openings is two.

7. The photodiode assembly of any one of claims 4-6, further comprising a conductive wire for electrically connecting the guard structures on either side of the opening.

8. The photodiode assembly of any one of claims 4-7, wherein the opening is filled with a material that is optically transparent at a wavelength of light detected by the photodiode.

9. The photodiode assembly of any one of claims 1-8, wherein a current transport direction of the photodiode is at an angle to a current transport direction of the guard structure.

10. The photodiode assembly of claim 9, wherein a current transport direction of the photodiode is perpendicular to a current transport direction of the guard structure.

11. The photodiode assembly of any one of claims 1-10, wherein the guard structure is coplanar with the waveguide, the guard structure comprising at least one of:

a gap;

a structure that is substantially optically transparent at the wavelength of light detected by the photodiode.

12. The photodiode assembly of any one of claims 1-10, wherein the guard structure is non-coplanar with the waveguide, the guard structure comprising at least one of:

the guard structure is disposed in a plane parallel to the plane of the waveguide and sufficiently spaced from the waveguide such that the guard structure does not substantially absorb light at the wavelength of light detected by the photodiode;

the guard structure comprises a gap; and

the guard structure includes a structure that is substantially optically transparent at the wavelength of light detected by the photodiode.

13. The photodiode assembly of any one of claims 1-12, wherein the photodiode comprises Si, SiGe, a III-V material, or a combination thereof.

14. The photodiode assembly of any of claims 1-13, wherein the guard structure comprises Si, Ge, SiGe, a III-V material, or any combination thereof.

15. The photodiode assembly of any of claims 1-14, wherein the waveguide comprises a silicon waveguide.

Technical Field

The present application belongs to the field of photonics. More particularly, the present application relates to photodiodes and methods of making and using the same.

Background

A Photodiode (PD) is a semiconductor photodetector capable of converting light into a current or voltage.

The most commonly used photodetectors are positive-negative (p-n) photodiodes, positive-intrinsic-negative (p-i-n) photodiodes, and avalanche photodiodes.

Photons absorbed at the p-n junction of a p-n PD or at the intrinsic region or i-region of a p-i-n photodiode generate a pair of current carriers-holes in the valence band and electrons in the conduction band-that drift toward the respective p-doped and n-doped regions. Incident light generates a photocurrent, where the voltage output is monotonically dependent on the amount of incident light. In its simplest form an avalanche photodiode is a p-i-n diode to which a very high reverse bias voltage is applied. More advanced avalanche photodiodes include an additional layer called a multiplication layer in which current carriers are multiplied by a process called impact ionization.

Due to its simplicity, compactness and ease of operation, PDs have been widely used in consumer electronics devices such as compact disc players, smoke detectors, and receivers for remote control in DVD players and televisions. PD is often used for the accurate measurement of optical power in science and industry as well as in various medical applications. In an optical communication system, a PD is used to convert an optical signal into an electrical signal.

Electrostatic discharge (ESD) from adjacent objects, such as the human body, is a major cause of electronic Integrated Circuits (ICs) and optoelectronic device failure. ESD has been well studied and standardized for IC and non-silicon based optoelectronic components. In particular, ESD sensitivity has been reported for non-silicon optoelectronic components such as laser diodes, light emitting diodes and InGaAs photodiodes.

To protect the photodiode from ESD, electronics manufacturers control air humidity, provide ground and mesa grounding, and introduce special packaging processes and materials. These measures are expensive to implement, are not fully effective, and are sometimes difficult to detect with residual ESD damage. Furthermore, if similar precautions are not taken, the ESD can damage the PD at the customer site.

For optical platform based systems such as silicon photonics (SiPh) with co-packaged (non-monolithic) drive circuitry, the previous disclosure states that ESD protection should be included. However, to date, these disclosures provide no guidance on how to achieve ESD protection against SiPh; furthermore, these publications do not disclose or suggest the design or fabrication of any photonic element that includes ESD protection.

Therefore, ESD protection is required for the SiPh system.

The above information is provided for the purpose of forming known information believed by the applicant to be of possible relevance to the present invention. No admission is necessarily intended, nor should be construed, as: any of the above information constitutes prior art against the present invention.

Disclosure of Invention

It is an object of the present application to provide electrostatic discharge protection for silicon photodiode systems.

According to an aspect of the present application, there is provided a photodiode assembly including: a photodiode; a waveguide (e.g., a silicon waveguide) in communication with the photodiode; and a guard structure, wherein the guard structure extends around substantially all of a circumference of the photodiode and includes a diode, wherein when the guard structure is coplanar with the waveguide, the guard structure includes at least one of:

a gap; and

a structure that is substantially optically transparent at a wavelength of light capable of being detected by the photodiode, an

Wherein, when the guard structure is not coplanar with the waveguide, at least one of:

the guard structure is disposed in a plane parallel to the plane of the waveguide and is sufficiently spaced from the waveguide such that the guard structure does not substantially absorb light at a wavelength of light detectable by the photodiode;

the protective structure comprises a gap; and

the protective structure comprises a structure that is substantially optically transparent at the wavelength of light that can be detected by the photodiode.

In some embodiments, the photodiode is a vertical PIN diode. In other embodiments, the photodiode is a PN lateral junction diode.

In some embodiments, the photodiodes of the photodiode assemblies described above are composed of Si, SiGe, III-V materials, or any combination thereof.

In some embodiments, the guard structure of the photodiode assembly described above comprises a PIN or PN lateral junction diode, a P +/N well (or N +/P-well) vertical junction, a zener diode, or a combination thereof. The guard structure is optionally a continuous guard ring or a discontinuous guard ring, for example in case the guard ring comprises one or two holes arranged to correspond to the entrance of the waveguide into the photodiode.

In some embodiments, the guard structure is comprised of Si, Ge, SiGe, a III-V material, or any combination thereof.

Drawings

For a better understanding of the application as described herein, as well as other aspects and further features of the present application, reference is made to the following description, taken in conjunction with the accompanying drawings, in which:

FIG. 1 schematically depicts an integrated silicon photonic switching cell including two monitoring photodiodes;

FIG. 2 depicts one embodiment of a vertical PIN photodiode including an ESD protection structure that is a lateral PIN diode guard ring having one or two holes, wherein FIG. 2A is a cross-sectional view of a vertical PIN PD; FIG. 2B is an electrical connection diagram of one embodiment of a PIN PD and a guard ring; FIG. 2C is an electrical connection diagram of another embodiment of a PIN PD with a guard ring that includes a combination of guard diodes; FIG. 2D is a top view of a unidirectional PIN PD; FIG. 2E is a top view of a bi-directional PIN PD;

FIG. 3 depicts the layers incorporated in a vertical PIN photodiode as shown in FIG. 2;

FIG. 4 depicts one embodiment of a vertical PIN photodiode including an ESD protection structure as a lateral PN junction diode guard ring with one or two holes, where FIG. 4A is a cross-sectional view of a vertical PIN PD having a lateral guard ring diode; FIG. 4B is an electrical connection diagram of a PD connected in parallel with a protection diode; FIG. 4C is a top view of a unidirectional PIN PD; FIG. 4D is a top view of a bi-directional PIN PD;

FIG. 5 depicts one embodiment of a vertical PIN photodiode including an ESD protection structure that is an SOI gated diode, where FIG. 5A is a cross-sectional view of a vertical PIN PD; FIG. 5B is an electrical connection diagram of the vertical PIN PD and the SOI gated diode guard structure; fig. 5C is a top view of unidirectional PIN PD; fig. 5D is a top view of the bidirectional PIN PD;

FIG. 6 depicts one embodiment of a vertical PIN photodiode including an ESD protection structure that is a double well field effect diode, where FIG. 6A is a cross-sectional view of a vertical PIN PD; FIG. 6B is an electrical connection diagram of a vertical PIN PD and a dual-well field effect diode guard structure; fig. 6C is a top view of unidirectional PIN PD; fig. 6D is a top view of the bidirectional PIN PD;

FIG. 7 depicts one embodiment of a vertical PIN photodiode included as

An ESD protection structure for a "under BOX" substrate diode, wherein fig. 7A is a cross-sectional view of a vertical PIN PD; fig. 7B is an electrical connection diagram of the vertical PIN PD; fig. 7C is a top view of unidirectional PIN PD; fig. 7D is a top view of the bidirectional PIN PD.

Detailed Description

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

As used in the specification and in the claims, the singular form of "a", "an", and "the" include plural referents unless the context clearly dictates otherwise.

The term "comprising" as used herein will be understood to mean that the following list is non-exhaustive and may or may not include any other additional suitable items, such as one or more other features, components and/or ingredients, as appropriate.

The term "ESD" is used herein to refer to electrostatic discharge.

The term "PD" is used herein to refer to a photodiode or photodetector, and these two terms may be used interchangeably.

The term "GS" is used herein to refer to a guard structure, such as a guard ring or a combination of guard elements, for providing protection against ESD.

The term "SiPh" is used herein to refer to silicon photons.

The term "SOI" is used herein to refer to silicon-on-insulator technology.

The term "BOX" is used herein to refer to the buried oxide layer.

Although the figures and descriptions provided below depict and describe photodiode structures having p-type and n-type regions, particularly in terms of relative positions, each structure will function in an equivalent manner when all of the p-type and n-type regions are swapped (note that in each structure, all of the regions must be swapped, not just a portion thereof). By way of example, referring to FIG. 6a as shown, the top layer is p +/i/n +/i/p + and the bottom layer is p + +/p +/p + +. A suitable alternative is the following structure: the top layer is n +/i/p +/i/n +, and the bottom layer is n + +/n +/n + +.

A Photodiode (PD) is one of the most ESD sensitive elements in the SiPh die. PD may experience premature breakdown due to an electric field locally concentrated at the junction edge. To withstand high ESD voltages, the PD may be designed to include a structure with a high electric field evenly distributed across the junction. PD may also experience breakdown due to high electric fields across the junction. One way to solve this problem is to: a protection diode is designed in parallel with the PD, which allows high current discharge or voltage clamping (i.e., ESD shunting).

The successful application of Guard Structures (GS), such as guard rings, in silicon photonics PD is limited by the interaction of light with the GS region. SiPh devices operate in a wavelength range where Si is generally transparent and Ge strongly absorbs. Ge is suitable as a photodetecting material since it is a strong absorber of light in the wavelength range in which SiPhs operates.

However, because Ge is a strong absorber of light, having a Ge region in the guard structure at the location where light enters the device may be disadvantageous because: the light absorbed in the shielding structure does not generate a current for light detection, and thus the responsivity of the PD may be reduced. More generally, it is desirable to configure the protective structure in the following manner: these structures do not interfere with light detection and propagation of light to the photodetector, while still being operable to mitigate breakdown caused by ESD.

When the PD is surrounded on all sides by guard ring structures, light can be transmitted to the PD from the top or bottom without encountering a guard ring. However, when light is routed to the PD through a waveguide that is parallel and coplanar with the guard ring, the guard ring forms a barrier between the waveguide and the PD. Furthermore, even when the guard ring is in a separate but parallel plane with respect to the waveguide, the vicinity of the guard ring may interfere with light propagation through the waveguide below or above the guard ring. The present invention aims to provide a protective structure that avoids or mitigates these difficulties. This would allow the PD, guard structures and waveguides to be fabricated in a limited planar area, which is desirable for fabrication on a wafer or other structure using photolithographic (or build-up) techniques.

In a first approach, the guard structure and the waveguide are arranged in parallel but spaced apart planes. In one embodiment, the spacing is large enough such that the light absorption of the protective structure is limited. In an alternative, the guard structure comprises at least one aperture arranged to correspond to a path of light propagation from the waveguide to the PD, thereby reducing light absorption by the guard structure. In this approach, the GS may be, for example, above the waveguide and may be coplanar with the PD. Alternatively, the GS may be below the waveguide, such as below the buried oxide layer.

In a second approach, the guard structure and the waveguide are in the same plane. In most embodiments of the method, the guard structure comprises at least one aperture arranged to allow propagation of light from the waveguide into the PD. In an alternative embodiment, the guard structure does not include an aperture. In such embodiments, all or a portion of the guard structure is made of a semiconductor material that does not absorb light or only minimally absorbs light at wavelengths of light that can be detected by the PD. In case only a part of the guard structure is made of a semiconductor material that does not absorb light or only minimally absorbs light at the wavelength required by the PD, this part is arranged to correspond to the entrance of the waveguide into the photodiode.

In some embodiments, each of the one or more holes included in the guard structure comprises an optically non-absorbing semiconductor material electrically connected to the guard structure on either side of the hole.

In embodiments where the guard structure comprises an aperture, a bridge structure is optionally included, the bridge structure electrically connecting the guard structure on either side of the aperture. When the guard structure is disposed on a layer of the integrated circuit, the bridge structure may include: a first via connecting the guard structure on a first side of the hole to a second layer of the integrated circuit; a second via connecting the guard structure on a second side of the aperture to the second layer; and a conductive trace formed on the second layer to electrically connect the first via and the second via.

In the SiPh system, useful optical materials for making GS are dielectrics (such as silicon dioxide and silicon nitride) and group IV materials (specifically, Si, Ge, and various compositions of SiGe, including quantum wells composed of Si, Ge, and SiGe). Similar to the III-V materials (i.e., InP/InGaAs/InGaAsP/InGaAlAs/GaAs/GaAlAs families of materials), the bandgap can be altered by altering the quantum well geometry and/or SiGe composition. However, SiGe and quantum well fabrication is more complex than Si or Ge itself, especially for large area and thick layers required for integrated photonics. III-V materials can be lattice matched and can grow complex multicomponent structures with few defects. However, Si, Ge and SiGe materials cannot be lattice matched and therefore growing complex multicomponent structures with few defects is challenging. The minimum number of group IV materials to construct a useful SiPh circuit including PD is two: si for the waveguide core and Ge for PD.

The present application provides an ESD protection structure (GS) applicable to integrated SiPh PD protection. The GS of the present application extends around all or substantially all of the circumference of the silicon PD to be protected and is configured to allow light propagation into the intrinsic region of the PD where it is converted to photocurrent. GS generally forms a ring shape. The PD may be at least partially in the same plane as the GS, in which case the ring surrounds at least a portion of the PD. Alternatively, the PD may be located above or below the plane of the GS while still close to the GS. In this case, the opening of the ring is aligned with the PD. Light propagates to the PD via the waveguide located in a first planar region that is parallel to (and may be coplanar with) a second planar region that includes the GS. The GS may include a hole aligned with the waveguide such that the waveguide passes below or above the hole. The aperture serves to mitigate interference of the GS with light as it propagates through the waveguide below or above the aperture.

As will be readily understood by those skilled in the art, when it comes to interference of the GS with light transmission, it is important to ensure that the GS is transparent or partially transparent to light at wavelengths that can be detected by the PD. It is important to ensure that the GS does not absorb or minimally absorbs light at the wavelength of interest (or signal wavelength) entering the PD. As mentioned above, this is achieved by appropriate selection of the materials used to make the GS or by including one or more holes in the GS. The absorption of light at non-signal wavelengths by GS is not necessarily a consideration.

As used herein with respect to GS, the term "opening" refers to the interior of the ring shape bounded by the curved inner sidewall of the ring. Thus, for example, the opening corresponds to the interior of the letter "O". The term "hole" refers to a break in the GS ring sidewall that extends from the outer sidewall to the inner sidewall. Thus, for example, the hole corresponds to a structure that transforms an "O" ring into a "C" shaped structure.

In one embodiment, GS is a guard ring that extends around the entire circumference of the silicon PD to be protected. In one example of this embodiment, the guard ring is disposed in a plane sufficiently spaced from the waveguide to minimize the interference of the GS in light propagation. In an alternative example, all or a portion of GS is formed of appropriately doped silicon (Si), germanium (Ge), or silicon/germanium (SiGe) such that the guard ring does not absorb the incoming light or absorbs a minimal amount of light, thereby allowing light propagation into the intrinsic region of the PD.

A combination of an electrical protection diode (or guard structure) and a photodiode in which the protection diode particularly allows propagation of light from a silicon waveguide may be particularly suitable for use where the photodiode is Si or Si/Ge.

As will be readily appreciated by those skilled in the art, materials other than silicon or germanium may also be used to construct the PD and/or GS.

For example, group III-V materials may be used alone or in combination with silicon and/or germanium.

In one embodiment, the GS is a guard ring coplanar with the waveguide, and the GS includes an aperture that allows light propagation into the intrinsic region of the PD. The silicon waveguide intersects the ring at the hole, thereby avoiding light absorption by the ring. In one example, the hole includes an undoped silicon region, such as a ring.

Depending on the PD layout, the GS may have one or two holes or may be configured by one or two separate doped semiconductor regions. A guard ring with one hole (C-like shape) can be designed for unidirectional PD. A ring with two holes or a GS with two separate elements can be designed for bidirectional PD. In embodiments where the GS comprises at least two apertures or consists of separate semiconductor regions, the GS is considered to be "discontinuous".

In some embodiments, the GS is discontinuous and may include two, three, or more electrically protected diodes arranged around the photodiode, e.g., to form a ring shape of individual diodes. The electric protection diode may be bent in an arcuate shape. The waveguide may travel through, over, or under the gap between the diodes. In some embodiments, the GS diode may be electrically connected using a conductive bridge located above or below the gap or using an optically transparent semiconductor bridge located within the gap. Note that in these cases, the GS is electrically continuous, but is still referred to herein as "discontinuous" due to the discontinuous nature of the diodes within the GS.

In embodiments where the GS is discontinuous, electrical connections may be introduced between the GS portions to create bridges, for example, through contacts, vias, and metal (e.g., aluminum or copper) or doped polysilicon portions that interconnect the GS portions. In this embodiment, the integrated SiPh waveguide intersects the GS at the hole. The metal bridge may be located above or below the optical waveguide region at a distance at which light in the waveguide does not significantly interact with the metal. This is desirable because metals strongly absorb light. The doped polysilicon may be adjacent to the optical waveguide region so that light in the waveguide does interact with the doped polysilicon. Doped polysilicon, however, is a weak absorber of light and, therefore, is a substantially transparent region. In general, the smaller the bridge material interacts with the light from the waveguide, the closer the bridge can be placed to the waveguide (assuming a given tolerance for the amount of light that can be absorbed by the GS). In the extreme case, the bridge is very (or almost completely) transparent to light at the relevant wavelength and that can pass through the waveguide.

As noted above, in all embodiments, it is not necessary to include a bridge (e.g., a metal or doped polysilicon bridge) across the light entry region. In contrast, the guard structure may include holes without bridges. When the protective structure comprises a single aperture, it is continuous even without bridging. When the guard structure comprises a plurality of holes, each individual part of the guard structure may operate as an individual protection diode, and the GS is discontinuous. However, regardless of the number of holes present, the electrical connection provided by the bridge generally provides improved charge distribution throughout the GS, which may increase the effectiveness of the GS.

In some embodiments, electrical connections between portions of the guard structure may be provided using conductive bridge portions (typically metal traces) located above or below the semiconductor guard structure (e.g., on the plane of a photonic integrated circuit including the conductive traces) and connected to the guard structure using vias.

The GS currently provided can protect PDs of different configurations, including PIN vertical junctions PD and PIN lateral junctions PD.

The GS of the present application may include one or more diodes. The specific diode structure may vary depending on the structure or application of the PD to be protected. As described in more detail below, the GS may be configured as a PIN or PN lateral junction diode, a P +/N well (or N +/P-well) vertical junction, a zener diode, an SOI gated diode, a double well field effect diode, a diode under the BOX, or other combination. These diode types are known to those skilled in the art, but have not previously been applied to the GS described herein.

The protection diode will be electrically connected to the PD to protect the PD from discharge currents, thereby increasing the robustness of the device to ESD events. The GS provides protection against ESD events by: (i) shunting the ESD from the PD; and/or (ii) shaping the electromagnetic field from the ESD to avoid strong gradients at the PD or enhance field uniformity during the ESD event, thereby suppressing breakdown due to the ESD event. GS defines the PD to substantially avoid sharp corners and related features associated with undesirable local enhancement of the electric field caused by ESD events.

GS may be formed in the silicon layer and/or in the germanium layer. The doping can be in Si or Ge (or both).

The silicon waveguide has a silicon core comprising full thickness silicon and a fully etched region without silicon. In some embodiments, there may be partially etched regions comprising thinner silicon layers. In this manner, a silicon ribbon or silicon rib waveguide may be provided. Germanium may be deposited on top of a silicon core or on silicon dioxide in partially etched regions or fully etched regions of silicon.

The on-chip ESD protection GS described herein may simplify the manufacturing and processing requirements of the current alternative to SiPh PDs. The present GS allows protection to be applied to enhance the robustness of the SiPh PD to ESD events. The design and fabrication of the integrated SiPh PD with GS as described herein is compatible with CMOS technology suitable for silicon photonics. Large node size processes (e.g., 0.13um) can be successfully used.

Further details of specific embodiments of the present GS and systems including the present GS are now provided with reference to the drawings. It should be noted that the drawings are merely schematic representations, not intended to portray specific parameters of the invention. The drawings are intended to depict only typical and exemplary aspects of the invention, and not as limiting.

The figures and the following description relate to embodiments in which the PD to be protected is a vertical PIN PD. However, it is readily understood that the various GS described and illustrated below and in the drawings are equally applicable to the protection of other PDs (such as SiPh PDs, including PIN lateral junction PDs).

Fig. 1 shows an example of a silicon photonic switching cell 100 comprising an optical switching cell 110 and two monitoring photodiodes 120. Input light enters the optical switch 110 and is output at the output waveguide. A portion of the output light is captured at the two monitor photodiodes 120. As described herein, incorporating GS into the monitor photodiode 120 reduces the sensitivity of the system to ESD events. As described above, the present GS may be incorporated into PIN PD such as, but not limited to, Si PIN PD, Se/Ge PIN PD, InGaAs PIN PD, Ge-on-SOI lateral PIN PD, Ge-on-SOI with silicon waveguides transiently butt-coupled to intrinsic Ge. Such a PIN PD may be part of an integrated SiPh switch unit (as shown in fig. 1) or may be incorporated in other systems requiring optical monitoring.

Fig. 2 depicts an embodiment of a GS with a vertical PIN PD. In this example, GS is a PN lateral junction diode guard ring.

Fig. 2A is a cross-sectional view depicting a Ge-PD 200 with a vertical PIN configuration integrated in a SiPh unit, such as a SOI die, the Ge-PD 200 including a silicon layer 210, the silicon layer 210 including a silicon waveguide 212 fabricated on a Buried Oxide (BOX) layer 220. Vertical PIN PD 200 includes a p + region 230, an n + region 235, and an intrinsic Ge region 240 located between the p + and n + regions. A heavily doped silicon p + + region 250 surrounding the vertical PIN PD 200 is used to conduct charge within the SiPh cell. Vertical PIN PD 200 is protected by GS, guard ring 260. As shown in fig. 2A, guard ring 260 is a p +/i/n + lateral junction diode disposed in the Ge layer, where guard ring 260 shares n + region 235 with PIN PD 200 and additionally includes p + region 237. That is, n + region 235 forms part of both PIN PD 200 and GS. As will be readily appreciated by those skilled in the art, an alternative to the structure shown in fig. 6A is a similar configuration as follows: there is an additional n + region that forms only a portion of the guard ring and a separate n + region that forms only a portion of the vertical PIN PD. For example, the two separate n + regions may be placed side by side.

Fig. 2B schematically shows a circuit comprising a vertical PIN PD 200 and a guard ring 260 (as a protection diode) connected in cathode-to-cathode parallel. The three arrows represent incident photons propagating from the silicon waveguide. To ensure optimal operation, the reverse voltage breakdown threshold of guard ring 260 may be configured to: less than the breakdown voltage of PIN PD 400 but higher than the bias voltage of PIN PD 200.

Other connections are also possible, for example cathode to anode, for the case where, for example, the PIN PD 200 present in a solar cell is used in the "photovoltaic" field. By way of example, fig. 2C shows an alternative connection layout of vertical PIN PD 200 with guard ring 261 including a combination of protection diodes. More specifically, this example uses a guard ring 261 for protecting vertical PIN PD 200 at both positive and negative ESD voltages, the guard ring 261 including a combination of protection diodes having the same design as used in guard ring 260 shown in fig. 2A. The circuit comprises three parallel branches: a first branch including a photodiode 200; a second branch including a first ESD protection diode formed by a guard ring, the first ESD protection diode connected with the photodiode cathode to cathode; and a third branch comprising two further series-connected ESD protection diodes formed by a guard ring, said two further series-connected ESD protection diodes being connected to the photodiode anode to cathode and cathode to anode respectively. This configuration, in which there are two protection diodes connected in series in one branch of the circuit, provides a threshold voltage of that branch that is higher than the reverse-biased operating voltage of the photodiode. This protects the photodiode from high voltages, the polarity of which coincides with the polarity of the reverse bias voltage of the photodiode. The other branch with one protection diode protects the PD from voltages with a polarity coinciding with the forward bias voltage of the PD. The circuit configuration provides ESD protection for both positive and negative voltages.

Fig. 2D is a top view of a vertical PIN PD 200 having a guard ring 260 and configured for unidirectional optical input by including a single aperture 262, where the single aperture 262 is aligned with the optical path to the PD. In this embodiment, the aperture 262 includes a metal bridge 264 electrically connected to the guard ring on both sides of the aperture 262, however, as will be readily understood by those skilled in the art, this bridge is optional. The metal bridge includes a pair of vias (or pillars) extending away from the guard ring and the optical path. A first end of each via is connected to the guard ring and a second end of the via, opposite the first end, is coupled by a conductive material, such as a metal trace. Thus, the conductive material connected to both sides of the hole is located away from the optical path.

The presence of the configuration of the aperture 262 reduces the potential interaction of light with the doped ring of the guard ring 260. Thus, light can pass through guard ring 260 or along guard ring 260 to PD 200 while avoiding absorption in the Ge-doped regions forming the guard ring. In this example, the aperture optionally comprises a material that is optically transparent or substantially optically transparent to light having a wavelength of light that is detectable by the PD. The aperture is configured to allow light having a wavelength of interest for the PD to pass from the waveguide to the PD. It should be noted that since the guard ring 260 is not in the same plane as the waveguide 212, the guard ring 260 need not have holes, although it may be beneficial for the guard ring 260 to have holes.

The layers of vertical PIN PD 200 are shown in fig. 3 and are similar to those of a standard vertical PIN PD, including a bottom silicon layer 210 with a waveguide 212, stacked on the bottom silicon layer 210 with a doped p + Si region 230, followed by a heavily doped p + + Si region 250, an intrinsic Ge layer 240, a doped n + Ge layer 235 with a doped p + Ge layer 237, a metal via 470 for contact, and a metal region 480 for routing. For simplicity, the metal bridge 264 is not shown in FIG. 3.

Fig. 2E is a top view of vertical PIN PD 200 with guard ring 260 and configured for bi-directional optical input by including two holes 262a and 262 b. In this embodiment, each aperture 262a and 262b is optionally spanned by a metal bridge 264. This configuration mitigates the interaction of light with the doped rings of the guard ring 260 and light can pass bi-directionally through the guard ring 260 or along the guard ring 260 to the PD 200 without being absorbed in the doped Ge. Further, in this example, one or both apertures optionally comprise a material that is optically transparent or substantially optically transparent at the wavelength of light that can be detected by the PD. The aperture is arranged to extend along an optical path through the waveguide so that light having a wavelength of interest to the PD passes from the waveguide to the PD. It should be noted that since the guard ring 260 is not in the same plane as the waveguide 212, the guard ring 260 need not include holes, although it may be beneficial for the guard ring 260 to include holes.

Fig. 4 depicts another embodiment of GS. In this example, GS is a PN lateral junction diode guard ring.

Fig. 4A is a cross-sectional view depicting a vertical PIN PD 300 integrated in a SiPh unit, such as an SOI die, the vertical PIN PD 300 including a silicon layer 310 with a waveguide 312 fabricated on a Buried Oxide (BOX) layer 320. Vertical PIN PD 300 includes a p + region 330, an n + region 335, and an intrinsic Ge region 340 located between the p + and n + regions. A heavily doped silicon p + + region 350 surrounding vertical PIN PD 300 is used to conduct charge in the SiPh cell. Vertical PIN PD 300 is protected by GS as guard ring 360. As shown in fig. 4A, the guard ring 360 is a PN lateral junction diode, formed in the silicon layer and formed in a plane parallel to the plane of the waveguide. Guard ring 360 includes p + +/p + doped silicon region 350/366 and n + +/n + doped silicon region 369/368.

Fig. 4B shows an electrical schematic diagram representing vertical PIN PD 300 connected in parallel cathode-to-cathode with guard ring 360.

The three arrows represent incident photons propagating from the silicon waveguide.

Fig. 4C is a top view 300 of vertical PIN PD 300 having guard ring 360 and configured for unidirectional optical input by including a single aperture 362. In this embodiment, the aperture 362 includes a metal connection 364 (using contacts and vias), the metal connection 364 being optional. The metal connection or bridge includes a pair of vias (or posts) that extend away from the guard ring and the optical path. A first end of each via is connected to the guard ring and a second end of the via, opposite the first end, is coupled by a conductive material, such as a metal trace. Thus, the conductive material connected to either side of the aperture is located away from the optical path.

The configuration including the holes ensures that light does not interact with the doped rings of guard ring 360 and that light can pass through the rings to PD 300 without being absorbed in the doped Si. As shown in fig. 4C, in this example, the guard ring 360 includes an aperture 362 aligned to coincide with the optical path through the waveguide 312. However, since the guard ring 360 is not in the same plane as the waveguide 312, it is not necessary for the guard ring 360 to include an aperture, although it may be beneficial for the guard ring 360 to include an aperture.

Fig. 4D is a top view of vertical PIN PD 300 having guard ring 360 and configured for bi-directional optical input by including two holes 362a and 362 b. In this embodiment, holes 362a and 362b each include metal connections 364 (using contacts and vias). This configuration ensures that light does not interact with the doped rings of guard ring 360 and that light can pass bi-directionally to PD 300 without being absorbed in the doped Si of guard ring 360. As shown in fig. 4D, in this example, the guard ring 360 includes two holes disposed along the optical path through the waveguide. However, since the guard ring 360 is not in the same plane as the waveguide, it is not necessary for the guard ring 360 to include an aperture, although it may be beneficial for the guard ring 360 to include an aperture.

The layers of vertical PIN PD 300 are similar to those shown in fig. 3, such that vertical PIN PD 300 includes silicon layer 310, doped p + Si region 330, heavily doped p + + Si region 350, intrinsic Ge layer 340, doped n + Ge layer 335, metal vias for contacts 370, and metal regions for routing 380.

Fig. 5 to 7 each depict an alternative embodiment of the presently described GS. As shown in fig. 5 to 7, the overall structure including the PD and GS uses bridges and/or external circuits in combination with connections between the different parts.

Fig. 5 depicts another embodiment of GS. In this example, GS is an SOI gated diode.

Fig. 5A is a cross-sectional view depicting a vertical PIN PD 400 integrated in a SiPh unit, the vertical PIN PD 400 including a silicon layer 410 with a silicon waveguide 412 fabricated on a BOX layer 420. Vertical PIN PD 400 includes a p + region 430, an n + region 435, and an intrinsic Ge region 440 located between the p + region and the n + region. A heavily doped silicon p + + region 450 surrounding the vertical PIN PD 400 is used to conduct charge within the SiPh cell and forms part of the GS. The vertical PIN PD 400 is protected by the GS as a guard ring 460. Guard ring 460 is an SOI gated diode disposed in silicon layer 410 and includes a gate 470, an N-well or P-well 472, an N + region 474, and a heavily doped P + + region 450. In this structure, there is no good contact. The gate electrode 470 is located over the N-well or P-well 472 and serves as a blocking structure to separate the N + region 474 from the heavily doped P + + region 450 and prevent electrical shorting caused by silicidation over the P-N junction region.

Fig. 5 schematically shows a circuit comprising a vertical PIN PD 400 and a guard ring 460 (as a protection diode) connected in cathode-to-cathode parallel. The three arrows represent incident photons propagating from the silicon waveguide.

Fig. 5C is a top view of a vertical PIN PD 400 having a guard ring 460 and configured for unidirectional optical input by including a single aperture 462, the single aperture 462 being aligned with an optical path through a silicon waveguide. In this embodiment, aperture 462 includes a metal bridge 464 electrically connected to guard rings on both sides of aperture 462, however, the bridge is optional. As described above, the metal bridge includes a pair of vias (or pillars) that extend away from the guard ring and the optical path. A first end of each via is connected to the guard ring and a second end of the via, opposite the first end, is coupled by a conductive material, such as a metal trace. Thus, the conductive material connected to both sides of the hole is located away from the optical path.

The presence of the configuration of apertures 462 reduces the likelihood of light interacting with the doped rings of the guard ring. Thus, light is able to pass through guard ring 460 to PD 400 with less chance of absorption in the doped region of Si forming the guard ring. In this example, the aperture optionally comprises a material that is optically transparent or substantially optically transparent to light that can be detected by the PD 400.

Fig. 5D is a top view of a vertical PIN PD 400 having a guard ring 460 and configured for bi-directional optical input by including two holes 462a and 462 b. In this embodiment, each of the apertures 462a and 462b may be spanned by a metal bridge 464. This configuration reduces or eliminates the interaction of light with the doped ring of the guard ring 460 and the light is able to pass bi-directionally through the ring to the PD 400 without being absorbed in the doped Ge. Further, in this example, one or both apertures optionally comprise a material that is optically transparent or substantially optically transparent to light having a wavelength of light that is detectable by the PD.

The layers of the vertical PIN PD 400 are similar to those shown in fig. 3, such that the vertical PIN PD 400 includes a silicon layer 410, a doped p + Si region 430, a heavily doped p + + Si region 450, an intrinsic Ge layer 440, a doped n + Ge layer 435, a metal via 470 for contact, and a metal region 480 for wiring.

Fig. 6 shows another embodiment of the presently described GS. In this example, GS is a double well field effect diode guard ring. Fig. 6A is a cross-sectional view depicting a vertical PIN PD 500 integrated in a SiPh cell, the vertical PIN PD 500 including a silicon layer 510 with a silicon waveguide 512 fabricated on a BOX layer 520. Vertical PIN PD 500 includes a p + region 530, an n + region 535, and an intrinsic Ge region 540 located between the p + and n + regions. A heavily doped silicon p + + region 550 surrounding the vertical PIN PD 500 is used to conduct charge within the SiPh cell and forms part of the guard ring 560. The vertical PIN PD 500 is protected by GS as guard ring 560 fabricated in silicon layer 510. As shown in fig. 6A, guard ring 560 is a double well field effect diode guard ring in Si. Guard ring 560 includes an N-well region 590, a p-well region 592, an N + region 594, a p + + region 550, and an N-poly oxide gate 596.

Guard ring 560 includes two wells (590 and 592) having the same length and disposed in the middle region of the diode structure. An N-poly gate 596 is placed over the two wells (590 and 592) allowing inversion to be formed in the wells as desired by applying appropriate gate biases. Electrical contact between the gate over the well region (gate bias contact) and the n-well or p-well of the diode is through the polysilicon gate. This means that there is no direct connection of the wells.

Fig. 6B schematically shows a circuit including a vertical PIN PD 500 and a guard ring 560 (as a protection diode) connected in cathode-to-cathode parallel. The three arrows represent incident photons propagating from the silicon waveguide.

Fig. 6C is a top view of vertical PIN PD 500 having a guard ring 560 and configured for unidirectional optical input by including a single hole 562, the single hole 562 being aligned with the optical path to the PD. In this embodiment, via 562 includes a metal bridge 564 electrically connected to guard rings on either side of via 562, however, this bridge is optional. The metal bridge includes a pair of vias (or pillars) extending away from the guard ring and the optical path. A first end of each via is connected to the guard ring and a second end of the via, opposite the first end, is coupled by a conductive material, such as a metal trace. The conductive material connected to either side of the aperture is then located away from the optical path.

The presence of the hole 562 configuration mitigates the interaction of light with the doped rings of the guard ring 560. Thus, light can pass through guard ring 560 to PD 500 without substantial absorption in the doped regions of Si forming the guard ring. In this example, the aperture optionally comprises a material that is optically transparent or substantially optically transparent to light having the wavelength of operation of the PD.

Fig. 6D is a top view of vertical PIN PD 500 having a guard ring 560 and configured for bi-directional optical input by including two apertures 562a and 562 b. In this embodiment, each of the holes 562a and 562b may be spanned by a metal bridge 564. This configuration enables light absorption by the doped rings of guard ring 560 to be reduced or eliminated so that light can pass bi-directionally through the rings to PD 500 without being absorbed in the doped regions of Si forming the guard ring.

The layers of vertical PIN PD 500 are similar to those shown in fig. 3, such that vertical PIN PD 500 includes a silicon layer 510, a doped p + Si region 530, a heavily doped p + + Si region 550, an intrinsic Ge layer 540, a doped n + Ge layer 535, a metal via 570 for contact, and a metal region 580 for routing. Further, in this example, one or both apertures optionally comprise a material that is optically transparent or substantially optically transparent to light having a wavelength of light that is detectable by the PD.

Fig. 7 shows another embodiment of GS. In this example, GS is the "under BOX" substrate diode guard ring. That is, the semiconductor portion of the GS is disposed in a first planar region, the photodiode is disposed in a second planar region, and the waveguide is disposed in a third planar region located between the first and second planar regions. Fig. 7A is a cross-sectional view depicting a vertical PIN PD 600 integrated in a SiPh unit, the vertical PIN PD 600 including a silicon layer 610 with a silicon waveguide 612 fabricated on a BOX layer 620. Vertical PIN PD 600 includes a p + region 630, an n + region 635, and an intrinsic Ge region 640 located between the p + and n + regions. A heavily doped silicon p + + region 650 surrounding the vertical PIN PD 600 is used to conduct charge within the SiPh cell. Vertical PIN PD 600 is protected by GS as guard ring 660. As shown in fig. 7A, guard ring 660 is a "under BOX" substrate diode. Guard ring 660 includes an n-well region 690, an n + region 692, a p + region 694, and two BOX regions 696 and 698. This structure can help alleviate the heat build-up problem, if desired.

Fig. 7B schematically shows a circuit comprising a vertical PIN PD 600 and a guard ring 660 (as a protection diode) connected in cathode-to-cathode parallel. The three arrows represent incident photons propagating from the silicon waveguide.

Fig. 7C is a top view of a vertical PIN PD 600 having a guard ring 660 and configured for unidirectional optical input by including a single aperture 662 formed in the guard ring at a location below and aligned with the waveguide. In this embodiment, bore 662 includes a metal bridge 664 electrically connected to guard rings on either side of bore 662. The metal bridge is optional. The metal bridge includes a pair of vias (or pillars) extending away from the guard ring and the optical path. A first end of each via is connected to the guard ring and a second end of the via, opposite the first end, is coupled by a conductive material, such as a metal trace. The conductive material connected to either side of the aperture is then located away from the optical path.

The presence of the configuration of apertures 662 reduces the interaction of light with the doped rings of guard ring 660. Thus, light can pass through guard ring 860 to PD 800 with less absorption in the doped Si regions forming the guard ring. In this example, the aperture optionally comprises a material that is optically transparent or substantially optically transparent to light having a wavelength that is detectable by the PD. Further, it should be noted that since the guard ring 660 is not in the same plane as the waveguide 612, the guard ring 660 need not necessarily include an aperture, although it may be beneficial for the guard ring 660 to include an aperture.

Fig. 7D is a top view of vertical PIN PD 600 having guard ring 660 and configured for bi-directional optical input by including two holes 662a and 662 b. In this embodiment, each bore 662a and 662b is optionally spanned by a metal bridge 664. This configuration mitigates the interaction of light with the doped rings of guard ring 660 so that light can pass bi-directionally through the ring to PD 600 without being absorbed in the doped Ge. Further, in this example, one or both apertures optionally comprise a material that is optically transparent or substantially optically transparent to light having a wavelength that is detectable by the PD. Further, it should be noted that since the guard ring 660 is not in the same plane as the waveguide 612, the guard ring 660 need not necessarily include any holes, although it may be beneficial for the guard ring 660 to include holes.

The layers of vertical PIN PD 600 are similar to those shown in fig. 3, such that vertical PIN PD 600 includes a silicon waveguide layer 610, a doped p + Si region 630, a heavily doped p + + Si region 650, an intrinsic Ge layer 640, a doped n + Ge layer 635, a metal via 670 for contact, and a metal region 680 for routing.

All publications, patents, and patent applications mentioned in this specification are indicative of the level of skill of those skilled in the art to which this invention pertains and are herein incorporated by reference to the same extent as if each individual publication, patent, or patent application was specifically and individually indicated to be incorporated by reference.

Having thus described the invention, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.