阅读说明：本技术 没有母板地面要求的搭锁式电磁干扰（emi）屏蔽 (Snap-on electromagnetic interference (EMI) shielding without motherboard ground requirements ) 是由 J·李 J·廖 X·李 C·E·考克斯 于 2020-02-28 设计创作，主要内容包括：一种设备包括印刷电路板(PCB)和用于PCB的屏蔽件。屏蔽件可以减少由PCB的一个或多个组件生成的高频电磁频率(EMF)噪声。PCB包括用于与对应的连接器接合的衬垫。例如,对于双列直插式存储器模块(DIMM)PCB,PCB包括用于插入到DIMM连接器中的衬垫。屏蔽件包括在其周边中与对应的连接器中的夹子对齐的间隙。间隙将对应于PCB的这样的类似特征：与对应的连接器接合以允许屏蔽件附接到PCB。屏蔽件包括从屏蔽件的面向连接器的边缘延伸的锁指,以与对应的连接器接合从而将屏蔽件与对应的连接器对齐。(An apparatus includes a Printed Circuit Board (PCB) and a shield for the PCB. The shield may reduce high frequency electromagnetic frequency (EMF) noise generated by one or more components of the PCB. The PCB includes pads for engaging with a corresponding connector. For example, for a dual in-line memory module (DIMM) PCB, the PCB includes pads for insertion into a DIMM connector. The shield includes a gap in its perimeter that aligns with a clip in a corresponding connector. The gap would correspond to such similar features of the PCB: engage with a corresponding connector to allow the shield to be attached to the PCB. The shield includes a locking finger extending from an edge of the shield facing the connector to engage with the corresponding connector to align the shield with the corresponding connector.)

1. An apparatus for noise shielding, comprising:

a Printed Circuit Board (PCB) including components that generate high frequency electromagnetic frequency (EMF) noise during operation, the PCB including pads for engaging with corresponding connectors; and

a removable shield for covering the assembly, the shield including a gap in a perimeter of the shield to align with a clip in the corresponding connector to secure the shield with the PCB, and a locking finger extending from an edge of the shield to engage with the corresponding connector to align the shield with the corresponding connector.

2. The apparatus of claim 1, wherein the shield is to be secured in contact with the PCB via the clip in the corresponding connector.

3. The apparatus of claim 2, wherein the PCB comprises a plurality of ground pads to contact the removable shield when secured.

4. The apparatus of claim 3, wherein the ground pad comprises a flat pad on the PCB to engage with a perforated surface of the shield.

5. The apparatus of claim 3, wherein the ground pad comprises a protruding pad on the PCB to engage a flat shield surface.

6. The apparatus of claim 3, wherein the ground pad comprises a pad to a ground plane of the PCB, wherein the shield is only indirectly connected to a system ground through the ground pad and the corresponding connector.

7. The apparatus of claim 1, wherein the shield includes a flange for engaging with the clip to secure to the PCB, wherein the gap in the perimeter includes a gap in the flange to align with the clip of the corresponding connector.

8. The apparatus of claim 1, wherein the shield includes sidewalls to completely surround the components on the PCB.

9. The apparatus of claim 1, wherein the component comprises a Dynamic Random Access Memory (DRAM) device.

10. The apparatus of claim 9, wherein the PCB comprises a PCB of a dual in-line memory module (DIMM).

11. A computing device with noise shielding, comprising:

a processor;

a memory Printed Circuit Board (PCB) coupled to the processor, the PCB including a memory device that generates high frequency electromagnetic frequency (EMF) noise during operation, the PCB including pads for engaging with corresponding connectors; and

a removable shield for covering the memory device, the shield including a gap in a perimeter of the shield to align with a clip in the corresponding connector to secure the shield with the PCB, and a locking finger extending from an edge of the shield to engage with the corresponding connector to align the shield with the corresponding connector.

12. The computing device of claim 11, wherein the shield is to be secured in contact with the PCB via the clip in the corresponding connector.

13. The computing device of claim 12, wherein the PCB includes a plurality of ground pads to contact the removable shield when secured.

14. The computing device of claim 13, wherein the ground pad comprises a flat pad on the PCB to engage with a perforated surface of the shield.

15. The computing device of claim 13, wherein the ground pad comprises a protruding pad on the PCB to engage with a flat shield surface.

16. The computing device of claim 13, wherein the ground pad comprises a pad to a ground plane of the PCB, wherein the shield is only indirectly connected to a system ground through the ground pad and the corresponding connector.

17. The computing device of claim 11, wherein the shield includes a flange for engaging with the clip to secure to the PCB, wherein the gap in the perimeter includes a gap in the flange to align with the clip of the corresponding connector.

18. The computing device of claim 11, wherein the shield includes sidewalls to completely surround the memory device.

19. The computing device of claim 11, wherein the PCB comprises a PCB of a dual in-line memory module (DIMM), wherein the memory device comprises a Dynamic Random Access Memory (DRAM) device mounted on the DIMM.

20. The computing device of claim 11, wherein the computing device,

wherein the processor comprises a multi-core processor;

further comprising a display communicatively coupled to the processor;

further comprising a network interface communicatively coupled to the processor; or

A battery for powering the computing device is also included.

Technical Field

The description relates generally to shielding for radiated electromagnetic interference (EMI), and more particularly, to on-demand EMI shielding that does not require motherboard grounding.

Background

Electronic devices with high speed communications generate high frequency noise when operating. High speed communication on signal lines of a Printed Circuit Board (PCB) causes the signal lines to emit Electromagnetic (EM) energy while transmitting signals. The emission of EM energy can result in electromagnetic interference (EMI) based on EM frequency (EMF) noise, which is the emitted signal energy that can interfere with other signaling.

As an example, a dual in-line memory module (DIMM) includes a memory device that performs high speed communications. DIMMs are typically constructed of Double Data Rate (DDR) memory devices, which is a traditional source of significant Radio Frequency Interference (RFI), because DDR memory spectrum falls into multiple radio frequency bands and causes significant radio sensitivity degradation (de-sense) problems. As memory speeds increase and system form factors decrease, conventional DDR physical layer designs will cause serious wireless performance and user experience problems.

Upcoming DDR5 (double data rate version 5) memory technologies will support data rates up to 6400MT/s (megabits per second). Thus, the memory bus, 5G radio, and WiFi communication have similar operating frequencies. Therefore, the potential risk of memory RFI will be significant.

Conventional DIMM shielding relies on an on-board shield that itself covers the memory chip and requires mounting to something on the PCB. The implementation of on-board shields is very limited and is affected by PCB routing. Thus, the shielding effectiveness is inconsistent, resulting in a large number of leaks. Another conventional approach to shielding is a motherboard grounding scheme, in which the shield is electrically connected to the motherboard ground. Such solutions typically involve wiring or connectors or connections that increase the complexity of the design and the complexity of manufacturing.

Drawings

The following description includes discussion of the figures with illustrations given by way of example of implementations. The drawings should be understood by way of example and not by way of limitation. As used herein, reference to one or more examples is understood to describe a particular feature, structure, or characteristic included in at least one implementation of the invention. The appearances of phrases such as "in one example" or "in an alternative example" in this document provide examples of implementations of the invention and do not necessarily all refer to the same implementation. However, these phrases are not necessarily mutually exclusive.

Fig. 1A is a block diagram of an example of a PCB (printed circuit board) without a partial ground for a snap-on shield.

Fig. 1B is a block diagram of an example of a PCB (printed circuit board) engaged with a corresponding connector having a local ground pad for a removable shield.

Fig. 1C is a block diagram of an example of a PCB (printed circuit board) with a removable shield engaged with a local ground pad and attached to a corresponding connector.

Fig. 2 is a schematic representation of an example of interconnecting a removable shield to a corresponding connector.

FIG. 3A is a schematic diagram representing an example of electromagnetic noise from an unshielded device.

FIG. 3B is a schematic diagram representing an example of electromagnetic noise from a shielded device.

Fig. 4A-4D are schematic representations of examples of grounding a shield to a local Printed Circuit Board (PCB).

Fig. 5 is a block diagram of an example of a PCB assembly surrounded by a grounded shield.

Fig. 6 is a flow chart of an example of a process for applying a grounded-on-demand shield.

FIG. 7 is a block diagram of an example of a memory subsystem in which grounded shielding may be implemented.

Fig. 8 is a block diagram of an example of a computing system in which a grounded shield may be implemented.

Fig. 9 is a block diagram of an example of a mobile device in which a grounded shield may be implemented.

The following is a description of certain details and implementations, including non-limiting descriptions of the drawings, which may depict some or all examples, as well as other potential implementations.

Detailed Description

As described herein, an apparatus includes a Printed Circuit Board (PCB) and a shield for the PCB. The shield may reduce high frequency electromagnetic frequency (EMF) noise generated by one or more components of the PCB. EMF noise can cause interference with the operation of other system components, especially when the frequency range of the emitted noise is within the same range as the operating frequency of the other components. The interference may be referred to as electromagnetic interference (EMI). The shield is grounded to the PCB and reduces EMI to the system components by reducing the amount of noise emitted.

The PCB includes pads for engaging with a corresponding connector. The gap would correspond to such similar features of the PCB: engage with a corresponding connector to allow the shield to be attached to the PCB. The shield includes a lock finger (latch finger) to extend from the shield past the PCB to engage with a corresponding connector to align the shield with the corresponding connector. For example, for a dual in-line memory module (DIMM) PCB, the PCB includes pads to be inserted into the DIMM connector. In such implementations, the shield for the DIMM may include a gap in its perimeter that aligns with a clip in the corresponding DIMM connector. The locking fingers may extend into existing slots in the DIMM connector and provide good noise reduction for the DIMM PCB.

In one example, the shield is removable. The shield may be referred to as a "snap-on" shield because it may be connected to ground on the PCB without requiring a permanent or semi-permanent mounting strategy, such as solder or adhesive/epoxy. Removable or snap-on shields may provide on-demand shielding. For example, for a given PCB, when shielding is required, shielding may be included and secured in place using features of the shielding itself or using features of the corresponding connector, or a combination of both. For the same given PCB, when shielding is not required, the PCB may include a ground contact, but no shield.

In addition to EMI shielding, snap-on shields may provide a heat dissipation solution for the PCB. The metal that provides the shielding also conducts heat away from the active components on the board and helps dissipate the heat. In one example, the snap-on shield connects to a ground contact on the PCB, which may be referred to as a local ground, and does not need to connect to the motherboard ground. The connection to the motherboard ground may provide a system ground to ensure a good noise floor for shielding. With the correct connection to the PCB, the connection to the local ground of the PCB can still provide efficient shielding.

The shields described herein are effective for Double Data Rate (DDR) memories even where the communication frequency generates Radio Frequency Interference (RFI) that falls within the spectrum of multiple radio frequency bands used for wireless communication. Applying shielding described as DIMM shielding reduces radio interference noise radiation from the memory device. Thus, allowing the system to maintain reliable wireless performance and a good user experience even with small form factors and high communication frequencies.

As described herein, removable shields are not required to connect to the motherboard ground. The lack of a connection to the motherboard ground may allow a system engineer to mount the shield on the PCB without board modification or re-rotation. In one example, the removable shield may be selectively post-mounted on the PCB, where RFI risk exists. In one example, shielding may be performed as a heat dissipation solution for memory devices on DIMMs. The shield may also be a heat dissipation solution for other components on the PCB rather than for the memory device.

Fig. 1A is a block diagram of an example of a PCB (printed circuit board) without a partial ground for a snap-on shield. System 100 includes connector 110, PCB120, and shield 140. PCB120 represents a circuit board on which active components (not specifically shown) are mounted. PCB represents a circuit to be connected to a motherboard or main circuit board via connector 110. Connector 110 corresponds to PCB120 in that the connector interconnects the PCB to a larger system as a system component.

The components mounted on the PCB120 generate EMI noise during operation. Without shielding, EMI may interfere with other components in the system 100, such as communication circuitry, not shown in fig. 1. The shield 140 reduces the effects of EMI noise generated by the PCB 120.

The connector 110 includes pins 112 for coupling to a system level board for connection to other system components. For example, if PCB120 is a memory module, pins 112 may be connected to a system board in which a processor is mounted. If PCB120 includes a processor, pins 112 may be connected to a connection board to couple to a peripheral device. Pads 122 on PCB120 correspond to pins 112 of connector 110. The pads 122 are connected to components on the PCB via traces on the PCB 120. Pins 112 connect those same traces to other system components.

The connector 110 includes an arm 114 that extends distally from the pin 112 and operates to secure the PCB120 to ensure adequate electrical contact between the pads 122 and the pin 112. Typically, as shown in system 100, there is an arm on either side of the connector. At the end of the arm 114, the connector 110 includes a tab (tab) 116. The tab 116 represents one or more features that secure the PCB 120. The tab 116 may be or include a tab, clip, pin, or other mechanism for providing mechanical engagement with the PCB 120. Typically, the arm 114 aligns the PCB120 with the connector 110, and the tab 116 secures the PCB120 to the arm (e.g., by applying a spring force to push the PCB 120). In one example, the arm 114 includes an alignment tab (not specifically identified) that aligns with the notch 124 of the PCB120, while one or more other tabs secure the PCB and shield to the connector 110. The tabs 116 may be referred to as retention tabs for an existing connector arm used to secure the PCB 120.

The tabs 116 of the connector 110 may be aligned with the notches 124 of the PCB 120. Notch 124 represents a mechanism for aligning and allowing the tabs to align with the mechanical features of connector 110. The shield 140 covers the PCB120, or more particularly, noise generating components of the PCB 120. Typically, the shield 140 covers only one side of the PCB 120. The shield 140 includes features for engaging the tabs 116 and arms 114 of the connector 110 to enable the shield to be removably secured to the PCB120 while connected to the connector 110.

In one example, the shield 140 includes a locking finger represented by finger 142. The fingers 142 extend into the slots 118 of the connector 110. The socket 118 represents a gap or space between the last of the pins 112 and the arm 114. Thus, the connector 110 includes a space into which the fingers 142 may be inserted to provide mechanical stability for the interconnection of the shield 140 with the connector 110. In one example, the shield 140 includes a locking finger 142 and a flange 144. In one example, the shield 140 includes a clip (not explicitly shown). The clip may be part of the shield 140 to clip onto the PCB120 or onto the connector 110, or to clip onto both the PCB 110 and the connector 110.

In one example, the shield 140 includes a flange 144. As shown, the flange 144 extends around the entire perimeter of the shield 140 except for the gap 146. Gap 146 corresponds to or is aligned with notch 124 of PCB 120. In one example, the flange 144 slides under or within a feature (e.g., a tab or channel) of the arm 114. In one example, the flange 144 on the edge corresponding to the edge of the PCB120 that will engage the arm 114 allows the flange to have mechanical contact with the channel or tab, and thus the same securing force used to secure the PCB120 may also secure the shield 140. The gap 146 may be aligned with the notch 124 and, thus, with a tab or feature of the connector 110. For example, the arm 114 may include a protruding element that would fit within the notch 124 and gap 146. Such protruding elements may provide a spring force towards the side (thin side) of the PCB 120. Other tab features of the arm 114 may provide a downward force on the upper surface of the PCB120 (i.e., the surface seen when looking at the schematic of the system 100). The force of pushing or pulling on the upper surface of the PCB120 may also push or pull the flange 144 to secure the shield 140 to the PCB 120.

The straight arrow between PCB120 and connector 110 indicates that PCB120 is inserted into connector 110 in this direction. The curved arrows between the shield 140 and the PCB120 indicate that the shield 140 covers the illustrated surface of the PCB 120. The illustrated surface of the PCB120 includes a plurality of ground pads 130, which may also be referred to as ground pads. The floor pad 130 has an associated spacing 132. The spaces 132 represent spaces between adjacent floor pads 130 along the perimeter of the PCB 120. In one example, the spacing 132 is less than or equal to one-tenth lambda (λ), where λ represents the wavelength of the center frequency of the noise being shielded. For example, for a noise frequency centered at about 5GHz, the wavelength λ v/f 3 × 10 × 8/5 × 10^9 is 0.6 meters, so λ/10 equals 6 mm.

The ground pad 130 provides an electrical connection to a local ground of the PCB 120. The local ground refers to a ground reference for components mounted on the PCB 120. In one example, the ground plane is provided via one or more ground planes within the PCB 120. The ground plane will be understood to be a layer of the plurality of PCBs 120. This ground plane will have some breaks for signal line routing and vias in the PCB. Thus, the plane is not necessarily the exclusive ground conductor on the ground layer, but the primary ground conductor. Although the local ground of the PCB120 is typically electrically coupled to the system ground through the connector 110, the local ground may slightly float off the system ground. The shield 140 may be connected to the ground of the PCB120 and need not be directly connected to the system ground, but rather connected to the system ground through the connector 110. Traditionally, the shield is directly connected to the motherboard ground, for example, by using screws or other electrical connections that are directly tied to the motherboard ground, and additional manufacturing is required to secure the shield. In system 100, shield 140 is connected to a PCB ground, which is then connected to a motherboard ground through connector 110.

In one example, the shield 140 represents a shield for a dual in-line memory module (DIMM), where the PCB120 represents a memory module board. The shield 140 may reduce RFI risk for the client system. The PCB120 includes ground pads 130 for electrical contact between the removable shield and the DIMM. In examples where the DIMM includes a memory device mounted on only one side, the shield 140 may cover that side. In examples where the DIMM includes memory devices on both sides, separate shields may be mounted on either side. The shields on either side may be substantially identical and similarly removable using the same or similar connection and securing mechanisms.

When the PCB120 is a DIMM, the one or more components that generate the EMF noise are Dynamic Random Access Memory (DRAM) devices. As a DIMM, the PCB120 may include notches 124 that align with the alignment tabs of the arms 114. The arm 114 also includes a retention tab that provides a downward spring force on the PCB 120. With the removable optional shield 140 covering at least the DRAM devices on the PCB120, the shield 140 may also include a flange 144 to engage with existing retention tabs. Thus, the retention tabs may also secure the shield to the PCB and ensure contact between the shield 140 and the floor pad 130.

Fig. 1B is a block diagram of an example of the PCB of fig. 1A engaged with a corresponding connector having a local ground pad for the removable shield. System 150 illustrates the interconnection of connector 110 and PCB120, which connector 110 and PCB120 may be the same as connector 110 and PCB120 of fig. 1A. When interconnected, it can be observed that the notch 124 of the PCB120 aligns with a feature of the arm 114 at the PCB-connector interface 152.

Fig. 1C is a block diagram of an example of a PCB having the removable shield of fig. 1A engaged with a local ground pad and attached to a corresponding connector. System 160 illustrates the interconnection of connector 110 and shielded PCB 170, where connector 110 may be the same as connector 110 of fig. 1A, and where shielded PCB 170 may be the same as the combination of PCB120 and shield 140 of fig. 1A. When interconnected, it can be observed that the notch 124 of the shielded PCB 170 aligns with a feature of the arm 114 at the PCB-shield-connector interface 162. The PCB-shield-connector interface 162 interfaces with both the PCB and the shield. It will be appreciated that the shield is removably connected in the system 160, and may be removed. With the PCB-shield-connector interface 162, the flange on the shield contacts the ground pad on the PCB. Thus, securing shielded PCB 170 into connector 110 creates flange-to-ground pad electrical contacts 172.

Fig. 2 is a schematic representation of an example of interconnecting a removable shield to a corresponding connector. System 200 provides an example of system 100 of fig. 1A. Connector 210 represents a connector for coupling the PCB to the system board. The shield 220 has an upper surface which is a surface plane parallel to the plane of the PCB to be covered. The side wall 224 extends from the upper surface 222 towards the PCB to be covered. Considering the orientation with the upper surface 222 as an upper portion, the side wall 224 extends downward toward the PCB.

With reference to the orientation just mentioned, the shield 220 includes a flange 226 at the bottom of the sidewall 224. A flange 226 extends from the side wall 224 and provides a lip around the perimeter of the shield 220 that can engage with features of the arm of the connector 210.

System 200 shows segment 230 and segment 240 with shield 220 engaged with connector 210. Shield 220 represents a removable shield that covers a PCB connected to connector 210. In one example, the shield 220 is slid into the connector 210 and engages a space in the connector 210 at the segment 230 via a locking finger on the shield.

In one example, the shield 220 may be considered a snap-on shield in that after sliding the shield into the connector 210, the shield may be pressed downward (referring to the same orientation as mentioned above) until the locking fingers on the shield 220 and the clip, tab, or flange, or a combination of these mechanisms, lock the shield and PCB in place. Segment 240 shows a locking clip or spring tab 250. Spring tabs 250 represent clips or tabs that apply a spring force or provide a force to flange 226 to secure shield 220 to a corresponding PCB (not specifically shown) and connector 210. In one example, the shield 220 presses the spring tab 250 downward until pressed past the tab, and then the spring tab 250 will press against the flange 226. With the flange 226 engaged with the arm of the connector 210 and the lock fingers locked into place with the connector 210, the shield is secured to the PCB and electrically engages the PCB ground.

FIG. 3A is a schematic diagram representing an example of electromagnetic noise from an unshielded device. The schematic 302 shows radiated noise emitted from an unshielded device 310. The unshielded device may be, for example, a DDR DIMM. A darker color indicates a higher energy intensity. As shown, the unshielded device 310 results in high noise radiation 312.

FIG. 3B is a schematic diagram representing an example of electromagnetic noise from a shielded device. Diagram 304 shows a relative comparison with diagram 302. Shielded device 320 represents the same device including a removable shield according to the description herein. The same device (e.g., DDR DIMM) results in lower noise radiation 322. The dashed circle area indicates the same space in the schematic 304 as shown in the schematic 302. Thus, it will be observed how in the schematic 304 significantly less noise energy is emitted.

As shown, the shield produces greater than 20dB shielding effectiveness against DIMM noise radiation over a wide frequency range compared to the unshielded device 310. The shielded device 320 is also compared to a device having a floating (ungrounded) shield, which is not specifically shown, but the emitted energy has a similar noise intensity as the schematic 302. Thus, the described grounded shield provides greater than 20dB shielding effectiveness compared to a comparable DIMM with a floating shield.

Fig. 4A-4D are schematic representations of examples of grounding a shield to a local Printed Circuit Board (PCB). Schematic 402, schematic 404, schematic 406, and schematic 408 are directed to fig. 4A, 4B, 4C, and 4D, respectively. As shown in the schematic, the contact mechanism between the shield and the PCB floor pad may be any combination of a perforated shield surface or a flat shield surface and a protruding floor pad or a flat floor pad. The schematic diagram shows only the combination between one protruding surface and one flat surface, but the implementation is not limited to the configuration shown. Other means and configurations may also be used. The particular shape of the protrusions shown is not necessarily representative, and any shape and size may be used.

Referring to schematic diagram 402, PCB 410 includes a short Ground (GND) pad 412. Where high precision is used in the manufacture of the shield and in securing the shield to the PCB 410 and corresponding connector, short ground pads may be used. Shield 420 represents a shield according to any example herein. The components labeled shield 420 represent cross-sectional portions of the flanges of the shield.

The shield 420 includes a perforated shield surface 422 that creates a protrusion from the bottom surface of the flange toward the PCB. The perforated shield surface 422 engages the flat PCB contact 414. The interconnection between the perforated surface of the shield 420 and the flat PCB contact 414 provides an electrical connection for the shield to ground, which may be maintained by spring force rather than by a type of binding. The interconnection between the perforated surface of the shield 420 and the flat PCB contact 414 will be understood to create a small space between the shield and the PCB, but the spacing will be very small. The intervals as shown in diagram 402 are not necessarily to scale.

Referring to the schematic view 404, the PCB 430 includes a long ground pad 432. In cases where high accuracy cannot be ensured by the engagement between the shield 440 and the PCB 430, a long ground pad may be used. Shield 440 represents a shield according to any example herein. The assembly labeled shield 440 represents a cross-sectional portion of the flange of the shield.

The shield 440 includes a perforated shield surface 442 that creates a protrusion from the bottom surface of the flange toward the PCB. The perforated shield surface 442 engages the flat PCB contact 434. The interconnection between the perforated surface of the shield 440 and the flat PCB contact 434 provides the shield with an electrical connection to ground, which may be maintained by spring force rather than by one type of binding. The elements shown in diagram 404 are not necessarily to scale.

Referring to the schematic view 406, the PCB 450 includes a short ground pad 452. Short ground pads may be used with high accuracy ensured by the engagement between the shield 460 and the PCB 450. Shield 460 represents a shield according to any example herein. The components labeled shield 460 represent the cross-sectional portion of the flange of the shield.

Shield 460 includes a flat shield surface 462. The flat shield surface 462 engages the protruding PCB contact 454, which protruding PCB contact 454 protrudes above the surface of the PCB. The interconnection between the flat surface of the shield 460 and the protruding PCB contact 454 provides the shield with an electrical connection to ground, which may be maintained by spring force rather than by one type of binding. The elements shown in diagram 406 are not necessarily to scale.

Referring to the schematic view 408, the PCB 470 includes a long floor pad 472. In cases where high accuracy cannot be ensured by engagement between the shield 480 and the PCB 470, a long ground pad may be used. Shield 480 represents a shield according to any example herein. The component labeled shield 480 represents a cross-sectional portion of the flange of the shield.

The shield 480 includes a flat shield surface 482. The flat shield surface 482 engages a protruding PCB contact 474 that protrudes above the surface of the PCB. The interconnection between the flat surface of the shield 480 and the protruding PCB contact 474 provides the shield with an electrical connection to ground, which may be maintained by spring force rather than by a type of binding. The elements shown in diagram 408 are not necessarily to scale.

Fig. 5 is a block diagram of an example of a PCB assembly surrounded by a grounded shield. System 500 provides an example of a PCB with shielding according to any example herein. The system 500 includes a PCB 510 with components 530 covered by a shield 520. The perspective view of system 500 is a side view of a PCB with a shield.

Component 530 represents the active components of PCB 510 that generate EMI noise. The tops of the components 530 are shown in dashed lines as they will be understood to be behind or within the shielding of the shield 520. It will be understood that the schematic view represents only a portion of the plate and shield, and that the assembly 530 may extend outside of the image shown.

The shield 520 has an upper surface 524, which upper surface 524 is a surface parallel to the component surface of the PCB 510. The shield 520 also has sidewalls 526 to extend from the upper surface 524 toward the PCB 510. A sidewall 526 connects the upper surface 524 to the flange 522. The flange 522 provides a feature in the shield 520 for allowing mechanical connection of the shield with the PCB 510 and associated connector. The connector may include tabs or other features for pressing onto the flange to press the shield 520 toward the PCB 510.

System 500 includes PCB-to-shield contacts 512. The contacts are shown in system 500 as PCB-to-shield contacts 512, which may be understood to include ground pads on PCB 510 and flanges 522 of shield 520. PCB-to-shield contact 512 may be any combination of a protruding PCB ground contact, a perforated shield protrusion in a flange, a flat PCB ground contact, a flat shield flange, or some other mechanism for creating a contact. Typically, PCB shield contacts will provide the most reliable electrical contact when there is one protruding side and another flat side. Electrical contacts refer to electrical contacts to ground that may ground the shield 520 to a local ground plane of the PCB 510. It will be appreciated that the flat flange and protruding PCB contact may require more complex manufacturing of the PCB contact, but may provide the most reliable contact, rather than having the protruding perforated area of the flange in contact with a flat pad on the PCB.

System 500 shows a space 514 between PCB-shield contacts 512. The spacing 514 may be consistent with that described above, having a distance corresponding to λ/10. System 500 also shows an air gap 540, which air gap 540 represents the space between flange 522 and PCB 510 that is formed due to PCB-to-shield contact 512. The protruding segments of the electrical contacts result in small gaps. In one example, the gap is small enough to be relatively unobvious, but does show contact via the protruding elements.

Fig. 6 is a flow chart of an example of a process for applying a grounded-on-demand shield. Process 600 represents a process for providing a demand-based removable shield. For PCBs with components that generate RF (radio frequency) noise during active use, the designer creates a ground pad for shielding on the PCB at 602.

In one example, a system designer determines at 604 whether to provide a protruding or a flat ground pad on a PCB. When a protruding floor pad is to be used, the system designer may provide the protruding floor pad on the PCB at 606. When a flat floor pad is to be used, the system designer may provide a flat floor pad on the PCB at 608.

In one example, the length of the floor mat is dependent on the precision to be applied to the assembly process and to the assembly of the system together. In one example, if the alignment tolerance is relatively high at 610, the system designer may provide a short ground pad on the PCB at 612. In one example, if the alignment tolerance is relatively low at 610, the system designer may provide a longer ground pad on the PCB at 614.

In one example, the system designer has the option of providing a shield on the PCB that is grounded or not using a shield on the PCB. In one example, if shielding is needed (yes branch of 616), then at 618 manufacturing may attach the shield and secure it with a corresponding connector for the PCB that also connects the shield to the PCB. In one example, if shielding is not needed (no branch of 616), the manufacturing may remove the shielding at 620.

FIG. 7 is a block diagram of an example of a memory subsystem in which grounded shielding may be implemented. System 700 includes elements of a processor and memory subsystem in a computing device.

In one example, system 700 includes a grounded shield 780 on memory module 770. Grounded shield 780 may be in accordance with any of the shields described herein. Grounded shield 780 is interconnected to ground contacts on memory module 770. Grounded shield 780 includes mechanical features for engaging with a connector that couples memory module 770 to memory controller 720 and processor 710. These features secure the shield in a non-permanent manner, thereby providing a removable shield.

Processor 710 represents a processing unit of a computing platform that may execute an Operating System (OS) and applications, which may be collectively referred to as a host or user of memory. The OS and applications perform operations that result in memory accesses. Processor 710 may include one or more individual processors. Each individual processor may include a single processing unit, a multi-core processing unit, or a combination thereof. The processing unit may be a main processor such as a CPU (central processing unit), a peripheral processor such as a GPU (graphics processing unit), or a combination thereof. Memory access may also be initiated by a device such as a network controller or a hard disk controller. Such a device may be integrated with the processor in some systems, or attached to the processor via a bus (e.g., PCI express), or a combination thereof. The system 700 may be implemented as an SOC (system on a chip) or may be implemented with stand-alone components.

References to memory devices may apply to different memory types. Memory devices generally refer to volatile memory technology. Volatile memory is memory that: the state of the memory (and thus the data stored on the memory) is indeterminate if power is interrupted to the device. Non-volatile memory refers to memory that: the state of the memory is determined even if power to the device is interrupted. Dynamic volatile memories require refreshing of data stored in the device to maintain state. One example of dynamic volatile memory includes DRAM (dynamic random access memory) or some variants, e.g., synchronous DRAM (sdram). The memory subsystem as described herein may be compatible with a variety of memory technologies: for example, DDR4(DDR version 4, JESD79, initial specification published by JEDEC in month 9 2012), LPDDR4 (low power DDR version 4, JESD209-4, originally published by JEDEC in month 8 2014), WIO2 (wide I/O2 (wide IO2), JESD229-2, originally published by JEDEC in month 8 2014), HBM (high bandwidth memory DRAM, JESD235A, originally published by JEDEC in month 11 2015), DDR5(DDR version 5, currently discussed by JEDEC), LPDDR low power dr5(DDR version 5, JESD209-5 published by JEDEC in month 2 2019), HBM2((HBM version 2), currently discussed by JEDEC), or other memory technologies or combinations of memory technologies, as well as derivatives or extended technologies based on these specifications.

In addition to or instead of volatile memory, in one example, a reference to a memory device may refer to a non-volatile memory device that: the state of the non-volatile memory device is determined even if power to the device is interrupted. In one example, the non-volatile memory devices are block addressable memory devices, e.g., NAND or NOR technologies. Thus, the memory devices may also include future generations of nonvolatile devices, such as three-dimensional cross-point memory devices, other byte-addressable nonvolatile memory devices, or memory devices using chalcogenide phase change materials (e.g., chalcogenide glass). In one example, the memory device may be or include multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM) or phase change memory with Switch (PCMs), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), Magnetoresistive Random Access Memory (MRAM) memory or Spin Transfer Torque (STT) -MRAM in combination with memristor technology, or a combination of any of the above, or other memory.

The description herein referring to "RAM" or "RAM device" may apply to any memory device, whether volatile or non-volatile, that allows random access. The description referring to "DRAM" or "DRAM device" may refer to volatile random access memory devices. A memory device or DRAM may refer to the die itself, to a packaged memory product including one or more dies, or both. In one example, a system having volatile memory that needs to be refreshed may also include non-volatile memory.

Memory controller 720 represents one or more memory controller circuits or devices for system 700. Memory controller 720 represents the control logic that generates memory access commands in response to the execution of operations by processor 710. Memory controller 720 accesses one or more memory devices 740. Memory device 740 may be a DRAM device consistent with any of the devices mentioned above. In one example, memory device 740 is organized and managed as different channels, where each channel is coupled to a bus and signal lines of multiple memory devices in parallel. Each channel is independently operable. Thus, each channel is independently accessed and controlled, and timing, data transfer, command and address exchanges, and other operations are independent for each channel. Coupling may refer to electrical coupling, communicative coupling, physical coupling, or a combination of these. Physical coupling may include direct contact. The electrical coupling includes an interface or interconnect that allows electrical current between the components or allows signaling between the components, or both. The communicative coupling includes connections (including wired or wireless) that enable the components to exchange data.

In one example, the settings for each channel are controlled by a separate mode register or other register setting. In one example, each memory controller 720 manages a separate memory channel, but system 700 may be configured with multiple channels managed by a single controller, or with multiple controllers on a single channel. In one example, memory controller 720 is part of host processor 710, e.g., logic implemented on the same die or in the same package space as the processor.

Memory controller 720 includes I/O interface logic 722 to couple to a memory bus, such as the memory channel mentioned above. The I/O interface logic 722 (and I/O interface logic 742 of the memory device 740) may include pins, pads, connectors, signal lines, traces, or wires, or other hardware for connecting devices, or a combination of these. I/O interface logic 722 may include a hardware interface. As shown, I/O interface logic 722 includes at least a driver/transceiver for signal lines. Typically, wires within an integrated circuit interface are coupled with pads, pins, or connectors to join signal lines or traces or other wires between devices. I/O interface logic 722 may include a driver, receiver, transceiver or terminal, or other circuit or combination of circuits to exchange signals on signal lines between devices. The exchange of signals includes at least one of transmission or reception. Although shown as I/O742 coupling I/O722 from memory controller 720 to memory device 740, it will be understood that in implementations of system 700 in which groups of memory devices 740 are accessed in parallel, multiple memory devices may include I/O interfaces to the same interface of memory controller 720. In implementations of system 700 that include one or more memory modules 770, I/O742 may include interface hardware for the memory modules in addition to interface hardware on the memory devices themselves. Other memory controllers 720 will include separate interfaces to other memory devices 740.

The bus between memory controller 720 and memory device 740 may be implemented as a plurality of signal lines coupling memory controller 720 to memory device 740. The bus may typically include at least a Clock (CLK)732, a command/address (CMD)734, and write Data (DQ) and read Data (DQ)736, as well as zero or more other signal lines 738. In one example, the bus or connection between memory controller 720 and the memory may be referred to as a memory bus. The signal lines for the CMD may be referred to as a "C/A bus" (or ADD/CMD bus, or some other design that indicates the transfer of command (C or CMD) and address (A or ADD) information), and the signal lines for writing and reading DQ may be referred to as a "data bus". In one example, the separate channels have different clock signals, C/A buses, data buses, and other signal lines. Thus, system 700 may be considered to have multiple "buses," in the sense that the separate interface paths may be considered to be separate buses. It will be understood that the bus may include at least one of a strobe signaling line, an alarm line, an auxiliary line, or other signal lines, or combinations thereof, in addition to the lines explicitly shown. It will also be appreciated that serial bus technology may be used for the connection between memory controller 720 and memory device 740. An example of a serial bus technology is 8B10B encoding and transmission of high speed data through a single differential pair of signals in each direction with an embedded clock. In one example, CMD 734 represents signal lines shared in parallel with multiple memory devices. In one example, the coded command signal lines of CMD 734 are shared by multiple memory devices, and each memory device has a separate chip select (CS _ n) signal line to select a separate memory device.

It will be appreciated that in the example of system 700, the buses between memory controller 720 and memory devices 740 include an auxiliary command bus CMD 734 and an auxiliary bus DQ 736 for carrying write data and read data. In one example, the data bus may include bidirectional lines for read data and for write/command data. In another example, the auxiliary bus DQ 736 may include unidirectional write signal lines for writing data from the host to the memory, and may include unidirectional lines for reading data from the memory to the host. Other signal lines 738 may accompany a bus or sub-bus such as strobe lines DQS depending on the memory technology and system design selected. The data bus may have more or less bandwidth per memory device 740, based on the design of the system 700, or based on the implementation if the design supports multiple implementations. For example, the data bus may support memory devices having an x32 interface, an x16 interface, an x8 interface, or other interfaces. The convention "xW" denotes the number of signal lines used to exchange data with memory controller 720, where W is an integer that refers to the interface size or width of the interface of memory device 740. The interface size of the memory devices is a controlling factor on how many memory devices can be used simultaneously per channel or coupled in parallel to the same signal line in system 700. In one example, a high bandwidth memory device, a wide interface device, or a stacked memory configuration, or a combination thereof, may implement a wider interface, e.g., an x128 interface, an x256 interface, an x512 interface, an x1024 interface, or other data bus interface width.

In one example, memory device 740 and memory controller 720 exchange data over a data bus in a sequence of bursts or consecutive data transfers. The burst corresponds to the number of transmission cycles related to the bus frequency. In one example, a transmission cycle may be an entire clock cycle for transmissions that occur on the same clock or strobe signal edge (e.g., on a rising edge). In one example, each clock cycle (referring to the period of the system clock) is divided into a plurality of Unit Intervals (UIs), where each UI is one transmission cycle. For example, double data rate transmission triggers on two edges (e.g., a rising edge and a falling edge) of a clock signal. The burst may last a configured number of UIs, which may be a configuration stored in a register, or may be triggered on the fly. For example, a sequence of eight consecutive transfer cycles may be considered a burst length of 8(BL8), and each memory device 740 may transfer data on each UI. Thus, an x8 memory device operating on BL8 may transfer 64 bits of data (8 data signal lines multiplied by 8 bits of data transferred per line in a burst). It will be understood that this simple example is by way of illustration only and not by way of limitation.

Memory device 740 represents a memory resource for system 700. In one example, each memory device 740 is a separate memory die. In one example, each memory device 740 may interface with multiple (e.g., 2) channels per device or die. Each memory device 740 includes I/O interface logic 742, the I/O interface logic 742 having a bandwidth determined by the implementation of the device (e.g., x16 or x8 or some other interface bandwidth). I/O interface logic 742 enables the memory devices to interface with memory controller 720. The I/O interface logic 742 may comprise a hardware interface and may be consistent with the I/O722 of the memory controller, but on the memory device side. In one example, multiple memory devices 740 are connected in parallel to the same command bus and data bus. In another example, multiple memory devices 740 are connected in parallel to the same command bus and to different data buses. For example, system 700 may be configured with multiple memory devices 740 coupled in parallel, where each memory device responds to commands and accesses memory resources 760 that are internal to each memory device. For a write operation, a single memory device 740 may write a portion of the entire data word, and for a read operation, a single memory device 740 may retrieve a portion of the entire data word. As a non-limiting example, a particular memory device may provide or receive 8-bits or 16-bits (depending on the x8 device or the x16 device) of an 8-bit or 256-bit data word, respectively, of a 128-bit data word for a read or write transaction. The remaining bits of the word will be provided or received in parallel by other memory devices.

In one example, the memory device 740 is disposed directly on a motherboard of a computing device or a host system platform (e.g., a PCB (printed circuit board) on which the processor 710 is disposed). In one example, memory device 740 may be organized as a memory module 770. In one example, memory module 770 represents a dual in-line memory module (DIMM). In one example, memory module 770 represents other organization of multiple memory devices to share at least a portion of the access or control circuitry, which may be separate circuitry, separate device, or separate board from the host system platform. Memory module 770 may include multiple memory devices 740 and a memory module may include support for multiple separate channels to included memory devices disposed on the memory module. In another example, the memory device 740 may be incorporated into the same package as the memory controller 720, for example, by techniques such as multi-chip modules (MCM), package-on-package, through-silicon vias (TSV), or other techniques or combinations. Similarly, in one example, multiple memory devices 740 may be incorporated into memory module 770, which memory module 770 itself may be incorporated into the same package as memory controller 720. It will be appreciated that for these and other implementations, memory controller 720 may be part of host processor 710.

Memory devices 740 each include memory resources 760. Memory resource 760 represents a memory location or a separate array of storage locations for data. Typically, memory resources 760 are managed as rows of data, which are accessed via word line (row) and bit line (individual bits within a row) controls. Memory resources 760 may be organized as separate channels, columns (rank) and banks (bank) of memory. A channel may refer to an independent control path to a storage location within memory device 740. A column may refer to a common location across multiple memory devices (e.g., the same row address within different devices). A bank may refer to an array of memory locations within memory device 740. In one example, the banks of the memory are divided into sub-banks, with at least a portion of the shared circuitry (e.g., drivers, signal lines, control logic) being used for the sub-banks, allowing for separate addressing and access. It will be appreciated that channels, columns, banks, sub-banks, groups of banks, or other organizations of memory locations, as well as combinations of these organizations, may overlap in their application to physical resources. For example, the same physical memory location may be accessed through a particular channel as a particular bank (which may also belong to a column). Thus, the organization of memory resources will be understood in an inclusive rather than exclusive manner.

In one example, memory device 740 includes one or more registers 744. Registers 744 represent one or more storage devices or storage locations that provide configurations or settings for the operation of the memory devices. In one example, registers 744 may provide storage locations for memory device 740 to store data for access by memory controller 720 as part of control or management operations. In one example, registers 744 include one or more mode registers. In one example, registers 744 include one or more multipurpose registers. The configuration of the location within registers 744 may configure memory device 740 to operate in different "modes," where the command information may trigger different operations within memory device 740 based on the mode. Additionally or in the alternative, different modes may also trigger different operations depending on the mode, depending on address information or other signal lines. The settings of registers 744 may indicate a configuration for the I/O settings (e.g., timing, termination or ODT (on die termination) 746, driver configuration, or other I/O settings).

In one example, memory device 740 includes ODT746 as part of the interface hardware associated with I/O742. ODT746 may be configured as mentioned above and provides a setting for applying impedance to the interface to the designated signal line. In one example, ODT746 is applied to the DQ signal lines. In one example, ODT746 is applied to the command signal lines. In one example, ODT746 is applied to the address signal lines. In one example, ODT746 may be applied to any combination of the aforementioned signal lines. The ODT setting may be changed based on whether the memory device is a selected target or non-target device of an access operation. ODT746 settings may affect the timing and reflection of signaling on the terminated lines. Careful control of the ODT746 may enable higher speed operation with improved matching of applied impedance and load. ODT746 may be applied to designated signal lines of I/O interfaces 742, 722, and need not be applied to all signal lines.

Memory device 740 includes a controller 750 that represents control logic within the memory device for controlling internal operations within the memory device. For example, controller 750 decodes a command sent by memory controller 720 and generates internal operations to execute or satisfy the command. The controller 750 may be referred to as an internal controller and is separate from the memory controller 720 of the host. Controller 750 may determine which mode to select based on registers 744 and configure internal execution of operations for accessing memory resources 760 or other operations based on the selected mode. Controller 750 generates control signals to control the routing of bits within memory device 740 to provide the appropriate interface for the selected mode and to direct commands to the appropriate memory location or address. The controller 750 includes command logic 752, which command logic 752 may decode command encodings received on the command and address signal lines. Thus, the command logic 752 may be or include a command decoder. Using command logic 752, the memory device may identify commands and generate internal operations to execute the requested commands.

Referring again to memory controller 720, memory controller 720 includes Command (CMD) logic 724, with CMD logic 724 representing the logic or circuitry for generating commands to be sent to memory device 740. The generation of a command may refer to a command prior to scheduling, or preparation of a queued command ready to be sent. Typically, signaling in the memory subsystem includes address information within or accompanying the command to indicate or select one or more memory locations in which the memory device should execute the command. In response to the scheduling of transactions for memory device 740, memory controller 720 may issue commands via I/O722 to cause memory device 740 to execute the commands. In one example, controller 750 of memory device 740 receives and decodes command and address information received from memory controller 720 via I/O742. Based on the received command and address information, controller 750 may control the timing of the operation of logic and circuitry within memory device 740 to execute the commands. The controller 750 is responsible for complying with standards or specifications within the memory device 740, such as timing and signaling requirements. Memory controller 720 may achieve compliance with a standard or specification by accessing scheduling and control.

Memory controller 720 includes a scheduler 730, which scheduler 730 represents logic or circuitry to generate and order transactions to be sent to memory device 740. From one perspective, it may be considered that a primary function of memory controller 720 is to schedule memory accesses and other transactions to memory device 740. Such scheduling may include generating the transaction itself to implement requests by the processor 710 for data and to maintain the integrity of the data (e.g., with commands related to refresh). A transaction may include one or more commands and result in the transmission of commands or data or both over one or more timing cycles (e.g., clock cycles or unit intervals). Transactions may be for access (e.g., read or write or related commands or combinations), and other transactions may include memory management commands for configuration, setting, data integrity, or other commands or combinations.

Memory controller 720 typically includes logic, such as scheduler 730, to allow the selection and ordering of transactions to improve the performance of system 700. Thus, memory controller 720 may select which of the outstanding transactions should be sent to memory device 740 in which order, typically implemented using logic that is much more complex than a simple first-in-first-out algorithm. Memory controller 720 manages the transmission of transactions to memory device 740 and manages the timing associated with the transactions. In one example, the transaction has deterministic timing that can be managed by the memory controller 720 and used to determine how to schedule the transaction with the scheduler 730.

In one example, memory controller 720 includes Refresh (REF) logic 726. Refresh logic 726 may be used for memory resources that are volatile and need to be refreshed to maintain a deterministic state. In one example, the refresh logic 726 indicates a location for the refresh and a type of refresh to perform. The refresh logic 726 may trigger a self-refresh within the memory device 740, or perform an external refresh (which may be referred to as an auto-refresh command) by sending a refresh command, or a combination thereof. In one example, system 700 supports all bank refreshes as well as each bank refresh. All bank refreshes result in the refresh of banks within all memory devices 740 coupled in parallel. Each bank refresh results in a refresh of a specified bank within the specified memory device 740. In one example, controller 750 within memory device 740 includes refresh logic 754 to apply refreshes within memory device 740. In one example, refresh logic 754 generates internal operations to perform refreshes in accordance with external refreshes received from memory controller 720. Refresh logic 754 may determine whether to direct a refresh to memory device 740 and, in response to a command, what memory resources 760 to refresh.

Fig. 8 is a block diagram of an example of a computing system in which a grounded shield may be implemented. System 800 represents a computing device according to any example herein, and may be a laptop computer, desktop computer, tablet computer, server, gaming or entertainment control system, embedded computing device, or other electronic device.

In one example, system 800 includes a grounded shield 890 on memory 830 (e.g., on a memory module providing memory 830 to system 800). The grounded shield 890 may be in accordance with any of the shields described herein. Grounded shield 890 is interconnected to a ground contact on memory 830. Grounded shield 890 includes mechanical features for engaging with a connector that couples memory 830 to memory controller 822. These features secure the shield in a non-permanent manner, thereby providing a removable shield.

System 800 includes a processor 810, which processor 810 may include any type of microprocessor, Central Processing Unit (CPU), Graphics Processing Unit (GPU), processing core, or other processing hardware or combination to provide for the processing or execution of instructions for system 800. Processor 810 controls the overall operation of system 800 and may be or include one or more programmable general purpose or special purpose microprocessors, Digital Signal Processors (DSPs), programmable controllers, Application Specific Integrated Circuits (ASICs), Programmable Logic Devices (PLDs), or a combination of these devices.

In one example, system 800 includes an interface 812 coupled to processor 810, which interface 812 may represent a higher speed interface or a high throughput interface for system components (e.g., memory subsystem 820 or graphics interface component 840) that require higher bandwidth connections. Interface 812 represents interface circuitry that may be a separate component or integrated onto the processor die. The interface 812 may be integrated as a circuit on the processor die or as a component on the system-on-chip. In the case of graphical interface 840, graphical interface 840 interfaces with graphical components to provide a visual display to a user of system 800. Graphics interface 840 may be a separate component or integrated onto a processor die or system on a chip. In one example, the graphical interface 840 may drive a High Definition (HD) display that provides output to a user. In one example, the display may comprise a touch screen display. In one example, graphics interface 840 generates a display based on data stored in memory 830 or based on operations performed by processor 810, or both.

Memory subsystem 820 represents the main memory of system 800 and provides storage for code to be executed by processor 810 or data values to be used in executing routines. Memory subsystem 820 may include one or more memory devices 830, such as Read Only Memory (ROM), flash memory, one or more variations of Random Access Memory (RAM) (e.g., DRAM), or other memory devices, or a combination of these devices. Memory 830 stores and hosts, among other things, an Operating System (OS)832 to provide a software platform for execution of instructions in system 800. Additionally, applications 834 may execute on the software platform of OS 832 from memory 830. Application 834 represents a program having its own operating logic to perform the execution of one or more functions. Process 836 represents an agent or routine that provides auxiliary functionality to OS 832 or one or more applications 834, or a combination thereof. OS 832, applications 834 and processes 836 provide software logic to provide functionality for system 800. In one example, memory subsystem 820 includes memory controller 822, which memory controller 822 is a memory controller for generating and issuing commands to memory 830. It will be appreciated that the memory controller 822 may be a physical part of the processor 810 or a physical part of the interface 812. For example, the memory controller 822 can be an integrated memory controller integrated onto a circuit having the processor 810 (e.g., onto a processor die or system on a chip).

Although not specifically shown, it will be understood that system 800 may include one or more buses or one or more bus systems between devices, such as a memory bus, a graphics bus, an interface bus, etc. A bus or other signal line may communicatively and electrically couple the components together or otherwise. A bus may include physical communication lines, point-to-point connections, bridges, adapters, controllers, or other circuits or combinations. A bus may include, for example, one or more or a combination of a system bus, a Peripheral Component Interconnect (PCI) bus, a hypertransport or Industry Standard Architecture (ISA) bus, a Small Computer System Interface (SCSI) bus, a Universal Serial Bus (USB), or other bus.

In one example, system 800 includes an interface 814, which interface 814 can be coupled to interface 812. Interface 814 may be a lower speed interface than interface 812. In one example, interface 814 represents interface circuitry that may include individual components and integrated circuits. In one example, a plurality of user interface components or peripheral components or both are coupled to the interface 814. Network interface 850 provides system 800 with the ability to communicate with remote devices (e.g., servers or other computing devices) over one or more networks. Network interface 850 may include an ethernet adapter, a wireless interconnect component, a cellular network interconnect component, USB (universal serial bus), or other interface or proprietary interface based on a wired or wireless standard. Network interface 850 may exchange data with remote devices, which may include transmitting data stored in memory or receiving data to be stored in memory.

In one example, system 800 includes one or more input/output (I/O) interfaces 860. I/O interface 860 may include one or more interface components through which a user interacts (e.g., audio, alphanumeric, tactile/touch, or other interface) with system 800. Peripheral interface 870 may include any hardware interface not specifically mentioned above. A peripheral device generally refers to a device that is dependently connected to the system 800. A dependent connection is one in which the system 800 provides a software platform or a hardware platform or both on which operations are performed and with which a user interacts.

In one example, system 800 includes a storage subsystem 880 for storing data in a nonvolatile manner. In one example, in some system implementations, at least some components of storage 880 may overlap with components of memory subsystem 820. Storage subsystem 880 includes storage device(s) 884, which storage device(s) 884 can be or include any conventional medium for storing large amounts of data in a non-volatile manner, such as one or more magnetic, solid state, or optical based disks or a combination thereof. The storage 884 holds the code or instructions and data 886 in a persistent state (i.e., the values are retained despite the interruption of power to the system 800). The storage 884 may generally be considered "memory," although the memory 830 is typically an execution or manipulation memory for providing instructions to the processor 810. Although storage 884 is non-volatile, memory 830 may include volatile memory (i.e., the value or state of data is indeterminate if power is interrupted to system 800). In one example, storage subsystem 880 includes a controller 882 for interfacing with storage 884. In one example, the controller 882 is a physical part of the interface 814 or the processor 810, or may include circuitry or logic in both the processor 810 and the interface 814.

Power supply 802 provides power to the components of system 800. More specifically, power supply 802 typically interfaces with one or more power supplies 804 in system 800 to provide power to the components of system 800. In one example, power supply 804 includes an AC to DC (alternating current to direct current) adapter for plugging into a wall outlet. Such AC power may be a renewable energy (e.g., solar) power source 802. In one example, the power supply 802 comprises a DC power supply, e.g., an external AC to DC converter. In one example, the power supply 802 or power supply 804 includes wireless charging hardware to charge via proximity to a charging field. In one example, the power source 802 may include an internal battery or fuel cell source.

Fig. 9 is a block diagram of an example of a mobile device in which a grounded shield may be implemented. Device 900 represents a mobile computing device, such as a computing tablet, mobile or smart phone, wearable computing device, or other mobile or embedded computing device. It will be understood that certain of the components are shown generally, and not all of the components of such a device are shown in device 900.

In one example, system 900 includes a grounded shield 990 on memory 962 (e.g., on a memory module providing memory 962 to system 900). The grounded shield 990 may be any shield according to the description herein. Grounded shield 990 is interconnected to ground contacts on memory 962. Grounded shield 990 includes mechanical features for engaging with a connector that couples memory 962 to memory controller 964. These features secure the shield in a non-permanent manner, thereby providing a removable shield.

The device 900 includes a processor 910, the processor 910 performing the primary processing operations of the device 900. Processor 910 may include one or more physical devices, such as a microprocessor, application processor, microcontroller, programmable logic device, or other processing module. The processing operations performed by the processor 910 include the execution of an operating platform or operating system on which applications and device functions are executed. The processing operations include operations related to I/O (input/output) of a human user or other device, operations related to power management, operations related to connecting the device 900 to another device, or a combination thereof. The processing operations may also include operations related to audio I/O, display I/O, or other interfacing, or a combination thereof. The processor 910 may execute data stored in a memory. The processor 910 may write or edit data stored in the memory.

In one example, the system 900 includes one or more sensors 912. Sensor 912 represents an embedded sensor or an interface to an external sensor or a combination thereof. The sensors 912 enable the system 900 to monitor or detect one or more conditions of the environment or device in which the system 900 is implemented. The sensors 912 may include environmental sensors (e.g., temperature sensors, motion detectors, light detectors, cameras, chemical sensors (e.g., carbon monoxide, carbon dioxide, or other chemical sensors)), pressure sensors, accelerometers, gyroscopes, medical or physiological sensors (e.g., biosensors, heart rate monitors, or other sensors for detecting physiological properties), or other sensors or combinations thereof. The sensors 912 may also include sensors for biometric systems, such as fingerprint recognition systems, facial detection or recognition systems, or other systems that detect or recognize user features. Sensor 912 should be understood broadly and is not limited to the many different types of sensors that may be implemented with system 900. In one example, the one or more sensors 912 are coupled to the processor 910 via front-end circuitry integrated with the processor 910. In one example, one or more sensors 912 are coupled to the processor 910 via another component of the system 900.

In one example, device 900 includes an audio subsystem 920, the audio subsystem 920 representing hardware (e.g., audio hardware and audio circuitry) and software (e.g., drivers, codecs) components associated with providing audio functionality to the computing device. The audio functions may include speaker or headphone output, and microphone input. Devices for such functions may be integrated into device 900 or connected to device 900. In one example, a user interacts with device 900 by providing audio commands that are received and processed by processor 910.

Display subsystem 930 represents hardware (e.g., display devices) and software components (e.g., drivers) that provide visual displays for presentation to a user. In one example, the display includes a haptic assembly or touch screen element that the user uses to interact with the computing device. The display subsystem 930 includes a display interface 932 that includes a particular screen or hardware device for providing a display to a user. In one example, the display interface 932 includes logic separate from the processor 910 (e.g., a graphics processor) to perform at least some processing related to a display. In one example, display subsystem 930 includes a touch screen device that provides both output and input to a user. In one example, the display subsystem 930 includes a High Definition (HD) or Ultra High Definition (UHD) display that provides output to a user. In one example, the display subsystem includes or drives a touch screen display. In one example, display subsystem 930 generates display information based on data stored in memory or based on operations performed by processor 910, or both.

I/O controller 940 represents hardware devices and software components related to user interaction. I/O controller 940 may operate to manage hardware that is part of audio subsystem 920 or display subsystem 930, or both. Additionally, I/O controller 940 illustrates a connection point for additional devices connected to device 900 through which a user may interact with the system. For example, devices that may be attached to device 900 may include a microphone device, a speaker or stereo system, a video system or other display device, a keyboard or keypad device, or other I/O devices used with a particular application, such as a card reader or other device.

As mentioned above, the I/O controller 940 may interact with the audio subsystem 920 or the display subsystem 930, or both. For example, input through a microphone or other audio device may provide input or commands for one or more applications or functions of device 900. Additionally, audio output may be provided instead of or in addition to display output. In another example, if the display subsystem includes a touch screen, the display device also serves as an input device, which may be managed at least in part by I/O controller 940. Additional buttons or switches may also be present on device 900 to provide I/O functions managed by I/O controller 940.

In one example, I/O controller 940 manages devices such as accelerometers, cameras, light or other environmental sensors, gyroscopes, Global Positioning Systems (GPS), or other hardware or sensors 912 that may be included in device 900. The input may be part of direct user interaction, as well as providing environmental input to the system to affect its operation (e.g., filtering noise, adjusting display for brightness detection, applying a flash or other feature for the camera).

In one example, device 900 includes power management 950 that manages battery power usage, charging of the battery, and features related to power saving operations. The power management 950 manages power from a power supply 952, which power supply 952 provides power to the components of the system 900. In one example, power supply 952 includes an AC to DC (alternating current to direct current) adapter for plugging into a wall outlet. Such AC power may be a renewable energy source (e.g., solar, motion-based power). In one example, the power supply 952 includes only DC power, which may be provided by a DC power source such as an external AC-to-DC converter. In one example, power supply 952 includes wireless charging hardware to charge via proximity to a charging field. In one example, power supply 952 may include an internal battery or fuel cell source.

Memory subsystem 960 includes memory device(s) 962 for storing information in device 900. Memory subsystem 960 may include non-volatile (state does not change if power to the memory device is interrupted) or volatile (state is indeterminate if power to the memory device is interrupted) memory devices or a combination thereof. Memory 960 may store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of system 900. In one example, memory subsystem 960 includes a memory controller 964 (which may also be considered part of the controls of system 900, and may potentially be considered part of processor 910). Memory controller 964 includes a scheduler to generate and issue commands to control access to memory devices 962.

Connectivity 970 includes hardware devices (e.g., wireless or wired connectors and communication hardware, or a combination of wired and wireless hardware) and software components (e.g., drivers, protocol stacks) to enable the device 900 to communicate with external devices. The external devices may be separate devices, such as other computing devices, wireless access points or base stations, and peripheral devices (e.g., headphones, printers) or other devices. In one example, the system 900 exchanges data with external devices to store the data in memory or to display on a display device. The exchanged data may include data to be stored in the memory or data already stored in the memory to read, write or edit the data.

Connectivity 970 may include a variety of different types of connectivity. In general, device 900 is shown with cellular connectivity 972 and wireless connectivity 974. Cellular connectivity 972 generally refers to cellular network connectivity provided by a wireless carrier (e.g., provided via GSM (global system for mobile communications) or variants or derivatives thereof, CDMA (code division multiple access) or variants or derivatives thereof, TDM (time division multiplexing) or variants or derivatives thereof, LTE (long term evolution — also referred to as "4G") or other cellular service standards). Wireless connectivity 974 refers to non-cellular wireless connectivity and may include a personal area network (e.g., bluetooth), a local area network (e.g., WiFi), or a wide area network (e.g., WiMax), or other wireless communications or combinations thereof. Wireless communication refers to the transmission of data through a non-solid medium by using modulated electromagnetic radiation. Wired communications occur over solid-state communications media.

Peripheral connection 980 includes hardware interfaces and connectors and software components (e.g., drivers, protocol stacks) for making peripheral connections. It will be understood that device 900 may be both a peripheral device ("to" 982) to other computing devices, and may have a peripheral device ("from" 984) connected thereto. For purposes such as managing (e.g., downloading, uploading, changing, synchronizing) content on the device 900, the device 900 typically has a "docking" connector to connect to other computing devices. Additionally, a docking connector may allow the device 900 to connect to certain peripheral devices that allow the device 900 to control the output of content to, for example, an audiovisual system or other system.

In addition to proprietary docking connectors or other proprietary connection hardware, the device 900 may also make peripheral connections 980 via common or standards-based connectors. Common types may include Universal Serial Bus (USB) connectors (which may include any of a number of different hardware interfaces), displayports including Micro Displayport (MDP), High Definition Multimedia Interface (HDMI), or other types.

In general, with regard to the description herein, in one example, an apparatus comprises: a Printed Circuit Board (PCB) including components that generate high frequency electromagnetic frequency (EMF) noise during operation, the PCB including pads for engaging with corresponding connectors; and a removable shield for covering the assembly, the shield including a gap in a perimeter of the shield to align with a clip in a corresponding connector to secure the shield with the PCB, and the shield including a locking finger extending from an edge of the shield to engage with the corresponding connector to align the shield with the corresponding connector.

In one example, the shield is adapted to be secured in contact with the PCB via a clip in the corresponding connector. In one example, the PCB includes a plurality of ground pads to contact the removable shield when secured. In one example, the ground pad comprises a flat pad on the PCB to engage with a perforated surface of the shield. In one example, the ground pad includes a protruding pad on the PCB to engage with the flat shield surface. In one example, the ground pad includes a pad to a ground plane of the PCB, wherein the shield is only indirectly connected to the system ground through the ground pad and the corresponding connector. In one example, the shield includes a flange for engaging with the clip to secure to the PCB, wherein the gap in the perimeter includes a gap in the flange to align with the clip of the corresponding connector. In one example, the shield includes sidewalls to completely surround components on the PCB. In one example, the component includes a Dynamic Random Access Memory (DRAM) device. In one example, the PCB comprises a PCB of a dual in-line memory module (DIMM).

In general, with regard to the description herein, in one example, a computing device comprises: a processor; and a memory Printed Circuit Board (PCB) coupled to the processor, the PCB including a memory device that generates high frequency electromagnetic frequency (EMF) noise during operation, the PCB including pads for engaging with corresponding connectors; a removable shield for covering a memory device, the shield including a gap in a perimeter of the shield to align with a clip in a corresponding connector to secure the shield with a PCB, and the shield including a locking finger extending from an edge of the shield to engage with the corresponding connector to align the shield with the corresponding connector.

In one example, the shield is adapted to be secured in contact with the PCB via a clip in the corresponding connector. In one example, the PCB includes a plurality of ground pads to contact the removable shield when secured. In one example, the ground pad comprises a flat pad on the PCB to engage with a perforated surface of the shield. In one example, the ground pad includes a protruding pad on the PCB to engage with the flat shield surface. In one example, the ground pad includes a pad to a ground plane of the PCB, wherein the shield is only indirectly connected to the system ground through the ground pad and the corresponding connector. In one example, the shield includes a flange for engaging with the clip to secure to the PCB, wherein the gap in the perimeter includes a gap in the flange to align with the clip of the corresponding connector. In one example, the shield includes sidewalls to completely surround components on the PCB. In one example, the PCB comprises a dual in-line memory module (DIMM) PCB, wherein the component comprises one of a plurality of Dynamic Random Access Memory (DRAM) devices mounted on the DIMM. In one example, a host processor device includes a multi-core processor. In one example, the system further includes a display communicatively coupled to the host processor. In one example, the system further includes a network interface communicatively coupled to the host processor. In one example, the system further includes a battery for powering the computing device.

The flow diagrams as shown herein provide examples of sequences of various process actions. The flow diagrams may indicate operations to be performed by software or firmware routines and physical operations. The flow diagrams may illustrate examples of implementations of states of a Finite State Machine (FSM) that may be implemented in hardware and/or software. Although shown in a particular sequence or order, the order of the acts may be modified unless otherwise specified. Thus, the illustrated schematic should be understood as an example only, and the process may be performed in a different order, and some actions may be performed in parallel. Additionally, one or more actions may be omitted; thus, not all implementations will perform all actions.

With respect to various operations or functions described herein, the various operations or functions may be described or defined as software code, instructions, configurations, and/or data. The content may be directly executable ("object" or "executable" form), source code, or difference code ("delta" or "patch" code). The software content described herein may be provided via an article of manufacture having the content stored thereon, or via a method of operating a communication interface to transmit data via the communication interface. A machine-readable storage medium may cause a machine to perform the functions or operations described, and includes any mechanism for storing information in a form accessible by a machine (e.g., a computing device, an electronic system, etc.), such as recordable/non-recordable media (e.g., Read Only Memory (ROM), Random Access Memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.). A communication interface includes any mechanism that interfaces with any of a hardwired, wireless, optical, etc. medium to communicate with another device, such as a memory bus interface, a processor bus interface, an internet connection, a disk controller, etc. The communication interface may be configured by providing configuration parameters and/or transmitting signals to prepare the communication interface to provide data signals describing the software content. The communication interface may be accessed via one or more commands or signals sent to the communication interface.

The various components described herein may be means for performing the operations or functions described. Each component described herein includes software, hardware, or a combination of these. A component may be implemented as a software module, a hardware module, special-purpose hardware (e.g., application specific hardware, Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), etc.), embedded controllers, hardwired circuitry, etc.

In addition to those described herein, various modifications may be made to the disclosed and implementations of the invention without departing from their scope. The specification and examples are, accordingly, to be regarded in an illustrative rather than a restrictive sense. The scope of the invention should be measured solely by reference to the claims that follow.