阅读说明：本技术 具有附加发射极/源极路径的并联功率模块 (Parallel power module with additional emitter/source path ) 是由 徐帆 陈礼华 于 2020-03-09 设计创作，主要内容包括：本公开提供了“具有附加发射极/源极路径的并联功率模块”。功率电子电路包括一对并联的开关元件。所述开关元件中的每一者包括两个功率端子、两个控制端子和附加端子。来自所述对中每一者的所述两个功率端子中的对应一个经由相应的第一功率路径和第二功率路径连接。来自所述对中每一者的所述两个控制端子中的对应一个经由相应的第一控制路径和第二控制路径连接。所述附加端子经由附加路径连接。所述电路还包括栅极驱动器和磁体,所述栅极驱动器分接所述第一控制路径和所述第二控制路径,所述磁体围绕所述附加端子以耦合所述附加路径的电感。(The present disclosure provides a "parallel power module with additional emitter/source paths". The power electronic circuit includes a pair of switching elements connected in parallel. Each of the switching elements includes two power terminals, two control terminals, and an additional terminal. A respective one of the two power terminals from each of the pairs is connected via respective first and second power paths. A respective one of the two control terminals from each of the pairs is connected via respective first and second control paths. The additional terminals are connected via additional paths. The circuit also includes a gate driver that taps the first control path and the second control path and a magnet that surrounds the additional terminal to couple an inductance of the additional path.)

1. A power electronic circuit, comprising:

a pair of parallel switching elements each comprising a gate, a Kelvin source, a drain and a source;

a gate path connecting the gate;

a Kelvin path connecting the Kelvin source;

a source path connected to the source;

a gate driver that taps the gate path and the Kelvin path and is configured to drive the gate, wherein the gate driver, the gate path, and the Kelvin path define portions of a gate loop; and

an additional path outside the gate return, the additional path in parallel with the Kelvin path and the source path.

2. The power electronic circuit of claim 1, further comprising a magnet surrounding a terminal of the additional path to couple an inductance of the additional path.

3. The power electronic circuit of claim 1, wherein a bus bar partially defines a portion of the additional path.

4. The power electronic circuit of claim 1, wherein the pair, the gate driver, and the path define portions of a half-bridge cell.

5. The power electronic circuit of claim 4, wherein the source path is a middle terminal of the half-bridge cell.

6. The power electronic circuit of claim 1, wherein each of the switching elements comprises an anti-parallel diode.

7. A power electronic circuit, comprising:

a pair of parallel-connected switching elements each comprising two power terminals, two control terminals, and an additional terminal, a corresponding one of the two power terminals from each of the pair being connected via respective first and second power paths, a corresponding one of the two control terminals from each of the pair being connected via respective first and second control paths, and the additional terminal being connected via an additional path;

a gate driver that taps the first control path and the second control path; and

a magnet surrounding the additional terminal to couple an inductance of the additional path.

8. The power electronic circuit of claim 7, wherein the switching element is a metal oxide semiconductor field effect transistor.

9. The power electronic circuit of claim 7, wherein the switching element is an insulated gate bipolar transistor.

10. The power electronic circuit of claim 7, wherein a bus bar defines a portion of the additional path.

11. The power electronic circuit of claim 7, wherein the additional terminals are bent toward each other.

12. A power electronic circuit, comprising:

a pair of parallel switching elements each including a gate, a Kelvin emitter, a collector, and an emitter;

a gate path connecting the gate;

a Kelvin path connecting the Kelvin emitter;

an emitter path connecting the emitter;

a gate driver, which taps the gate path and the Kelvin path, configured to drive the gate, wherein the gate driver, the gate path, and the Kelvin path define portions of a gate loop; and

an additional path outside the gate return, the additional path in parallel with the Kelvin path and the emitter path.

13. The power electronic circuit of claim 12, further comprising a magnet surrounding a terminal of the additional path to couple an inductance of the additional path.

14. The power electronic circuit of claim 12, wherein a bus bar partially defines the additional path.

15. The power electronic circuit of claim 12, wherein the pair, the gate driver, and the path define portions of a half-bridge cell.

Technical Field

The present disclosure relates to power semiconductor devices.

Background

Power semiconductors are used as switches or rectifiers in certain power electronic devices, such as switched mode power supplies. They are also referred to as power devices, or when used in integrated circuits, as power Integrated Circuits (ICs). Power semiconductors are typically used in commutation mode (which is on or off) and have a design optimized for this purpose. Power semiconductors are used in systems that deliver tens of milliwatts (e.g., headphone amplifiers) and systems that deliver gigawatts (e.g., high voltage direct current (hvdc) power lines).

Some Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are one type of power semiconductor device, a depletion channel device: establishing a conductive path from drain to source may require a voltage rather than a current. At low frequencies, this may reduce the gate current, as it only needs to charge the gate capacitance during switching. The switching time ranges from tens of nanoseconds to hundreds of microseconds. In general, MOSFET devices are not bi-directional and are not reverse voltage blocking.

Insulated Gate Bipolar Transistors (IGBTs), another type of power semiconductor, typically have characteristics common to Bipolar Junction Transistors (BJTs) and MOSFETs. It may have a high gate impedance and therefore a low gate current requirement, like a MOSFET. It may have a low on-state voltage drop in the operating mode, like a BJT. Some IGBTs can be used to block both positive and negative voltages and have reduced input capacitance compared to MOSFET devices.

Disclosure of Invention

The power electronic circuit includes a pair of parallel-connected switching elements each including a gate, a kelvin source, a drain, and a source. The circuit also includes a gate path connecting the gate, a kelvin path connecting the kelvin source, a source path connecting the source, and a gate driver that taps the gate path and the kelvin path and is configured to drive the gate. The gate driver, gate path, and kelvin path define portions of a gate loop. The circuit still further includes an additional path outside the gate return in parallel with the kelvin path and the source path.

The power electronic circuit comprises a pair of parallel-connected switching elements each comprising two power terminals, two control terminals, and an additional terminal. A respective one of the two power terminals from each of the pairs is connected via respective first and second power paths. A respective one of the two control terminals from each of the pairs is connected via respective first and second control paths. The additional terminals are connected via additional paths. The circuit also includes a gate driver that taps the first control path and the second control path and a magnet that surrounds the additional terminal to couple an inductance of the additional path.

The power electronic circuit comprises a pair of parallel-connected switching elements, each of which comprises a gate, a Kelvin emitter, a collector and an emitter; the circuit also includes a gate path connecting the gate, a kelvin path connecting the kelvin source, an emitter path connecting the emitter, and a gate driver that taps the gate path and the kelvin path and is configured to drive the gate. The gate driver, gate path, and kelvin path define portions of a gate loop. The circuit still further includes an additional path outside the gate return in parallel with the kelvin path and the source path.

Drawings

FIG. 1 is a schematic diagram of a half-bridge circuit.

Fig. 2A and 2B are front and side views (cross-sections) of a half-bridge power module.

Fig. 3 is a schematic diagram of a parallel half-bridge power module and the resulting gate loop oscillation.

Fig. 4 is a graph of gate voltages associated with the parallel half-bridge power module of fig. 3.

Fig. 5 is a schematic diagram of a power module package for parallel semiconductors.

Fig. 6 is a schematic diagram of a parallel half-bridge power module with additional emitter/source side paths.

Fig. 7A and 7B are front and side views, respectively, of a half-bridge power module with extended emitter/source leadframe terminals and additional emitter/source paths.

Fig. 8 is a schematic diagram of a parallel half-bridge power module with coupled stray inductance on the additional emitter/source side path.

Fig. 9A and 9B are front and top views, respectively, of a parallel half-bridge power module with coupled stray inductance on the additional emitter/source side path realized by an extended leadframe.

Fig. 10A and 10B are front and side views, respectively, of a parallel half-bridge power module with stray inductance coupling on the additional emitter/source side path enabled by a pin and wire bond (wire bond).

Fig. 11 is an elevation view of a parallel half-bridge power module with stray inductance coupling on the additional emitter/source side path enabled by pins and bonding wires.

Detailed Description

Various embodiments of the present disclosure are described herein. However, the disclosed embodiments are merely exemplary, and other embodiments may take various and alternative forms not explicitly shown or described. The figures are not necessarily to scale; some features may be exaggerated or minimized to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present invention. As one of ordinary skill in the art will appreciate, various features illustrated and described with reference to any one of the figures may be combined with features illustrated in one or more other figures to produce embodiments that are not explicitly illustrated or described. The combination of features shown provides a representative embodiment of a typical application. However, various combinations and modifications of the features consistent with the teachings of the present disclosure may be desired for particular applications or implementations.

Referring to fig. 1, a half-bridge cell 10 (which is the main unit of a power electronic circuit/converter circuit) includes an upper switching element 12 and a lower switching element 14. Each of the switching elements 12, 14 includes an active power device 16, 18 (e.g., a power silicon/silicon carbide MOSFET or a silicon IGBT) with or without an anti-parallel diode 20, 22. Each of the switching elements 12, 14 also has two power terminals: drain for MOSFET configuration (D)_n) And source electrode (S)_n) (or collector (C) for IGBT configuration_n) And an emitter (E)_n) ); and two control terminals: gate (G) for MOSFET configuration_n) And Kelvin source (K)_n) (or kelvin emitter for IGBT configurations). Here, n is "1" when referring to the switching element 12, and is "2" when referring to the switching element 14. Grid G_nAnd Kelvin source/emitter K_nThe terminals constitute a gate circuit to control the switching on and off of the active semiconductor. The positive DC terminal P and the negative DC terminal N of the half-bridge unit are connected to the drain terminal D of the switching element 12, respectively₁And a source terminal S of the switching element 14₂. The intermediate terminal of the half-bridge unit 10, which is also the source terminal S of the switching element 12, is connected to an output load (e.g. an electric motor winding U/V/W)₁And a drain terminal D of the switching element 14₂。

Traction inverters in electric/hybrid electric vehicles typically include one or several three-phase converters. In some topologies, a boost DC-DC converter is also present. For high power traction inverter applications, several half-bridge units need to be used in parallel to achieve high output power. Power modules package half-bridge units known for their flexibility in various applications, different inverter topologies and power ratings. Thus, several half-bridge power modules may be necessary in a traction inverter, depending on the inverter topology and power rating.

Referring to fig. 2A and 2B, the half-bridge unit 10 is shown in the context of a power module 24, in which the switching elements 12, 14 are soldered (or sintered) to copper lead frames on both the top and bottom sides. Drain terminal D_nSource terminal S_nThe external power terminal P, N and the neutral phase output are part of the lead frame. The signal pins 26 are connected to the active power devices 12, 14 (or directly soldered/sintered to the semiconductor) by wire bonds 28. Signal pin 26 includes a gate G for_nAnd Kelvin emitter/source K_nAnd some sensor signal outputs (if there are on-chip sensors). The copper pad 30 and the epoxy resin 32 connect the drain terminal D_nAnd a source terminal S_nAnd (4) separating. The power module 24 may be cooled from one or both sides.

Fig. 3 shows a circuit 34 of parallel power switching elements 36, 38, 40, 42, each having two power terminals, i.e. drains D_x-yAnd source S_x-yAnd two control terminals, i.e. gates G_x-yAnd Kelvin source KS_x-y. Here, x is "1" when referring to the switching elements 36, 38, and "2" when referring to the switching elements 40, 42, and y is "1" when referring to the switching elements 36, 40, and "2" when referring to the switching elements 38, 42. (in the context of IGBT technology, the power terminals will instead act as collector and emitter, while the control terminals will include a kelvin emitter instead of a kelvin source). Corresponding gate G_x-yAnd Kelvin source KS_x-yCorresponding gate loops are formed to control the power switching elements 36, 38, 40, 42. The circuit 34 also includes a gate driver integrated circuit 44 common to the switching elements 36, 38 and a gate driver integrated circuit 46 common to the switching elements 40, 42. Gate path 48 is electrically connected to gate G_1-1、G_1-2 The Kelvin path 50 electrically connects Kelvin sources KS_1-1、KS_1-2And source path 52 electrically connects source S_1-1、S_1-2. Resistance R_G1-1、R_G1-2In gate path 48. Similarly, gate path 54 is electrically connected to gate G_2-1、G_2-2Kelvin path 56 electrically connects Kelvin sources KS_2-1、KS_2-2And source path 58 electrically connects source S_2-1、S_2-2. Resistance R_G2-1、R_G2-2In the gate path 54. Also shown are various inductances L_Kx-y、L_Sx-y. These are not actual elements, but rather represent some of the inductance present in circuit 34.

When half-bridge power modules are used in parallel for high power applications, the switching on/off transient currents of the parallel power semiconductors are often unbalanced due to inter-piece variations in power semiconductor parameters, uneven bus bar layout, and/or unbalanced semiconductor junction capacitance and circuit stray inductance. The unbalanced current results in a voltage potential difference, i.e., V, at the emitter/source sides of the parallel semiconductors_K1-1-V_K1-2≠0，V_S1-1-V_S1-2Not equal to 0 (which should always be zero in the ideal case). Voltage difference (V)_K1-1-V_K1-2) With K_1-1And K_1-2(L_K1-1、L_K1-2) And S_1-1And S_1-2(L_S1-1、L_S1-2) The semiconductor junction capacitance and circuit stray inductance between them induce oscillations in the gate loops of the parallel semiconductors. The oscillation is uncontrollable and may result in a gate voltage (V) across the semiconductor_G1-1、K_1-1And V_G1-2、K_1-2) Oscillating at high peak voltage values.

Referring to fig. 4, a simulation shows an oscillating gate voltage waveform. The peak value of the gate voltage is close to 50V, which is much higher than the gate driver output of 20V. Parallel silicon carbide MOSFETs switch much faster than silicon alone and are prone to gate voltage oscillations unless the switching speed is reduced. However, reduced switching speed results in higher switching losses.

Referring again to FIG. 3, stray inductance (L) connecting the emitter/source sides of the semiconductor is reduced_K1-1、L_K1-2And/or L_S1-1、L_S1-2) The voltage potential difference of the parallel power modules will be reduced or eliminated and the gate voltage oscillation will be effectively suppressed. Stray inductance L_K1-1、L_K1-2Mainly from the signal pins of the power module, the bond wires and the circuit traces on the gate drive printed circuit board. Inductor L_S1-1、L_S1-2Mainly from the terminals connecting the parallel power modules and the external bus bars. To achieve the reductionL_K1-1、L_K1-2And/or L_S1-1、L_S1-2The prior art approach is to package the parallel semiconductors 60, 62 in a power module 64, as shown in fig. 5. This approach eliminates the external bus bars connecting the parallel semiconductors 60, 62 and effectively reduces L_S1-1、L_S1-2(FIG. 3). With respect to the half-bridge power module 24 in fig. 2A and 2B, this type of power module is not based on basic circuit cells, i.e., half-bridge cells, and is therefore not suitable for different applications. For example, in fig. 5, the parallel semiconductors 60, 62 may need to be designed differently. For traction inverters of different power ratings, the power module 64 may need to be redesigned to package a different number of semiconductors. In addition, the design and assembly process of the bus bar may be complicated.

To avoid gate voltage oscillations by reducing the emitter/source side stray inductance between the parallel power semiconductors, we propose to add additional paths 66, 68 to the circuit 34 of fig. 3 on the emitter/source of each of the power semiconductors 36, 38 and 40, 42, as shown in fig. 6. The additional path 66 directly connects K_1-1/S_1-1Side and K_1-2/S_1-2And (4) side connection. Likewise, the additional path 68 directly couples K to_2-1/S_2-1Side and K_2-2/S_2-2And (4) side connection. The additional paths 66, 68 are external to the gate return and may be designed to be physically short and have small stray inductances.

Fig. 7A shows an example design implementing the proposed additional paths in the context of the power module described in fig. 2A and 2B. The added emitter/source side path proposed in fig. 6 is achieved by extending the semiconductor emitter/source copper lead frames 70, 72. Fig. 7B shows the power module 24 of fig. 7A with a corresponding power module 74 (similar in design to the power module 24 of fig. 7A) attached. The extended semiconductor emitter/source copper lead frame 70 and the corresponding extended back semiconductor emitter/source lead frame 76 of the power module 74 are connected via a minimum length of bus bar 78 to reduce stray inductance. With small stray inductance, associated Kelvin sources and sources (e.g.See K of FIG. 6_1-1And K_1-2And S_1-1And S_1-2) The voltage potential difference between them will remain small even during fast transient switching. Therefore, gate loop oscillation and gate degradation can be avoided when the power semiconductors are operated in parallel. At the same time, the half-bridge power module structure can be used for flexible and convenient design/assembly for different vehicle applications. Cooling channels 80 are also shown adjacent the power modules 24, 74.

To further reduce stray inductance in the added emitter/ source paths 66, 68, another design is proposed that couples stray inductance in the added emitter/ source paths 66, 68 as shown in fig. 8. By the coupling, the equivalent impedance between the power semiconductors can be reduced. If Kelvin emitter/source path inductance (e.g., L)_K1-1And L_K1-2) Coupled, the impedance of each semiconductor gate loop will increase, which increases switching time and losses. If phase output path inductance (e.g., L)_S1-1And L_S1-2) Coupled, the output power current will saturate the coupling magnet. Coupling stray inductance L in the additional path_CM1-1And L_CM1-2The gate loop or power output will not be affected. By mixing L_CM1-1And L_CM1-2Coupling into a Common Mode (CM) structure may also reduce or eliminate K_1-1And K_1-2(and S_1-1And S_1-2) The voltage potential difference between (which is the differential mode voltage).

Referring to fig. 9A and 9B, the extended emitter/source lead frame terminals 70, 76 (similar to the signal pins 26) may be soldered to a gate drive Printed Circuit Board (PCB)82 to achieve the stray inductance L_CM1-1、L_CM1-2(and L_CM2-1、L_CM2-2) Is coupled. The extended emitter/ source leadframe terminals 70, 76 may be connected through PCB traces and then emitter/source paths formed. Most of the stray inductance (L) in this added path_CM1-1、L_CM1-2) On the extended terminals. The inductance on the PCB traces and internal lead frame is typically negligible. Applying magnet 84 to the added emitter/source terminals 70, 76To implement the CM architecture. The power module 74 also includes an extended emitter/source leadframe terminal 86. Thus, a magnet 88 is applied over the added emitter/source terminals 72, 86.

The proposed additional emitter/source paths can also be realized by wire bonds and signal pins. Fig. 10A illustrates such an example in the context of the power module depicted in fig. 2A and 2B. Signal pins 90, 92 are added and connected to the power semiconductor emitter/source sides of the switching elements 12, 14, respectively. These additional pins are also connected by PCB traces.

To further improve the coupling effect and reduce the equivalent inductance in the added path, a third alternative is shown in fig. 11. The additional emitter/source leadframe terminals (fig. 9A-9B) or leads (fig. 10A-10B) are bent and are close to each other.

Therefore, we propose an additional emitter/source for the parallel half-bridge power module. Possible advantages of some of the designs contemplated herein are as follows. When the power semiconductors are operated in parallel at fast switching speeds, gate loop oscillations can be avoided. The half-bridge power module architecture is not significantly changed and the power module can still flexibly accommodate different traction inverter topologies and power ratings in the vehicle. Only minor changes in power module design are required and short bus bars or magnets can be added. The additional costs should be minimized. Some of the proposed designs may be implemented during assembly of the power module and traction inverter. The normal functions of the traction inverter, such as the inverter phase output and the power semiconductor gate driver, will not be affected. The proposed arrangement is applicable to different types of half-bridge power modules (single-or double-sided cooled power modules, power modules using wire bonds or lead frames as chip top surface connections, etc.).

The words used in the specification are words of description rather than limitation, and it is understood that various changes may be made without departing from the spirit and scope of the disclosure and claims. As previously mentioned, features of the various embodiments may be combined to form further embodiments that may not be explicitly described or illustrated. Although various embodiments may have been described as providing advantages over or being preferred over other embodiments or prior art implementations in terms of one or more desired characteristics, one of ordinary skill in the art will recognize that one or more features or characteristics may be compromised to achieve desired overall system attributes, which depend on the particular application and implementation. These attributes include, but are not limited to, cost, strength, durability, life cycle cost, marketability, appearance, packaging, size, serviceability, weight, manufacturability, ease of assembly, and the like. Accordingly, embodiments described as being less desirable with respect to one or more characteristics than other embodiments or prior art implementations are outside the scope of the present disclosure and may be desirable for particular applications.

According to the present invention, there is provided a power electronic circuit having a pair of parallel-connected switching elements each comprising a gate, a kelvin source, a drain and a source; a gate path connecting the gate; a Kelvin path connecting the Kelvin sources; a source path connecting the source; a gate driver that taps the gate path and the Kelvin path and is configured to drive the gate, wherein the gate driver, the gate path and the Kelvin path define portions of a gate loop; and an additional path outside the gate return, in parallel with the kelvin path and the source path.

The invention also features, according to one embodiment, a magnet surrounding a terminal of the additional path to couple an inductance of the additional path.

According to one embodiment, the bus bar partially defines a portion of the additional path.

According to one embodiment, the pair, gate driver and path define portions of a half-bridge cell.

According to one embodiment, the source path is a middle terminal of the half-bridge cell.

According to one embodiment, the invention also features a U/V/W phase that taps the source path.

According to one embodiment, the invention also features a DC terminal that taps the source path.

According to one embodiment, each of the switching elements comprises an anti-parallel diode.

According to the present invention, there is provided a power electronic circuit having a pair of parallel switching elements each comprising two power terminals, two control terminals and an additional terminal, a respective one of the two power terminals from each of the pair being connected via respective first and second power paths, a respective one of the two control terminals from each of the pair being connected via respective first and second control paths; and an additional terminal connected via an additional path; a gate driver that taps the first control path and the second control path; and a magnet surrounding the additional terminal to couple the inductance of the additional path.

According to one embodiment, the switching element is a metal oxide semiconductor field effect transistor.

According to one embodiment, the switching element is an insulated gate bipolar transistor.

According to one embodiment, the bus bar defines a portion of the additional path.

According to one embodiment, the additional terminals are bent towards each other.

According to the present invention, there is provided a power electronic circuit having a pair of parallel-connected switching elements each comprising a gate, a kelvin emitter, a collector and an emitter; a gate path connecting the gate; a Kelvin path connecting the Kelvin emitters; an emitter path connecting the emitter; a gate driver that taps the gate path and the Kelvin path and is configured to drive the gate, wherein the gate driver, the gate path, and the Kelvin path define portions of a gate loop; and an additional path outside the gate return, in parallel with the kelvin path and the emitter path.

According to one embodiment, the invention also features a magnet surrounding the terminal of the additional path to couple the inductance of the additional path.

According to one embodiment, the bus bar partially defines the additional path.

According to one embodiment, the pair, gate driver and path define portions of a half-bridge cell.

According to one embodiment, the emitter path is a middle terminal of the half-bridge cell.

According to one embodiment, the invention also features a U/V/W phase of the tapped emitter path.

According to one embodiment, the invention also features a DC terminal that taps the emitter path.