阅读说明：本技术 双交流端口的单相半桥式多电平逆变器及构造、调试方法 (Single-phase half-bridge type multi-level inverter with double alternating current ports and construction and debugging method ) 是由 朱淼 陈阳 王晗 徐莉婷 蔡旭 于 2020-07-10 设计创作，主要内容包括：本发明提供了一种双交流端口的单相半桥式多电平逆变器及构造、调试方法,包括：半桥子模块串、全桥子模块串、桥臂电抗器以及电容；所述半桥子模块串采用半桥子模块串联组合；所述全桥子模块串采用全桥子模块串联组合；所述半桥子模块串包括：第一半桥子模块串、第二半桥子模块串；所述第一半桥子模块串、全桥子模块串、第二半桥子模块串依次分别通过2只串联桥臂电抗器连接构成第一桥臂；两只电容串联构成第二桥臂。本发明所提出的逆变器的同一桥臂两不同端口可以与电容桥臂组合,输出两路不同的交流电,能够显著改善装置输出能力,有效提升装置能量密度,降低规划部署成本。(The invention provides a single-phase half-bridge type multilevel inverter with double alternating current ports and a construction and debugging method, wherein the construction and debugging method comprises the following steps: the half-bridge sub-module string, the full-bridge sub-module string, the bridge arm reactor and the capacitor are connected in series; the half-bridge sub-module string adopts a series combination of half-bridge sub-modules; the full-bridge sub-module string adopts a series combination of full-bridge sub-modules; the half-bridge sub-module string comprises: the first half-bridge submodule string and the second half-bridge submodule string; the first half-bridge submodule string, the full-bridge submodule string and the second half-bridge submodule string are sequentially and respectively connected through 2 series bridge arm reactors to form a first bridge arm; two capacitors are connected in series to form a second bridge arm. Two different ports of the same bridge arm of the inverter can be combined with a capacitor bridge arm to output two paths of different alternating currents, so that the output capacity of the inverter can be obviously improved, the energy density of the inverter can be effectively improved, and the planning and deployment cost can be reduced.)

1. A single-phase half-bridge multi-level inverter with dual ac ports, comprising: the half-bridge sub-module string, the full-bridge sub-module string, the bridge arm reactor and the capacitor are connected in series;

the half-bridge sub-module string adopts a series combination of half-bridge sub-modules;

the full-bridge sub-module string adopts a series combination of full-bridge sub-modules;

the half-bridge sub-module string comprises: the first half-bridge submodule string and the second half-bridge submodule string;

the first half-bridge submodule string, the full-bridge submodule string and the second half-bridge submodule string are sequentially connected through 2 series bridge arm reactors respectively.

2. A method for constructing a single-phase half-bridge multi-level inverter with two ac ports, which is characterized by using the single-phase half-bridge multi-level inverter with two ac ports of claim 1, and comprises:

step S1: from a direct current P pole to a direct current N pole, a modular multilevel bridge arm main body is divided into 3 parts, wherein the bridge arm comprises a 1 st part, a 2 nd part and a 3 rd part from top to bottom, wherein the 1 st part is a series-combined half-bridge sub-module string, the 2 nd part is a series-combined full-bridge sub-module string, and the 3 rd part is a series-combined half-bridge sub-module string;

step S2: connecting 3 parts of the modular multilevel bridge arm main body through 2 bridge arm reactors respectively to form a bridge arm;

a first alternating current terminal and a second alternating current terminal are respectively led out between 2 adjacent bridge arm reactors of the connecting sub-module;

step S3: two capacitors connected in series are adopted, and two ends of the two capacitors connected in series are respectively connected with a direct current P pole and an N pole to form the other bridge arm of the single-phase inverter;

step S4: and a connection point between the capacitors is led out to serve as a third alternating current terminal, and the first alternating current terminal and the third alternating current terminal as well as the second alternating current terminal and the third alternating current terminal respectively form a pair of alternating current output ports.

3. A method for debugging a single-phase half-bridge multi-level inverter with dual ac ports, which is characterized by using the single-phase half-bridge multi-level inverter with dual ac ports of claim 1, and comprises:

step P1: calculating the switching period T of the system work according to the given working frequency f;

step P2: when the period starts, the voltage command values v of the AO and UO ports are obtained_AO ^*、v_UO ^*(ii) a Measuring the capacitance voltage of each submodule in each area; calculating the mean value of the capacitor voltage of each sub-module in each area, and respectively recording the mean value as V_CX、V_CY、V_CZ(ii) a Measuring the corresponding current, respectively denoted as i_X、i_Y、i_Z；

The inverter is provided with two alternating current output ports which are respectively marked as AO and UO;

step P3: calculating the initial value N of the number of the submodules needing to be input in the X area_X0 ^*；

Step P4: calculating the initial value N of the number of submodules needing to be input in the Z area_Z0 ^*；

Step P5: correcting initial value N of number of submodules needing to be input in X area_X0 ^*(ii) a Obtaining the number N of modules actually required to be input in the X area_X ^*。

4. The method for debugging the double-AC-port single-phase half-bridge multi-level inverter according to claim 3, further comprising:

step P6: correcting number initial value N of submodules needing to be input in Z area_Z0 ^*(ii) a Obtaining the number N of modules actually required to be input in the Z area_Z ^*。

5. The method for debugging the double-AC-port single-phase half-bridge multi-level inverter according to claim 4, further comprising:

step P7: calculating the initial value N of the number of submodules needing to be input in the Y area_Y0 ^*；

Step P8: correcting number initial value N of submodules needing to be input in Y area_Y0 ^*Obtaining the number N of modules actually required to be input in the Y area_Y ^*。

6. The method for debugging the dual ac port single-phase half-bridge multi-level inverter of claim 5, wherein the step P5 comprises:

step P5.1: judging whether the voltage fluctuation of the capacitor of the sub-module in the X area exceeds a preset fluctuation limit value or not; if Δ V_CXIf the limit value is not exceeded, the step P5.2 is carried out; otherwise go to step P5.3;

step P5.2: setting the number N of modules which need to be put into practice_X ^*＝N_X0 ^*(ii) a Go to step P5.10;

step P5.3: Δ V_CX>When 0, go to step P5.4; otherwise go to step P5.7;

step P5.4: i.e. i_X>When 0, go to step P5.5; otherwise go to step P5.6;

step P5.5: correcting the number of modules N actually required to be input_X ^*＝N_X0 ^*-1; go to step P5.10;

step P5.6: correcting the number of modules N actually required to be input_X ^*＝N_X0 ^*+ 1; go to step P5.10;

step P5.7: i.e. i_X>When 0, go to step P5.5; otherwise go to step P5.6;

step P5.8: correcting the number of modules N actually required to be input_X ^*＝N_X0 ^*+ 1; go to step P5.10;

step P5.9: correcting the number of modules N actually required to be input_X ^*＝N_X0 ^*-1; go to step P5.10;

step P5.10: go to step P6.

7. The method for debugging the dual ac port single-phase half-bridge multi-level inverter of claim 5, wherein the step P6 comprises:

step P6.1: judging Z area submodule capacitor voltage fluctuation delta V_CZWhether the fluctuation exceeds a preset fluctuation limit value; if the limit value is not exceeded, go to step P6.2; otherwise go to step P6.3;

step P6.2: setting the number N of modules which need to be put into practice_Z ^*＝N_Z0 ^*(ii) a Go to step P6.10;

step P6.3: Δ V_CZ>When 0, go to step P6.4; otherwise go to step P6.7;

step P6.4: i.e. i_Z>When 0, go to step P6.5; otherwise go to step P6.6;

step P6.5: correcting the number of modules N actually required to be input_Z ^*＝N_Z0 ^*-1; go to step P6.10;

step P6.6: correcting the number of modules N actually required to be input_Z ^*＝N_Z0 ^*+ 1; go to step P6.10;

step P6.7: i.e. i_Z>When 0, go to step P6.5; otherwise go to step P6.6;

step P6.8: correcting the number of modules N actually required to be input_Z ^*＝N_Z0 ^*+ 1; go to step P6.10;

step P6.9: correcting the number of modules N actually required to be input_Z ^*＝N_Z0 ^*-1; go to step P6.10;

step P6.10: go to step P7.

8. The method for debugging the double-AC-port single-phase half-bridge multi-level inverter according to claim 7, further comprising:

step P9: x, Y, Z, sequencing the capacitor voltage of each sub-module in each area from high to low;

step P10: i.e. i_X>When 0, go to step P12; otherwise go to step P11;

step P11: selecting N with highest submodule voltage in X region_X ^*The sub-module sets the working state of the sub-module in the switching period as input; the remaining submodules are set to be cut off; go to step P13;

step P12: selecting N with lowest submodule voltage in X region_X ^*The sub-module sets the working state of the sub-module in the switching period as input; the remaining submodules are set to be cut off; go to step P13;

step P13: i.e. i_Z>When 0, go to step P15; otherwise go to step P14;

step P14: selecting N with highest voltage of submodules in Z region_Z ^*The sub-module sets the working state of the sub-module in the switching period as input; the remaining submodules are set to be cut off; go to step P16;

step P15: selecting N with lowest submodule voltage in Z region_Z ^*The sub-module sets the working state of the sub-module in the switching period as input; the remaining submodules are set to be cut off; go to step P16;

step P16: n is a radical of_Y ^*>When 0, go to step P17; otherwise go to step P20;

step P17: i.e. i_Y>When 0, go to step P19; otherwise go to step P18;

step P18: selecting N with highest voltage of submodules in Y region_Y ^*The sub-module sets the working state of the sub-module in the switching period as positive input; the remaining submodules are set to be cut off; go to step P23;

step P19: selecting N with lowest submodule voltage in Y area_Y ^*The sub-module sets the working state of the sub-module in the switching period as positive input; the remaining submodules are set to be cut off; go to step P23;

step P20: i.e. i_Y>When 0, go to step P22; otherwise go to step P21;

step P21: selecting-N with lowest submodule voltage in Y region_Y ^*The sub-module sets the working state of the sub-module in the switching period as negative input; the remaining submodules are set to be cut off; go to step P23;

step P22: selecting-N with highest submodule voltage in Y region_Y ^*The sub-module sets the working state of the sub-module in the switching period as negative input; the remaining submodules are set to be cut off; go to step P23;

step P23: the setting of the working state of the submodule is finished, and the process jumps to the step P2 after the period is finished.

9. The method for debugging the dual ac port single-phase half-bridge multi-level inverter of claim 8, wherein the step P8 comprises:

step P8.1: judging the capacitor voltage fluctuation delta V of the sub-module in the Y area_CYWhether the fluctuation exceeds a preset fluctuation limit value; if the limit value is not exceeded, go to step P8.2; otherwise go to step P8.3;

step P8.2: setting the number N of modules which need to be put into practice_Y ^*＝N_Y0 ^*(ii) a Go to step P9;

step P8.3: n is a radical of_Y0 ^*>When 0, go to step P8.4; otherwise go to step P8.11;

step P8.4: Δ V_CY>When 0, go to step P8.5; otherwise go to step P8.8;

step P8.5: i.e. i_Y>When 0, go to step P8.6; otherwise go to step P8.7;

step P8.6: correcting the number of modules N actually required to be input_Y ^*＝N_Y0 ^*-1; go to step P9;

step P8.7: correcting the number of modules N actually required to be input_Y ^*＝N_Y0 ^*+ 1; go to step P9;

step P8.8: i.e. i_Y>When 0, go to step P8.9; otherwise go to step P8.10;

step P8.9: correcting the number of modules N actually required to be input_Y ^*＝N_Y0 ^*+ 1; go to step P9;

step P8.10: correcting the number of modules N actually required to be input_Y ^*＝N_Y0 ^*-1; go to step P9.

10. The method for debugging a dual ac port single-phase half-bridge multi-level inverter according to claim 9, wherein the step P8 further comprises:

step P8.11: Δ V_CY>When 0, go to step P8.4; otherwise go to step P8.7;

step P8.12: i.e. i_Y>When 0, go to step P8.13; otherwise go to step P8.14;

step P8.13: correcting the number of modules N actually required to be input_Y ^*＝N_Y0 ^*+ 1; go to step P9;

step P8.14: correcting the number of modules N actually required to be input_Y ^*＝N_Y0 ^*-1; go to step P9;

step P8.15: i.e. i_Y>When 0, go to step P8.16; otherwise go to step P8.17;

step P8.16: correcting the number of modules N actually required to be input_Y ^*＝N_Y0 ^*-1; go to step P9;

step P8.17: correcting the number of modules N actually required to be input_Y ^*＝N_Y0 ^*+ 1; go to step P9.

Technical Field

The invention relates to the technical field of multi-level inverters, in particular to a single-phase half-bridge type multi-level inverter with double alternating current ports and a construction and debugging method.

Background

The rapid development of power electronic technology and the wide application of power electronic equipment obviously improve the controllable degree and the intelligent level of a power grid and promote the change of the form of the power grid. A large number of high voltage dc transmission lines and equipment are present in the ac power grid. The direct current load and the direct current distribution system are also important components in the future power system. In the future, the situation of multi-voltage-level alternating current and direct current hybrid connection of an electric power system will appear. As a core device for DC-AC power conversion, the steady-state and dynamic performances of the inverter directly influence the safe and stable operation of the power grid side and the reliable power supply of the user side. Inverters of different voltage classes will typically adopt different topologies. Single-phase inverters and three-phase inverters of the same voltage class may also differ in specific topology. The single-phase inverter of low voltage class usually adopts two-level structure, and its basic topology is divided into half-bridge and full-bridge, as shown in fig. 1 and 2. The half-bridge type two-level inverter adopts two fully-controlled devices to form a half-bridge circuit, and forms an alternating current side output port together with two capacitors. The full-bridge two-level inverter adopts four full-control devices to form a full-bridge circuit, and an alternating current side output port is formed. A single-phase inverter of a low voltage class generally operates by a Pulse Width Modulation (PWM) method, and an ac output waveform thereof is a voltage pulse of ± U at a high frequency, and therefore, there are a large number of harmonics, and it is necessary to perform filtering by an L-type or LCL-type filter. In higher voltage class applications such as motor drives, three-level, five-level, etc. inverter topologies are typically used. Fig. 3 and 4 show typical diode-clamped three-level single-phase inverter topologies. Multilevel circuits also typically operate using PWM modulation. The inverter of the multilevel circuit such as three-level circuit and the like has the advantages that the quality of the output waveform is obviously improved along with the increase of the number of levels, and the volume of a required filter is obviously reduced. Due to the limited capabilities of power electronic switching devices, two-level circuits are difficult to apply directly to higher voltage class applications. And the topology of the multi-level circuit matched with the high-voltage grade becomes too complex, so that the difficulty of a modulation strategy is greatly improved, and the overall reliability is reduced. Therefore, in higher voltage class situations, a modular multilevel circuit is usually used to meet the application scenario requirements of higher voltage class and capacity. Among them, the most common is a modular multilevel inverter using half-bridge sub-modules, the basic topology of which is shown in fig. 5 and 6. As the number of sub-modules increases, modular multilevel circuits typically employ a nearest level approximation (NLM) modulation method. The single-phase bridge arm of the modular multilevel circuit generally needs to be composed of an upper bridge arm and a lower bridge arm which have the same structure, so that the device volume of the modular multilevel circuit has a space for further reduction. In addition, the traditional nearest level approximation modulation strategy requires that the total number of input sub-modules of an upper bridge arm and a lower bridge arm is kept constant in the modulation process, and the modulation strategy has a further improved space. Under the condition that urban land resources are increasingly scarce, how to further improve the energy density of the device, reduce the size of the inverter and simplify the modulation strategy of the inverter on the basis of ensuring the reliable operation of the system becomes an important direction for the development of the inverter in the future.

Patent document "topological structure of single-phase cascaded seven-level inverter and control method thereof" discloses a single-phase cascaded seven-level inverter topology and a control method thereof. The inverter is composed of a three-level Boost circuit and a six-switch inverter circuit, the midpoint potential is adjusted by using the three-level Boost circuit, so that the voltage ratio of the middle bus capacitor is 1: 2, and a potential condition is provided for realizing seven-level output. Compared with the traditional multi-level topology, the topology uses fewer switching devices, and the circuit structure is simplified. Because the voltage control effect of the intermediate bus capacitor is the key of reliable operation of the system, a mathematical model of the direct-current side voltage control system is established on the basis of discussing the operation mechanism of the circuit topology, and a voltage control method is provided according to the mathematical model, so that the effective operation of the inverter control system is realized. Finally, the feasibility of the proposed circuit topology and the correctness of theoretical analysis are verified by means of system simulation and experiments. The document adopts a seven-level topological structure, and compared with a two-level circuit, the withstand voltage level of the seven-level topological structure is improved to a certain extent. The circuit still cannot operate at too high voltage levels and its modulation strategy is complex.

Disclosure of Invention

Aiming at the defects in the prior art, the invention aims to provide a single-phase half-bridge type multi-level inverter with double alternating current ports and a construction and debugging method.

The invention provides a single-phase half-bridge type multilevel inverter with double alternating current ports, which comprises: the half-bridge sub-module string, the full-bridge sub-module string, the bridge arm reactor and the capacitor are connected in series; the half-bridge sub-module string adopts a series combination of half-bridge sub-modules; the full-bridge sub-module string adopts a series combination of full-bridge sub-modules; the half-bridge sub-module string comprises: the first half-bridge submodule string and the second half-bridge submodule string; the first half-bridge submodule string, the full-bridge submodule string and the second half-bridge submodule string are sequentially and respectively connected through 2 series bridge arm reactors to form a first bridge arm; two capacitors are connected in series to form a second bridge arm.

According to the construction method of the single-phase half-bridge multi-level inverter with the double alternating current ports, the single-phase half-bridge multi-level inverter with the double alternating current ports is adopted, and the construction method comprises the following steps: step S1: 3 parts of the main body of the modular multilevel bridge arm are arranged from a direct current P pole to a direct current N pole, the bridge arm is from top to bottom, the 1 st part is a series-combined half-bridge sub-module string, the 2 nd part is a series-combined full-bridge sub-module string, and the 3 rd part is a series-combined half-bridge sub-module string; step S2: 3 parts of the modular multilevel bridge arm main body are respectively connected through 2 bridge arm reactors; a first alternating current terminal and a second alternating current terminal are respectively led out between 2 adjacent bridge arm reactors of the connecting sub-module; two ac terminals, upper and lower, can be led out. Step S3: two capacitors connected in series are adopted, and two ends of the two capacitors connected in series are respectively connected with a direct current P pole and an N pole to form the other bridge arm of the single-phase inverter; step S4: and a connection point between the capacitors is led out to serve as a third alternating current terminal, and the first alternating current terminal and the third alternating current terminal as well as the second alternating current terminal and the third alternating current terminal respectively form a pair of alternating current output ports. The inverter has two ac output ports, denoted AO and UO, respectively.

The three sub-module groups are respectively recorded as X, Y, Z from top to bottom. Each submodule group comprises N submodules. The half-bridge sub-modules have inputs andthe cut-off state is two states, and the full-bridge submodule has three states of positive input, cut-off state and negative input. Let the capacitor voltage be V_CIf the voltage that the submodule group X can output is 0, V_C、2V_C、…、NV_CThe voltage that the submodule group Y can output is 0 +/-V_C、±2V_C、…、±NV_CThe voltage that the submodule group Z can output is 0 and V_C、2V_C、…、NV_C。

The number of the submodules put into by the three submodules is recorded as N_x、N_yAnd N_z. The AO and UO port voltages are

Through a reasonable modulation method, the stable and basically consistent voltage of the capacitor of each submodule can be maintained. By periodically varying N_xAnd N_zThe value of (d) can be such that both output ports of the inverter can output a specified ac voltage waveform.

According to the debugging method of the single-phase half-bridge multi-level inverter with the double alternating current ports, which is provided by the invention, the single-phase half-bridge multi-level inverter with the double alternating current ports is adopted, and the debugging method comprises the following steps:

step P1: calculating the switching period T of the system work according to the given working frequency f;

step P2: when the period starts, the voltage command values v of the AO and UO ports are obtained_AO ^*、v_UO ^*(ii) a Measuring the capacitance voltage of each submodule in each area; calculating the mean value of the capacitor voltage of each sub-module in each area, and respectively recording the mean value as V_CX、V_CY、V_CZ(ii) a Measuring the corresponding current, respectively denoted as i_X、i_Y、i_Z；

Wherein the inverter has two AC output ports, denoted as AO and UO respectively

Step P3: meterCalculating the initial value N of the number of submodules required to be input in the X area_X0 ^*(ii) a The calculation method is shown as the following formula; wherein round () represents a rounding function;

step P4: calculating the initial value N of the number of submodules needing to be input in the Z area_Z0 ^*(ii) a The calculation method is shown as the following formula; wherein round () represents a rounding function;

step P5: correcting initial value N of number of submodules needing to be input in X area_X0 ^*(ii) a Obtaining the number N of modules actually required to be input in the X area_X ^*. The correction flow is shown in fig. 10.

Preferably, the method further comprises the following steps: step P6: correcting number initial value N of submodules needing to be input in Z area_Z0 ^*(ii) a Obtaining the number N of modules actually required to be input in the Z area_Z ^*. The correction flow is shown in fig. 11.

Preferably, the step P5 includes:

step P5.1: judging whether the voltage fluctuation of the capacitor of the sub-module in the X area exceeds a preset fluctuation limit value or not; if Δ V_CXIf the limit value is not exceeded, the step P5.2 is carried out; otherwise go to step P5.3;

step P5.2: setting the number N of modules which need to be put into practice_X ^*＝N_X0 ^*(ii) a Go to step P5.10;

step P5.3: Δ V_CX>When 0, go to step P5.4; otherwise go to step P5.7;

step P5.4: i.e. i_X>When 0, go to step P5.5; otherwise go to step P5.6;

step P5.5: correcting the number of modules N actually required to be input_X ^*＝N_X0 ^*-1; go to step P5.10;

step P5.6: correcting the number of modules N actually required to be input_X ^*＝N_X0 ^*+ 1; go to step P5.10;

step P5.7: i.e. i_X>When 0, go to step P5.5; otherwise go to step P5.6;

step P5.8: correcting the number of modules N actually required to be input_X ^*＝N_X0 ^*+ 1; go to step P5.10;

step P5.9: correcting the number of modules N actually required to be input_X ^*＝N_X0 ^*-1; go to step P5.10;

step P5.10: go to step P6.

Preferably, the step P6 includes:

step P6.1: judging Z area submodule capacitor voltage fluctuation delta V_CZWhether the fluctuation exceeds a preset fluctuation limit value; if the limit value is not exceeded, go to step P6.2; otherwise go to step P6.3;

step P6.2: setting the number N of modules which need to be put into practice_Z ^*＝N_Z0 ^*(ii) a Go to step P6.10;

step P6.3: Δ V_CZ>When 0, go to step P6.4; otherwise go to step P6.7;

step P6.4: i.e. i_Z>When 0, go to step P6.5; otherwise go to step P6.6;

step P6.5: correcting the number of modules N actually required to be input_Z ^*＝N_Z0 ^*-1; go to step P6.10;

step P6.6: correcting the number of modules N actually required to be input_Z ^*＝N_Z0 ^*+ 1; go to step P6.10;

step P6.7: i.e. i_Z>When 0, go to step P6.5; otherwise go to step P6.6;

step P6.8: correcting the number of modules N actually required to be input_Z ^*＝N_Z0 ^*+ 1; go to step P6.10;

step P6.9: correcting the number of modules N actually required to be input_Z ^*＝N_Z0 ^*-1; go to step P6.10;

step P6.10: go to step P7;

preferably, the method further comprises the following steps:

step P7: calculating the initial value N of the number of submodules needing to be input in the Y area_Y0 ^*；

Step P8: correcting number initial value N of submodules needing to be input in Y area_Y0 ^*Obtaining the number N of modules actually required to be input in the Y area_Y ^*. The correction flow is shown in fig. 12;

preferably, the method further comprises the following steps:

step P9: x, Y, Z, sequencing the capacitor voltage of each sub-module in each area from high to low;

step P10: i.e. i_X>When 0, go to step P12; otherwise go to step P11;

step P11: selecting N with highest submodule voltage in X region_X ^*The sub-module sets the working state of the sub-module in the switching period as input; the remaining submodules are set to be cut off; go to step P13;

step P12: selecting N with lowest submodule voltage in X region_X ^*The sub-module sets the working state of the sub-module in the switching period as input; the remaining submodules are set to be cut off; go to step P13;

step P13: i.e. i_Z>When 0, go to step P15; otherwise go to step P14;

step P14: selecting N with highest voltage of submodules in Z region_Z ^*The sub-module sets the working state of the sub-module in the switching period as input; the remaining submodules are set to be cut off; go to step P16;

step P15: selecting N with lowest submodule voltage in Z region_Z ^*The sub-module sets the working state of the sub-module in the switching period as input; the remaining submodules are set to be cut off; go toStep P16;

step P16: n is a radical of_Y ^*>When 0, go to step P17; otherwise go to step P20;

step P17: i.e. i_Y>When 0, go to step P19; otherwise go to step P18;

step P18: selecting N with highest voltage of submodules in Y region_Y ^*The sub-module sets the working state of the sub-module in the switching period as positive input; the remaining submodules are set to be cut off; go to step P23;

step P19: selecting N with lowest submodule voltage in Y area_Y ^*The sub-module sets the working state of the sub-module in the switching period as positive input; the remaining submodules are set to be cut off; go to step P23;

step P20: i.e. i_Y>When 0, go to step P22; otherwise go to step P21;

step P21: selecting-N with lowest submodule voltage in Y region_Y ^*The sub-module sets the working state of the sub-module in the switching period as negative input; the remaining submodules are set to be cut off; go to step P23;

step P22: selecting-N with highest submodule voltage in Y region_Y ^*The sub-module sets the working state of the sub-module in the switching period as negative input; the remaining submodules are set to be cut off; go to step P23;

step P23: the setting of the working state of the submodule is finished, and the process jumps to the step P2 after the period is finished.

Preferably, the step P8 includes:

step P8.1: judging the capacitor voltage fluctuation delta V of the sub-module in the Y area_CYWhether the fluctuation exceeds a preset fluctuation limit value; if the limit value is not exceeded, go to step P8.2; otherwise go to step P8.3;

step P8.2: setting the number N of modules which need to be put into practice_Y ^*＝N_Y0 ^*(ii) a Go to step P9;

step P8.3: n is a radical of_Y0 ^*>When 0, go to step P8.4; otherwise go to step P8.11;

step P8.4: Δ V_CY>When 0, go to step P8.5; otherwise go to step P8.8;

step P8.5: i.e. i_Y>When 0, go to step P8.6; otherwise go to step P8.7;

step P8.6: correcting the number of modules N actually required to be input_Y ^*＝N_Y0 ^*-1; go to step P9;

step P8.7: correcting the number of modules N actually required to be input_Y ^*＝N_Y0 ^*+ 1; go to step P9;

step P8.8: i.e. i_Y>When 0, go to step P8.9; otherwise go to step P8.10;

step P8.9: correcting the number of modules N actually required to be input_Y ^*＝N_Y0 ^*+ 1; go to step P9;

step P8.10: correcting the number of modules N actually required to be input_Y ^*＝N_Y0 ^*-1; go to step P9;

preferably, the step P8 further includes:

step P8.11: Δ V_CY>When 0, go to step P8.4; otherwise go to step P8.7;

step P8.12: i.e. i_Y>When 0, go to step P8.13; otherwise go to step P8.14;

step P8.13: correcting the number of modules N actually required to be input_Y ^*＝N_Y0 ^*+ 1; go to step P9;

step P8.14: correcting the number of modules N actually required to be input_Y ^*＝N_Y0 ^*-1; go to step P9;

step P8.15: i.e. i_Y>When 0, go to step P8.16; otherwise go to step P8.17;

step P8.16: correcting the number of modules N actually required to be input_Y ^*＝N_Y0 ^*-1; go to step P9;

step P8.17: correcting the number of modules N actually required to be input_Y ^*＝N_Y0 ^*+1；Go to step P9.

Compared with the prior art, the invention has the following beneficial effects:

1. the invention provides a single-phase half-bridge type modular multilevel inverter with double alternating current ports, and provides a corresponding modulation method aiming at the topology of the inverter, the structure is reasonable, the use is convenient, and the defects of the prior art are overcome;

2. the topology adopts a half-bridge and full-bridge sub-module mixed combination mode, compared with a single alternating current output terminal of a bridge arm of a traditional modularized multi-level inverter, the same modularized multi-level bridge arm of the proposed topology is provided with 2 alternating current output terminals which are respectively connected with a common midpoint to form 2 alternating current output ports;

3. the invention provides a corresponding nearest level approximation modulation strategy aiming at the novel inverter topology, can realize accurate output of double alternating current ports and maintain efficient work of the system;

4. the same bridge arm of the inverter provided by the invention can output two paths of different alternating currents, so that the output capacity of the device can be obviously improved, the energy density of the device is effectively improved, and the planning and deployment cost is reduced.

5. The novel nearest level approximation modulation method provided by the invention is simple and easy to implement, can accurately output following instruction values, and maintains effective work of the system.

Drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:

fig. 1 is a schematic diagram of a two-level half-bridge inverter topology.

Fig. 2 is a schematic diagram of a two-level full-bridge inverter topology.

Fig. 3 is a schematic diagram of a three-level half-bridge inverter topology.

Fig. 4 is a schematic diagram of a three-level full-bridge inverter topology.

Fig. 5 is a schematic diagram of a half-bridge single-phase inverter topology based on half-bridge sub-modules.

Fig. 6 is a schematic diagram of a half-bridge sub-module-based MMC full-bridge single-phase inverter topology.

Fig. 7 is a schematic diagram of a half-bridge modular multilevel single-phase inverter topology according to the present invention.

Fig. 8 is a schematic diagram of various physical quantities involved in the half-bridge modular multilevel single-phase inverter according to the present invention.

Fig. 9 is a schematic diagram of a modulation flow of a half-bridge modular multilevel single-phase inverter according to an embodiment of the present invention.

Fig. 10 is a schematic diagram of a method for correcting the input number of the X-region sub-module in the embodiment of the present invention.

Fig. 11 is a schematic diagram of a method for correcting the input number of the sub-module in the Z region according to an embodiment of the present invention.

Fig. 12 is a schematic diagram of a method for correcting the input number of the Y-region sub-module in the embodiment of the present invention.

Fig. 13 is a schematic diagram of an application example of the present invention in the embodiment of the present invention.

FIG. 14 is a schematic diagram showing an AC side voltage output waveform of an example of application of the present invention.

FIG. 15 is a schematic diagram showing an AC side voltage output waveform of an example of application of the present invention.

Detailed Description

The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.

The invention provides a single-phase half-bridge type multilevel inverter with double alternating current ports, which comprises: the half-bridge sub-module string, the full-bridge sub-module string, the bridge arm reactor and the capacitor are connected in series; the half-bridge sub-module string adopts a series combination of half-bridge sub-modules; the full-bridge sub-module string adopts a series combination of full-bridge sub-modules; the half-bridge sub-module string comprises: the first half-bridge submodule string and the second half-bridge submodule string; the first half-bridge submodule string, the full-bridge submodule string and the second half-bridge submodule string are sequentially and respectively connected through 2 series bridge arm reactors to form a first bridge arm; two capacitors are connected in series to form a second bridge arm.

According to the construction method of the single-phase half-bridge multi-level inverter with the double alternating current ports, the single-phase half-bridge multi-level inverter with the double alternating current ports is adopted, and the construction method comprises the following steps: step S1: from a direct current P pole to a direct current N pole, a modular multilevel bridge arm main body is divided into 3 parts, wherein the bridge arm comprises a 1 st part, a 2 nd part and a 3 rd part from top to bottom, wherein the 1 st part is a half-bridge sub-module, the 2 nd part is a full-bridge sub-module and the 3 rd part is a half-bridge sub-module which are combined in series; step S2: 3 parts of the modular multilevel bridge arm main body are respectively connected through 2 bridge arm reactors; a first alternating current terminal and a second alternating current terminal are respectively led out between 2 adjacent bridge arm reactors of the connecting sub-module; two ac terminals, upper and lower, can be led out. Step S3: two capacitors connected in series are adopted, and two ends of the two capacitors connected in series are respectively connected with a direct current P pole and an N pole to form the other bridge arm of the single-phase inverter; step S4: and a connection point between the capacitors is led out to serve as a third alternating current terminal, and the first alternating current terminal and the third alternating current terminal as well as the second alternating current terminal and the third alternating current terminal respectively form a pair of alternating current output ports. The inverter has two ac output ports, denoted AO and UO, respectively. The three sub-module groups are respectively recorded as X, Y, Z from top to bottom. Each submodule group comprises N submodules. The half-bridge sub-module has two states of input and cut-off, and the full-bridge sub-module has three states of positive input, cut-off and negative input. Let the capacitor voltage be V_CIf the voltage that the submodule group X can output is 0, V_C、2V_C、…、NV_CThe voltage that the submodule group Y can output is 0 +/-V_C、±2V_C、…、±NV_CThe voltage that the submodule group Z can output is 0 and V_C、2V_C、…、NV_C。

The number of the submodules put into by the three submodules is recorded as N_x、N_yAnd N_z. The AO and UO port voltages are

Through a reasonable modulation method, the stable and basically consistent voltage of the capacitor of each submodule can be maintained. By periodically varying N_xAnd N_zThe value of (d) can be such that both output ports of the inverter can output a specified ac voltage waveform.

According to the debugging method of the single-phase half-bridge multi-level inverter with the double alternating current ports, which is provided by the invention, the single-phase half-bridge multi-level inverter with the double alternating current ports is adopted, and the debugging method comprises the following steps:

step P1: calculating the switching period T of the system work according to the given working frequency f;

step P2: when the period starts, the voltage command values v of the AO and UO ports are obtained_AO ^*、v_UO ^*(ii) a Measuring the capacitance voltage of each submodule in each area; calculating the mean value of the capacitor voltage of each sub-module in each area, and respectively recording the mean value as V_CX、V_CY、V_CZ(ii) a Measuring the corresponding current, respectively denoted as i_X、i_Y、i_Z；

Wherein the inverter has two AC output ports, denoted as AO and UO respectively

Step P3: calculating the initial value N of the number of the submodules needing to be input in the X area_X0 ^*(ii) a The calculation method is shown as the following formula; wherein round () represents a rounding function;

step P4: calculating the initial value N of the number of submodules needing to be input in the Z area_Z0 ^*(ii) a The calculation method is shown as the following formula; wherein round () represents a rounding function;

step P5: correcting initial value N of number of submodules needing to be input in X area_X0 ^*(ii) a Obtaining the number N of modules actually required to be input in the X area_X ^*. The correction flow is shown in fig. 10.

Preferably, the method further comprises the following steps: step P6: correcting number initial value N of submodules needing to be input in Z area_Z0 ^*(ii) a Obtaining the number N of modules actually required to be input in the Z area_Z ^*. The correction flow is shown in fig. 11.

Preferably, the step P5 includes:

step P5.1: judging whether the voltage fluctuation of the capacitor of the sub-module in the X area exceeds a preset fluctuation limit value or not; if Δ V_CXIf the limit value is not exceeded, the step P5.2 is carried out; otherwise go to step P5.3;

step P5.2: setting the number N of modules which need to be put into practice_X ^*＝N_X0 ^*(ii) a Go to step P5.10;

step P5.3: Δ V_CX>When 0, go to step P5.4; otherwise go to step P5.7;

step P5.4: i.e. i_X>When 0, go to step P5.5; otherwise go to step P5.6;

step P5.5: correcting the number of modules N actually required to be input_X ^*＝N_X0 ^*-1; go to step P5.10;

step P5.6: correcting the number of modules N actually required to be input_X ^*＝N_X0 ^*+ 1; go to step P5.10;

step P5.7: i.e. i_X>When 0, go to step P5.5; otherwise go to step P5.6;

step P5.8: correcting the number of modules N actually required to be input_X ^*＝N_X0 ^*+ 1; go to step P5.10;

step P5.9: correcting the number of modules N actually required to be input_X ^*＝N_X0 ^*-1; go to step P5.10;

step P5.10: go to step P6.

Preferably, the step P6 includes:

step P6.1: judging Z area submodule capacitor voltage fluctuation delta V_CZWhether the fluctuation exceeds a preset fluctuation limit value; if the limit value is not exceeded, go to step P6.2; otherwise go to step P6.3;

step P6.2: setting the number N of modules which need to be put into practice_Z ^*＝N_Z0 ^*(ii) a Go to step P6.10;

step P6.3: Δ V_CZ>When 0, go to step P6.4; otherwise go to step P6.7;

step P6.4: i.e. i_Z>When 0, go to step P6.5; otherwise go to step P6.6;

step P6.5: correcting the number of modules N actually required to be input_Z ^*＝N_Z0 ^*-1; go to step P6.10;

step P6.6: correcting the number of modules N actually required to be input_Z ^*＝N_Z0 ^*+ 1; go to step P6.10;

step P6.7: i.e. i_Z>When 0, go to step P6.5; otherwise go to step P6.6;

step P6.8: correcting the number of modules N actually required to be input_Z ^*＝N_Z0 ^*+ 1; go to step P6.10;

step P6.9: correcting the number of modules N actually required to be input_Z ^*＝N_Z0 ^*-1; go to step P6.10;

step P6.10: go to step P7;

preferably, the method further comprises the following steps:

step P7: calculating the initial value N of the number of submodules needing to be input in the Y area_Y0 ^*；

Step P8: correcting number initial value N of submodules needing to be input in Y area_Y0 ^*Obtaining the number N of modules actually required to be input in the Y area_Y ^*. The correction flow is shown in fig. 12;

preferably, the method further comprises the following steps:

step P9: x, Y, Z, sequencing the capacitor voltage of each sub-module in each area from high to low;

step P10: i.e. i_X>When 0, go to step P12; otherwise go to step P11;

step P11: selecting N with highest submodule voltage in X region_X ^*The sub-module sets the working state of the sub-module in the switching period as input; the remaining submodules are set to be cut off; go to step P13;

step P12: selecting N with lowest submodule voltage in X region_X ^*The sub-module sets the working state of the sub-module in the switching period as input; the remaining submodules are set to be cut off; go to step P13;

step P13: i.e. i_Z>When 0, go to step P15; otherwise go to step P14;

step P14: selecting N with highest voltage of submodules in Z region_Z ^*The sub-module sets the working state of the sub-module in the switching period as input; the remaining submodules are set to be cut off; go to step P16;

step P15: selecting N with lowest submodule voltage in Z region_Z ^*The sub-module sets the working state of the sub-module in the switching period as input; the remaining submodules are set to be cut off; go to step P16;

step P16: n is a radical of_Y ^*>When 0, go to step P17; otherwise go to step P20;

step P17: i.e. i_Y>When 0, go to step P19; otherwise go to step P18;

step P18: selecting N with highest voltage of submodules in Y region_Y ^*The sub-module sets the working state of the sub-module in the switching period as positive input; the remaining submodules are set to be cut off; go to step P23;

step P19: selecting N with lowest submodule voltage in Y area_Y ^*The sub-module sets the working state of the sub-module in the switching period as positive input; the remaining submodules are set to be cut off; go to step P23;

step P20: i.e. i_Y>When 0, go to step P22; otherwise go to step P21;

step P21: selecting-N with lowest submodule voltage in Y region_Y ^*The sub-module sets the working state of the sub-module in the switching period as negative input; the remaining submodules are set to be cut off; go to step P23;

step P22: selecting-N with highest submodule voltage in Y region_Y ^*The sub-module sets the working state of the sub-module in the switching period as negative input; the remaining submodules are set to be cut off; go to step P23;

step P23: the setting of the working state of the submodule is finished, and the process jumps to the step P2 after the period is finished.

Preferably, the step P8 includes:

step P8.1: judging the capacitor voltage fluctuation delta V of the sub-module in the Y area_CYWhether the fluctuation exceeds a preset fluctuation limit value; if the limit value is not exceeded, go to step P8.2; otherwise go to step P8.3;

step P8.2: correcting the number of modules N actually required to be input_Y ^*＝N_Y0 ^*(ii) a Go to step P9;

step P8.3: n is a radical of_Y0 ^*>When 0, go to step P8.4; otherwise go to step P8.11;

step P8.4: Δ V_CY>When 0, go to step P8.5; otherwise go to step P8.8;

step P8.5: i.e. i_Y>When 0, go to step P8.6; otherwise go to step P8.7;

step P8.6: correcting the number of modules N actually required to be input_Y ^*＝N_Y0 ^*-1; go to step P9;

step P8.7: correcting the number of modules N actually required to be input_Y ^*＝N_Y0 ^*+ 1; go to step P9;

step P8.8: i.e. i_Y>When 0, go to step P8.9; otherwise go to step P8.10;

step P8.9: correcting the number of modules N actually required to be input_Y ^*＝N_Y0 ^*+ 1; go to step P9;

step P8.10: correcting the number of modules N actually required to be input_Y ^*＝N_Y0 ^*-1; go to step P9;

preferably, the step P8 further includes:

step P8.11: Δ V_CY>When 0, go to step P8.4; otherwise go to step P8.7;

step P8.12: i.e. i_Y>When 0, go to step P8.13; otherwise go to step P8.14;

step P8.13: correcting the number of modules N actually required to be input_Y ^*＝N_Y0 ^*+ 1; go to step P9;

step P8.14: correcting the number of modules N actually required to be input_Y ^*＝N_Y0 ^*-1; go to step P9;

step P8.15: i.e. i_Y>When 0, go to step P8.16; otherwise go to step P8.17;

step P8.16: correcting the number of modules N actually required to be input_Y ^*＝N_Y0 ^*-1; go to step P9;

step P8.17: correcting the number of modules N actually required to be input_Y ^*＝N_Y0 ^*+ 1; go to step P9.

Specifically, in one embodiment, the single-phase half-bridge modular multilevel inverter proposed by this patent is constructed, as shown in fig. 13. The double AC output ports are AO and UO. The direct current side power supply voltage is 400kV, the load 1 is 1000 omega and 20 mH; the load 2 is 500 Ω, 20 mH. Wherein, X, Y, Z parts of the modular multilevel bridge arm of the inverter each contain 20 sub-modules, i.e. N-20. And the two capacitors of the other bridge arm are both 2 mF.

The voltage command value of the two alternating current output ports is 200sin (100 pi t) kV. The ac side output voltage is shown in fig. 14. The ac side current is as shown in fig. 15. As can be seen from fig. 14, the output voltage waveforms of the two ac ports AO and UO are substantially coincident and are sinusoidal step waves which change according to the reference voltage law. It can be seen from fig. 15 that the AO port current amplitude is half of the UO port current. The simulation output result is consistent with the theoretical result.

The invention provides a single-phase half-bridge type modular multilevel inverter with double alternating current ports, and provides a corresponding modulation method aiming at the topology of the inverter, the structure is reasonable, the use is convenient, and the defects of the prior art are overcome; the topology adopts a half-bridge and full-bridge sub-module mixed combination mode, compared with a single alternating current output terminal of a bridge arm of a traditional modularized multi-level inverter, the same modularized multi-level bridge arm of the proposed topology is provided with 2 alternating current output terminals which are respectively connected with a common midpoint to form 2 alternating current output ports; the invention provides a corresponding nearest level approximation modulation strategy aiming at the novel inverter topology, can realize accurate output of double alternating current ports and maintain efficient work of the system.

In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application.

The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.