阅读说明：本技术 真空沟道场效应晶体管及其制造方法以及半导体装置 (Vacuum channel field effect transistor, method of manufacturing the same, and semiconductor device ) 是由 安藤善文 于 2021-07-09 设计创作，主要内容包括：本发明提供一种能够增大源漏间电流的真空沟道场效应晶体管及其制造方法以及半导体装置。真空沟道场效应晶体管(100)具有：设置在p型半导体基板(1)上的第一绝缘膜(2)、设置在第一绝缘膜(2)上的栅极(3)、设置在栅极(3)上的第二绝缘膜(4)、设置在第二绝缘膜(4)上的漏极(7)、以及在p型半导体基板(1)的表面上与包括第一绝缘膜(2)、栅极(3)和第二绝缘膜(4)的侧面的侧壁相接而设置的n+杂质扩散层(6)。通过对n+杂质扩散层(6)、栅极(3)和漏极(7)施加规定的电压,从而使得n+杂质扩散层(6)的电荷载流子在面向侧壁的真空中或空气中向漏极(7)移动,由此能够使源漏间的电流增大。(The invention provides a vacuum channel field effect transistor capable of increasing current between a source and a drain, a manufacturing method thereof and a semiconductor device. A vacuum channel field effect transistor (100) comprises: the semiconductor device includes a first insulating film (2) provided on a p-type semiconductor substrate (1), a gate electrode (3) provided on the first insulating film (2), a second insulating film (4) provided on the gate electrode (3), a drain electrode (7) provided on the second insulating film (4), and an n + impurity diffusion layer (6) provided on the surface of the p-type semiconductor substrate (1) in contact with a sidewall including side surfaces of the first insulating film (2), the gate electrode (3), and the second insulating film (4). By applying a predetermined voltage to the n + impurity diffusion layer (6), the gate (3), and the drain (7), charge carriers in the n + impurity diffusion layer (6) are moved to the drain (7) in vacuum or air facing the side wall, thereby increasing the current between the source and drain.)

1. A vacuum channel field effect transistor, comprising:

a semiconductor substrate;

a first insulating film provided on the semiconductor substrate;

a gate electrode disposed on the first insulating film;

a second insulating film disposed on the gate electrode;

a drain electrode provided on the second insulating film; and

an impurity diffusion layer provided on a surface of the semiconductor substrate in contact with a sidewall including side surfaces of the first insulating film, the gate electrode, and the second insulating film,

by applying a predetermined voltage to the impurity diffusion layer, the gate electrode, and the drain electrode, charge carriers of the impurity diffusion layer are moved to the drain electrode in a vacuum or air facing the side wall.

2. The vacuum channel field effect transistor of claim 1, wherein:

the impurity diffusion layer is an n-type impurity diffusion layer, and the charge carriers are electrons.

3. The vacuum channel field effect transistor of claim 2, wherein:

by applying a predetermined negative voltage or GND voltage to the n-type impurity diffusion layer, a predetermined positive voltage is applied to the gate and the drain, so that the electrons of the n-type impurity diffusion layer move toward the drain in the vacuum or air facing the sidewall.

4. The vacuum channel field effect transistor of claim 1, wherein:

the impurity diffusion layer is a p-type impurity diffusion layer, and the charge carriers are holes.

5. The vacuum channel field effect transistor of claim 4, wherein:

by applying a predetermined positive voltage or GND voltage to the p-type impurity diffusion layer and applying a predetermined negative voltage to the gate and the drain, the holes of the p-type impurity diffusion layer are moved toward the drain in the vacuum or air to which the side wall faces.

6. The vacuum channel field effect transistor of any of claims 1-5, wherein:

the impurity diffusion layer is in contact with a bottom portion of the first insulating film.

7. The vacuum channel field effect transistor of any of claims 1-6, wherein:

the charge carriers include charge carriers of an inversion layer formed on a surface of the semiconductor substrate in contact with the first insulating film, and the inversion layer is connected to the impurity diffusion layer.

8. The vacuum channel field effect transistor of any of claims 1-7, wherein:

the side wall at least comprises more than two.

9. The vacuum channel field effect transistor of any of claims 1-8, wherein:

at least the side face of the gate electrode included in the side wall is covered with an insulating film.

10. The vacuum channel field effect transistor of any of claims 1-9, wherein:

the drain electrode extends to a side closer to the impurity diffusion layer than the side wall.

11. The vacuum channel field effect transistor of any of claims 1-10, wherein:

the drain electrode covers an upper entirety of a space of vacuum or air facing the sidewall.

12. The vacuum channel field effect transistor of any of claims 1-11, wherein:

the first insulating film has a thickness thinner than that of the second insulating film.

13. The vacuum channel field effect transistor of any of claims 1-12, wherein:

the second insulating film is provided between a surface of the semiconductor substrate and a bottom surface of the drain electrode, and the second insulating film is provided adjacent to a side wall including a side surface of the gate electrode and the first insulating film on a side not in contact with the impurity diffusion layer.

14. The vacuum channel field effect transistor of any of claims 1-13, wherein:

the first insulating film and the second insulating film include a silicon oxide film or a silicon nitride film.

15. The vacuum channel field effect transistor of any of claims 1-14, wherein:

the vacuum channel field effect transistor further includes an insulating film for blocking a space in a side surface direction and an upper surface direction of the vacuum channel field effect transistor from outside air.

16. A semiconductor device, characterized in that the semiconductor device has a plurality of field effect transistors, the field effect transistors comprising:

a semiconductor substrate;

a first insulating film provided on the semiconductor substrate;

a gate electrode disposed on the first insulating film;

a second insulating film disposed on the gate electrode;

a drain electrode provided on the second insulating film; and

an impurity diffusion layer provided on a surface of the semiconductor substrate in contact with a sidewall including side surfaces of the first insulating film, the gate electrode, and the second insulating film,

by applying a predetermined voltage to the impurity diffusion layer, the gate electrode, and the drain electrode, charge carriers of the impurity diffusion layer move toward the drain electrode in a vacuum or air facing the side wall,

the plurality of field effect transistors include an n-type field effect transistor and a p-type field effect transistor, the impurity diffusion layer of the n-type field effect transistor is an n-type impurity diffusion layer and the charge carriers are electrons, the impurity diffusion layer of the p-type field effect transistor is a p-type impurity diffusion layer and the charge carriers are holes.

17. The semiconductor device according to claim 16, wherein:

the semiconductor device is a complementary inverter circuit, the gate of the n-type field effect transistor is connected with the gate of the p-type field effect transistor, the drain of the n-type field effect transistor is connected with the drain of the p-type field effect transistor, the n-type impurity diffusion layer is a source of the n-type field effect transistor, and the p-type impurity diffusion layer is a source of the p-type field effect transistor.

18. The semiconductor device according to claim 16 or 17, wherein:

the semiconductor substrate is an SOI substrate.

19. A vacuum channel field effect transistor, comprising:

a semiconductor substrate;

a source electrode provided in a plate shape on the semiconductor substrate in a direction perpendicular to a surface of the semiconductor substrate;

a drain electrode provided in a plate shape in a direction perpendicular to a surface of the semiconductor substrate and facing the source electrode with a vacuum or air interposed therebetween; and

a gate electrode disposed in a plate shape in a direction perpendicular to a surface of the semiconductor substrate and facing the vacuum or air between the source electrode and the drain electrode,

by applying a predetermined voltage to the source, the gate, and the drain, charge carriers of the source move to the drain in the vacuum or in air.

20. The vacuum channel field effect transistor of claim 19 wherein:

an n-type impurity diffusion layer is provided on a surface of the source, and electrons in the n-type impurity diffusion layer are moved to the drain in the vacuum or in the air by applying a predetermined negative voltage or a GND voltage to the n-type impurity diffusion layer and applying a predetermined positive voltage to the gate and the drain.

21. The vacuum channel field effect transistor of claim 19 wherein:

the source electrode has a p-type impurity diffusion layer on a surface thereof, and holes in the p-type impurity diffusion layer are moved to the drain electrode in the vacuum or air by applying a predetermined positive voltage or a GND voltage to the p-type impurity diffusion layer and applying a predetermined negative voltage to the gate electrode and the drain electrode.

22. A method of fabricating a vacuum channel field effect transistor, comprising:

forming a first insulating film on a semiconductor substrate;

forming a gate electrode on the first insulating film;

forming a second insulating film on the gate electrode;

forming a sidewall including side surfaces of the first insulating film, the gate electrode, and the second insulating film;

forming an impurity diffusion layer on a surface of the semiconductor substrate in contact with the side wall; and

and forming a drain electrode on the second insulating film.

23. The method of manufacturing a vacuum channel field effect transistor according to claim 22, wherein:

the impurity diffusion layer is an n-type impurity diffusion layer.

24. The method of manufacturing a vacuum channel field effect transistor according to claim 22, wherein:

the impurity diffusion layer is a p-type impurity diffusion layer.

25. The manufacturing method of a vacuum channel field effect transistor according to any one of claims 22 to 24, characterized in that:

the method further includes, after the step of forming the side wall, a step of forming an insulating film at least on the side surface included in the side wall of the gate electrode.

Technical Field

The invention relates to a vacuum channel field effect transistor, a method of manufacturing the same, and a semiconductor device.

Background

As a Field Effect Transistor (hereinafter, may be referred to as FET) suitable for high-speed operation, a vacuum channel FET using vacuum as a medium of charge carriers is known (for example, see non-patent documents 1 and 2).

Non-patent document 1 discloses a vacuum channel FET having a source, a silicon oxide film formed in this order on the source, a gate, a silicon oxide film, and a drain, and discharging charge carriers into a vacuum from a sidewall of the source. In the case of an n-type FET, the source is formed of a p-type silicon substrate, and electrons in the 2DES (two-dimensional electron system) and inversion layer induced in the vicinity of the interface between the source and the silicon oxide film on the source are released from the sidewall of the source to vacuum by the gate voltage and the source-drain voltage, and reach the drain, thereby flowing a current between the source and the drain.

Non-patent document 2 discloses a vacuum channel FET including an anode, a silicon oxide film formed on the anode in this order, a gate, a silicon oxide film, and a cathode, and releasing electrons from a sidewall of the cathode to a vacuum. The electrons are released from the side wall of the cathode into a vacuum by FN tunneling due to the gate voltage and the cathode-anode voltage.

Documents of the prior art

Non-patent document

Non-patent document 1: siwapon Srisonphan, Yun Suk Jung, and Hong Koo Kim, "Metal-oxide-semiconductor field-effect transistor with a vacuum channel," NATURE NAOTECHNOLOGY, VOL7, AUGUST2012

Non-patent document 2: fatemeh Kohani Khoshkbijari, and Mohammad Javad Sharifi, "Reducing the gate current in vacuum channel field-emission transistors using a gate," Journal of Computational Electronics (2020)19:263-

Disclosure of Invention

Problems to be solved by the invention

In the vacuum channel FET, it is desirable to increase the source-drain current during the on operation. However, in the vacuum channel FETs as in non-patent documents 1 and 2, when electrons are released from the source or the cathode into the vacuum, the vacuum channel FETs are configured to release electrons only from the side wall portion of the source or the cathode, and thus there is a problem that it is difficult to increase the current between the source and the drain.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a vacuum channel field effect transistor capable of increasing a source-drain current, a method for manufacturing the same, and a semiconductor device.

Means for solving the problems

The vacuum channel field effect transistor of the present invention is characterized by comprising: a semiconductor substrate; a first insulating film provided on the semiconductor substrate; a gate electrode disposed on the first insulating film; a second insulating film provided on the gate electrode; a drain electrode provided on the second insulating film; and an impurity diffusion layer provided on a surface of the semiconductor substrate in contact with a sidewall including a side surface of the first insulating film, the gate electrode, and the second insulating film, wherein a predetermined voltage is applied to the impurity diffusion layer, the gate electrode, and the drain electrode, whereby charge carriers of the impurity diffusion layer move to the drain electrode in a vacuum or in air facing the sidewall.

In addition, the vacuum channel field effect transistor of the present invention includes: a semiconductor substrate; a source electrode provided on the semiconductor substrate in a plate shape in a direction perpendicular to a surface of the semiconductor substrate; a drain electrode provided in a plate shape in a direction perpendicular to a surface of the semiconductor substrate and opposed to the source electrode with a vacuum or air interposed therebetween; and a gate electrode provided in a plate shape in a direction perpendicular to a surface of the semiconductor substrate and facing the vacuum or the air between the source electrode and the drain electrode, wherein a predetermined voltage is applied to the source electrode, the gate electrode, and the drain electrode, whereby charge carriers of the source electrode move to the drain electrode in the vacuum or the air.

The method for manufacturing a vacuum channel field effect transistor of the present invention includes: forming a first insulating film on a semiconductor substrate; forming a gate electrode on the first insulating film; forming a second insulating film on the gate electrode; forming a sidewall including side surfaces of the first insulating film, the gate electrode, and the second insulating film; forming an impurity diffusion layer on a surface of the semiconductor substrate in contact with the side wall; and forming a drain electrode on the second insulating film.

The semiconductor device of the present invention is characterized in that: having a plurality of field effect transistors, said field effect transistors comprising: a semiconductor substrate; a first insulating film provided on the semiconductor substrate; a gate electrode disposed on the first insulating film; a second insulating film provided on the gate electrode; a drain electrode provided on the second insulating film; and an impurity diffusion layer provided on a surface of the semiconductor substrate in contact with a side wall including side surfaces of the first insulating film, the gate electrode, and the second insulating film, wherein a predetermined voltage is applied to the impurity diffusion layer, the gate electrode, and the drain electrode, whereby charge carriers of the impurity diffusion layer move to the drain electrode in a vacuum or in air facing the side wall, the plurality of field effect transistors include an n-type field effect transistor and a p-type field effect transistor, the impurity diffusion layer of the n-type field effect transistor is an n-type impurity diffusion layer and the charge carriers are electrons, the impurity diffusion layer of the p-type field effect transistor is a p-type impurity diffusion layer and the charge carriers are holes.

Effects of the invention

According to the present invention, it is possible to provide a vacuum channel field effect transistor capable of increasing a current between a source and a drain by providing an impurity diffusion layer as a source, a method for manufacturing the same, and a semiconductor device.

Drawings

Fig. 1 is a sectional view showing the structure of an FET according to a first embodiment of the present invention.

Fig. 2 is a plan view showing the structure of an FET according to a first embodiment of the present invention.

Fig. 3 is a sectional perspective view showing the structure of an FET according to a first embodiment of the present invention.

Fig. 4 is a sectional view showing the manufacturing method of the FET according to the first embodiment of the present invention in stages, and is a sectional view at a stage where the second insulating film is formed.

Fig. 5 is a sectional view showing a manufacturing method of an FET according to the first embodiment of the present invention in stages, and is a sectional view at a stage where an n + impurity diffusion layer is formed.

Fig. 6 is a sectional view showing the structure of an FET circuit according to a second embodiment of the present invention.

Fig. 7 is a sectional view showing the structure of an FET according to a third embodiment of the present invention.

Fig. 8 is a sectional perspective view showing the structure of an FET according to a third embodiment of the present invention.

Fig. 9 is a sectional view showing the structure of an FET according to a fourth embodiment of the present invention.

Fig. 10 is a sectional view showing the structure of an FET circuit according to a fifth embodiment of the present invention.

Fig. 11 is a sectional view showing the structure of an FET according to a sixth embodiment of the present invention.

Fig. 12 is a sectional view showing a method of manufacturing an FET according to a sixth embodiment of the present invention in stages, and is a sectional view at a stage where a filler is formed.

Fig. 13 is a sectional view showing a method of manufacturing an FET according to a sixth embodiment of the present invention in stages, and is a sectional view at a stage where a cap opening is formed.

Fig. 14 is a sectional view showing the structure of an FET according to a seventh embodiment of the present invention.

Fig. 15 is a perspective view showing the structure of an FET according to a seventh embodiment of the present invention.

Fig. 16 is a sectional view showing a method of manufacturing an FET according to a seventh embodiment of the present invention in stages, and is a sectional view at a stage where a second insulating film is formed.

Fig. 17 is a sectional view showing a manufacturing method of an FET according to a seventh embodiment of the present invention in stages, and is a sectional view at a stage where a gate electrode is formed.

Fig. 18 is a sectional view showing a manufacturing method of an FET according to a seventh embodiment of the present invention in stages, and is a sectional view at a stage where an n + impurity diffusion layer is formed.

Fig. 19 is a sectional view showing the structure of an FET according to a seventh embodiment of the present invention.

Fig. 20 is a perspective view showing the structure of an FET circuit according to an eighth embodiment of the present invention.

Detailed Description

(first embodiment)

A vacuum channel field effect transistor 100 (hereinafter, referred to as an FET100) according to a first embodiment of the present invention will be described with reference to fig. 1 to 3. Fig. 1 is a sectional view at a position a-a' in the top view of fig. 2. Fig. 3 is a perspective view of a cross section at a-a' position in the top view of fig. 2, as viewed from above.

In fig. 1 to 3, the FET100 of the first embodiment is an n-type FET, and a first insulating film 2, a gate electrode 3, a second insulating film 4, and a drain electrode 7 are formed in this order on a p-type semiconductor substrate 1. Further, an opening 5 is formed to penetrate the second insulating film 4, the gate electrode 3, and the first insulating film 2 and reach the p-type semiconductor substrate 1. An n + impurity diffusion layer 6 functioning as a source is formed on the p-type semiconductor substrate 1 in the opening 5. The side surfaces of the first insulating film 2, the gate electrode 3, and the second insulating film 4 are exposed on four side walls of the opening 5, and the four side walls are in contact with the n + impurity diffusion layers 6. A back surface electrode 8 is formed on the back surface of the p-type semiconductor substrate 1. The gate 3 and the drain 7 are connected to a voltage source capable of supplying a positive voltage, and the n + impurity diffusion layer 6 and the back electrode 8 are connected to a voltage source capable of supplying a negative voltage.

In the FET100, the direction of the vacuum channel is a direction perpendicular to the surface of the n + impurity diffusion layer 6 (longitudinal direction in fig. 1).

When the P-type semiconductor substrate 1 is a P-type silicon substrate, As (arsenic) or P (phosphorus) As an n-type impurity is introduced into the P-type semiconductor substrate 1 and heat treatment is performed, whereby the n + impurity diffusion layer 6 is formed on the bottom surface of the opening 5. n + impurity diffusion layer 6 covers the entire bottom surface of opening 5 and is preferably in contact with first insulating film 2, but may extend outside the side surface of opening 5 and be in contact with the bottom of first insulating film 2. In addition, n + impurity diffusion layer 6 does not necessarily need to cover the entire bottom surface of opening 5 as long as it does not affect the FET operation.

The thickness of the first insulating film 2 is, for example, 2nm to 20nm, and when the p-type semiconductor substrate 1 is a p-type silicon substrate, the material may be, for example, a silicon oxide film obtained by subjecting the surface of the p-type semiconductor substrate 1 to oxidation treatment, or a silicon oxide film deposited by CVD or the like. The thickness of the second insulating film 4 is, for example, 10nm or more and 20nm or less, and may be, for example, an insulating film including a silicon oxide film or a silicon nitride film deposited by a CVD method or the like.

The thicknesses of the first insulating film 2 and the second insulating film 4 are not necessarily the same thickness, and as described later, the thickness of the first insulating film 2 is preferably formed thinner than the thickness of the second insulating film 4. In this case, for example, the thickness of the first insulating film 2 is 2nm or more and 10nm or less, and the thickness of the second insulating film 4 is 15nm or more and 30nm or less.

The gate electrode 3 is formed of a conductive film such as a metal or polysilicon into which an n-type impurity is introduced, and has a thickness of, for example, 10nm to 20 nm.

The drain electrode 7 is formed of a conductive film such as metal or polysilicon, and has a thickness of, for example, 50nm or more and 200nm or less.

The back electrode 8 is formed of a metal such as Al or a conductive layer such as an impurity diffusion layer, and has a thickness of, for example, 50nm or more and 200nm or less. The substrate voltage of the p-type semiconductor substrate 1 of the FET100 is applied to the back surface electrode 8. In the case where an n-type diffusion layer for applying a voltage to the substrate of the p-type semiconductor substrate 1 is separately provided on the surface of the p-type semiconductor substrate 1, the back surface electrode 8 may be omitted.

The opening 5 may be a square having a side length of 0.05 μm or more and 0.5 μm or less, for example, in the plan view of fig. 2. As shown in fig. 1 to 3, n + impurity diffusion layer 6 is formed on the bottom surface of opening 5, and the side surfaces of first insulating film 2, gate electrode 3, and second insulating film 4 are exposed on the four side walls of opening 5.

(principle of action)

Next, the operation of the FET100 will be described. The FET100 is an n-type FET, and a vacuum space facing the inside of the opening 5 including the side walls of the first insulating film 2, the gate electrode 3, and the second insulating film 4 serves as a channel for electrons as charge carriers (hereinafter, the vacuum space serving as a channel is sometimes referred to as a vacuum channel space).

By applying a gate-source voltage V_GS(hereinafter, it may be referred to as "V")_GS) Electrons are discharged into a vacuum channel space at a predetermined voltage, and a source-drain voltage V is set to_DS(hereinafter, it may be referred to as "V")_DS) The released movement is performed with a predetermined voltage. Specifically, by applying a positive voltage from the gate electrode 3 to the above-mentioned vacuum channel space and applying a negative voltage or GND voltage to the n + impurity diffusion layer 6 as a source, FN (Fowler-Nordheim) tunneling of electrons in the n + impurity diffusion layer 6 to the vacuum barrier occurs, whereby the electrons are released to the vacuum channel space. As shown by the arrows in fig. 1, electrons are discharged from n + impurity diffusion layer 6 as a source in a direction perpendicular to the surface of n + impurity diffusion layer 6 (vertical direction in fig. 1), that is, in the same direction as the vacuum channel direction. Electrons e released into the vacuum channel space are converted into V_DSThe generated electric field is attracted to the drain 7.

By applying a positive voltage to the gate electrode 3, the surface of the p-type semiconductor substrate 1 in contact with the first insulating film is depleted, and electrons in the inversion layer are accumulated. Since n + impurity diffusion layer 6 is in contact with the side wall of opening 5, electrons in the inversion layer and n + impurity diffusion layer 6 are in a connected state. Therefore, by applying a positive voltage or GND voltage to the n + impurity diffusion layer 6, electrons of the inversion layer are caused to flow into the n + impurity diffusion layer 6. In this way, electrons in the inversion layer can be used as charge carriers of the FET100 in addition to electrons in the n + impurity diffusion layer 6 described above. In order to use electrons of the inversion layer as charge carriers of the FET100 and to facilitate the flow of electrons of the inversion layer into the n + impurity diffusion layer 6, it is preferable that the n + impurity diffusion layer 6 is extended toward the p-type semiconductor substrate 1 side in contact with the first insulating film 2 so that the n + impurity diffusion layer 6 is formed in contact with the bottom surface of the first insulating film 2.

When the FET100 is turned on, a voltage of, for example, 0V is applied to the n + impurity diffusion layer 6 as the source, a voltage of, for example, +2V is applied to the drain 7, a voltage of, for example, +1V is applied to the gate 3, and a voltage of, for example, 0V is applied to the back surface electrode 8.

As described above, since the release of electrons is caused by the FN tunneling effect between the n + impurity diffusion layer 6 and the vacuum, the positive voltage applied from the gate 3 to the vacuum channel space is preferably applied in the vicinity of the interface of the n + impurity diffusion layer 6 and the vacuum. Therefore, the thickness of the first insulating film 2 is preferably formed thinner than the thickness of the second insulating film 4.

In the above description, the case where the FET100 is an N-type FET was described, but the FET100 can also be made a p-type FET by making the p-type semiconductor substrate 1 an N-type semiconductor substrate or an N-well and making the N + impurity diffusion layer 6 a p-type impurity diffusion layer. When the FET100 is a p-type FET, holes that become charge carriers are released from the p + impurity diffusion layer into the vacuum channel space, move through the vacuum channel space, and reach the drain 7. The release of holes into the vacuum channel space is performed by applying V as in the case where FET100 is an n-type FET_GSSet to a predetermined voltage, and the movement after release is performed by setting V to a predetermined voltage_DSIs performed at a predetermined voltage. Specifically, by applying a negative voltage from the gate 3 to the above-described vacuum channel space and applying a positive voltage or GND voltage to the p + impurity diffusion layer as a source, the holes in the p + impurity diffusion layer are caused to undergo the FN tunneling effect against the vacuum barrier, whereby the holes are released to the vacuum channel space. The holes are discharged from the p + impurity diffusion layer as the source in the longitudinal direction (vertical direction) with respect to the p + impurity diffusion layer, that is, in the same direction as the direction of the vacuum channel. Hole passage V released into vacuum channel space_DSThe generated electric field moves in vacuum to reach the drain 7. In the case where the FET100 is a p-type FETThe FET100 can be turned on by applying, for example, 0V to the p + impurity diffusion layer as the source, for example, -2V to the drain 7, and for example, -1V to the gate 3.

The channel length L of the FET100 is the height from the n + impurity diffusion layer 6 to the drain 7, i.e., the sum of the thicknesses of the first insulating film 2, the gate 3, and the second insulating film 4. Since the mean free path of electrons in vacuum is about 60nm, the sum of the thicknesses of the first insulating film 2, the gate electrode 3, and the second insulating film 4 is preferably 60nm or less.

The channel width W of the FET100 corresponds to the circumference and area of the opening 5. Therefore, by increasing at least one of the perimeter and the area of the opening 5, the source-drain current I can be increased_DS. Although the upper surface and the lower surface of the opening 5 are set to be square in the above description and fig. 1 to 3, the present embodiment is not limited to this, and the upper surface and the lower surface of the opening 5 may be set to be, for example, circular, elliptical, polygonal or star-shaped in order to increase at least one of the circumferential length and the area.

In the above description, the FET100 uses the entire internal space of the four sidewalls facing the opening 5 as a channel, but the present embodiment is not limited thereto, and at least one sidewall including the first insulating film 2, the gate electrode 3, and the second insulating film 4 may be provided for one n + impurity diffusion layer 6. In order to increase the source-drain current, it is preferable that there are two or more side walls for one n + impurity diffusion layer 6.

In the above description, the inside of the opening 5 is set to be vacuum, but the present embodiment is not limited to this, and the inside of the opening 5 may be air. When the inside of the opening 5 is air, the mean free path of electrons in the air is shorter than that in vacuum, and therefore the channel length L is preferably shorter than that in vacuum.

Although the structure in which FET100, which is an n-type FET, is formed on p-type semiconductor substrate 1 has been described above, the PN junction formed by p-type semiconductor substrate 1 and n + impurity diffusion layer 6 does not directly contribute to the operation of FET 100. In addition, the parasitic capacitance and junction leakage due to the PN junction also become a factor that degrades the high speed and reliability of the FET 100. Therefore, the n + impurity diffusion layer 6 serving as a source of electron emission may have a structure in which a PN junction is not formed with another semiconductor layer, and in this case, high speed and reliability of the FET100 can be improved. In the case where the PN junction is not formed, for example, the first insulating film 2, the gate electrode 3, and the second insulating film 4 may be formed in this order on the N-type semiconductor substrate or the N-well but not on the P-type semiconductor substrate 1 or the P-well, and then the opening portion 5, the N + impurity diffusion layer 6, the drain electrode 7, and the back surface electrode 8 may be formed.

In the case where the FET100 is a p-type FET, a p-type impurity diffusion layer serving as a hole release source may be configured not to form a PN junction with another semiconductor layer, for the same reason as in the case where the FET100 is an n-type FET. In this case, for example, the first insulating film 2, the gate electrode 3, and the second insulating film 4 may be formed in this order on a P-type semiconductor substrate or a P-well, and then the opening portion 5, the P + impurity diffusion layer, the drain electrode 7, and the back surface electrode 8 may be formed instead of being formed on an N-well or an N-type semiconductor substrate or an N-well.

(production method)

Next, an example of a method for manufacturing the FET100 in the case of using a silicon substrate as the p-type semiconductor substrate 1 will be described. First, as shown in fig. 4, a silicon oxide film is formed on the surface of the p-type semiconductor substrate 1 as the first insulating film 2 by a thermal oxidation method, for example, to a thickness of 20 nm. Next, a P (phosphorus) -doped polysilicon layer is formed as a gate electrode 3 on the first insulating film 2 by a CVD method with a thickness of, for example, 20 nm. Next, a silicon oxide film is formed as the second insulating film 4 on the gate electrode 3 by a plasma CVD method with a thickness of, for example, 20 nm. The sectional view at this stage is fig. 4.

Next, a photoresist (not shown) is formed on the second insulating film 4 by photolithography so that a region other than the region where the FET100 is formed and the region where the opening 5 is formed (see fig. 2) are opened. Next, the second insulating film 4, the gate electrode 3, and the first insulating film 2 exposed are removed using a photoresist as a mask by a dry etching method, thereby forming the opening 5.

Next, As (arsenic) ions are implanted into the p-type semiconductor substrate 1 in the opening 5 by an ion implantation method to form an n + impurity diffusion layer 6, and then the photoresist is removed. The sectional view at this stage is fig. 5.

Next, Al (aluminum) is formed in a thickness of, for example, 100nm by a sputtering method.

Thereafter, the formed Al is processed into the shape of the drain electrode 7 by photolithography and dry etching. As shown in fig. 1 to 3, the drain electrode 7 is formed on the second insulating film 4. Next, Al is formed on the back surface of the p-type semiconductor substrate 1 by a sputtering method with a thickness of, for example, 200 nm. Through the above steps, the FET100 shown in fig. 1 can be produced.

In the above description, the opening 5 is formed by photolithography and dry etching, but the present embodiment is not limited to this. For example, the opening 5 may be formed by dry etching with Ga (gallium) ions using an FIB (Focused Ion Beam) device without using photolithography. Further, Al to be the drain electrode 7 and the back electrode 8 is formed by a sputtering method, but instead of Al, Ga may be deposited by, for example, an FIB apparatus. Further, a P well into which a P-type impurity is introduced may be formed on the P-type semiconductor substrate 1 as necessary.

(Effect)

In the conventional vacuum channel FET, the discharge of charge carriers proceeds only from the sidewall of the source or cathode in a direction perpendicular to the direction of the vacuum channel. Therefore, it is difficult to increase the source-drain current. In addition, in the conventional vacuum channel FET, if the thickness of the source or the cathode is increased in order to increase the area of the sidewall which is a discharge source of the charge carriers, there is a problem that the vertical dimension of the FET increases. In contrast, in FET100 of the present embodiment, electrons as charge carriers are released into a vacuum from n + impurity diffusion layer 6 provided on the surface of p-type semiconductor substrate 1 in a direction perpendicular to the surface of n + impurity diffusion layer 6. By using the impurity diffusion layer as a charge carrier emission source, the area of the charge carrier emission source can be increased as compared with the sidewall of the conventional source or cathode, and therefore the emission amount of charge carriers can be increased as compared with the conventional case. Further, since the charge carriers in the inversion layer on the surface of the semiconductor substrate 1 in contact with the first insulating film 2 can be released into the vacuum through the impurity diffusion layer, the amount of the released charge carriers can be increased as compared with the conventional case. Further, since the charge carriers of the FET100 are discharged from the impurity diffusion layer in the same direction as the direction of the vacuum channel (direction parallel to the direction of the vacuum channel), the charge carriers can be more efficiently discharged than in the conventional case. Therefore, a high-performance vacuum channel FET capable of increasing the source-drain current can be obtained as compared with the conventional case.

(second embodiment)

In the first embodiment, the case where the vacuum channel field effect transistor is an n-type FET and the case where the vacuum channel field effect transistor is a p-type FET have been described, but a semiconductor device having a complementary FET circuit in which an n-type FET and a p-type FET are formed on the same semiconductor substrate may be configured.

As shown in fig. 6, a vacuum channel field effect transistor circuit 110 (hereinafter referred to as an FET circuit 110) of the second embodiment is a complementary FET circuit composed of an n-type FET and a p-type FET. The same portions as those in the first embodiment are denoted by the same reference numerals, and common descriptions may be omitted.

The n-type FET shown on the left side of fig. 6 has the same configuration as the FET100 described in the first embodiment, and a first insulating film 2, a gate electrode 3, a second insulating film 4, and a drain electrode 7 are formed in this order on a p-type semiconductor substrate 1. Further, the semiconductor device has an opening 5 which penetrates the second insulating film 4, the gate electrode 3, and the first insulating film 2 and reaches the p-type semiconductor substrate 1. An n + impurity diffusion layer 6 functioning as a source is formed on the p-type semiconductor substrate 1 in the opening 5.

The p-type FET shown on the right side of fig. 6 has the same configuration as the FET100 described in the first embodiment, and has a first insulating film 2, a gate electrode 3, a second insulating film 4, and a drain electrode 7 formed in this order on an N well 9 having an N-type impurity introduced into a p-type semiconductor substrate 1, and an opening 5 penetrating the second insulating film 4, the gate electrode 3, and the first insulating film 2 and reaching the N well 9. A p + impurity diffusion layer 10 functioning as a source is formed in the N well 9 in the opening 5.

As an example of the complementary FET circuit, a case where the FET circuit 110 is a complementary inverter circuit will be described. As shown in fig. 6, in the FET circuit 110, the gates 3 and the drains 7 of the n-type FET and the p-type FET are connected to each other, respectively. The gates 3 of the n-type FET and the p-type FET are connected to a voltage source of the complementary inverter circuit that supplies the input voltage. The output voltage of the complementary inverter circuit is output to the outside from the drains 7 of the n-type FET and the p-type FET. The N + impurity diffusion layer 6 and the back surface electrode 8 are connected to a voltage source that can supply a negative voltage, and the p + impurity diffusion layer 10 and the N well 9 are connected to a voltage source that can supply a positive voltage.

In the complementary inverter circuit operation, a GND voltage of, for example, 0V is applied to the n + impurity diffusion layer 6 of the n-type FET, and a positive voltage of, for example, +2V is applied to the p + impurity diffusion layer 10 of the p-type FET. A GND voltage, for example, is applied to the p-type semiconductor substrate 1 via the back electrode 8. A positive voltage of, for example, +2V is applied to the N-well 9. In this state, a positive voltage of, for example, +2V or a GND voltage of 0V is applied to the gates 3 of the n-type FET and the p-type FET as an input signal of the complementary inverter circuit, whereby an output voltage as an output signal of the complementary inverter circuit is output from the drains 7 of the n-type FET and the p-type FET to the outside. Before the input signal voltage reaches the GND voltage or +2V, both the p-type FET and the n-type FET are turned on and a current flows, and after the input signal voltage reaches the GND voltage or +2V, one of the p-type FET and the n-type FET is turned off and a current does not flow. Thus, the FET circuit 110 is a low-power circuit that performs the same operation as a conventional cmos inverter circuit.

The example shown in fig. 6 is an example of a case where the FET circuit 110 is a complementary inverter circuit, and various modifications can be made within the scope of the present invention. For example, the wiring diagram of fig. 6 may be changed as necessary, and the voltages applied to the gate electrode 3, the N + impurity diffusion layer 6, the p + impurity diffusion layer 10, the p-type semiconductor substrate 1, and the N well 9 may be supplied via other voltage sources, other wirings, and other circuits, respectively. The FET circuit 110 can be implemented by being modified to other complementary FET circuits, for example, a differential amplifier circuit having a plurality of n-type FETs and p-type FETs, an SRAM circuit, and the like. In addition, the input signal is not limited to a positive voltage of +2V or a voltage of 0V, and for example, a negative voltage may be applied instead of the voltage of 0V in order to increase hole discharge efficiency from the p + impurity diffusion layer 10 of the p-type FET.

(production method)

Next, a method of manufacturing the FET circuit 110 will be described. First, a photoresist (not shown) that is open only in the region where the p-type FET is formed on the p-type semiconductor substrate 1 by photolithography. Next, P (phosphorus) as an N-type impurity is implanted into the P-type semiconductor substrate 1 by an ion implantation method, thereby forming the N well 9. Next, a method of sequentially forming the first insulating film 2, the gate electrode 3, and the second insulating film 4 on the surface of the p-type semiconductor substrate 1 is the same as that of the first embodiment, and therefore, description thereof is omitted.

Next, a photoresist is formed on the second insulating film by photolithography so that a region other than the region where the n-type FET and the p-type FET are formed in fig. 6 and a region where the opening portion 5 of each of the n-type FET and the p-type FET is formed are opened. Next, the second insulating film 4, the gate electrode 3, and the first insulating film 2 are removed by a dry etching method using a photoresist as a mask, and then the photoresist is removed.

Next, after a photoresist that opens only the region where the n-type FET is to be formed is formed by photolithography, As (arsenic) ions are implanted into the p-type semiconductor substrate 1 in the opening 5 of the n-type FET by ion implantation to form the n + impurity diffusion layer 6, and then the photoresist is removed. Next, after a photoresist for opening only the region where the p-type FET is to be formed is formed by photolithography, B (boron) ions are implanted into the N well 9 in the opening 5 of the p-type FET by ion implantation to form a p + impurity diffusion layer 10, and then the photoresist is removed. The method of sequentially forming the drain electrode 7 and the back electrode 8 is the same as that of the first embodiment, and therefore, the description thereof is omitted.

(Effect)

As described above, according to this embodiment, a semiconductor device including a complementary FET circuit which is formed by forming an n-type FET and a p-type FET having a vacuum channel on the same semiconductor substrate and operates at low power can be obtained.

(third embodiment)

The vacuum channel field effect transistor 120 (hereinafter referred to as FET120) according to the third embodiment is different from the first embodiment in that a sidewall portion of the gate electrode 3 is provided with the sidewall insulating film 11, and the other configuration is the same as that of the first embodiment. The same portions as those in the first embodiment are denoted by the same reference numerals, and common descriptions may be omitted.

As shown in fig. 7 and 8, the FET120 of the third embodiment has a sidewall insulating film 11 on the sidewall of the gate 3. The sidewall insulating film 11 may be formed at least on the sidewall of the gate electrode 3 facing the opening 5. The sidewall insulating film 11 may be formed by thermally oxidizing a polysilicon film formed as the gate electrode 3, or may be formed by a CVD method or a sputtering method.

(production method)

Next, a method for manufacturing the FET120 will be described. A method of sequentially forming the first insulating film 2, the gate electrode 3, and the second insulating film 4 on the surface of the p-type semiconductor substrate 1, and then forming the opening portion 5 and the n + impurity diffusion layer 6 is the same as that of the first embodiment, and therefore, description thereof is omitted.

When the sidewall insulating film 11 is formed by thermal oxidation, the gate electrode 3 is formed of, for example, a polysilicon film into which an n-type impurity of 10nm to 20nm is introduced. After the opening 5 is formed, the surface of the exposed polysilicon film constituting the gate electrode 3 is thermally oxidized by a thermal oxidation method. Next, the thermal oxide film formed simultaneously on n + impurity diffusion layer 6 by this thermal oxidation is removed by anisotropic etching, thereby forming sidewall insulating film 11 on the sidewall of gate electrode 3. The thickness of the sidewall insulating film 11 is, for example, 1nm to 10 nm. When the sidewall insulating film 11 is formed by a CVD method or a sputtering method, the gate electrode 3 may be made of a metal such as copper or tungsten instead of polysilicon. After the n + impurity diffusion layer 6 is formed, a silicon oxide film is deposited by a CVD method, for example, as in the case of thermal oxidation. Then, the silicon oxide film simultaneously deposited on the n + impurity diffusion layer 6 by this CVD method is removed by anisotropic etching, thereby forming a sidewall insulating film 11 on the sidewall of the gate electrode 3. Next, the method of sequentially forming the drain electrode 7 and the back electrode 8 is the same as that of the first embodiment, and therefore, the description thereof is omitted.

(Effect)

In the present embodiment, the sidewall insulating film 11 is provided on the sidewall of the gate electrode 3, so that electrons are emitted from the gate electrodeThe vacuum space inside the opening 5 can suppress trapping of some electrons by the gate electrode 3 to which a positive potential is applied, while moving from the n + impurity diffusion layer 6 to the drain electrode 7. Therefore, the source-drain current I can be set_DSIn addition, a high-performance vacuum channel FET can be obtained.

(fourth embodiment)

The vacuum channel field effect transistor 130 (hereinafter referred to as FET130) according to the fourth embodiment is different from the first embodiment in that it includes the drain 7 extending above the opening 5, and the other configuration is the same as that of the first embodiment. The same portions as those in the first embodiment are denoted by the same reference numerals, and common descriptions may be omitted.

As shown in fig. 9, in the FET130 of the fourth embodiment, the drain 7 is formed so as to cover the entire upper portion of the opening 5. The drain 7 may extend to the n + impurity diffusion layer 6 side of the side surface of the second insulating film 4 within a range not covering the entire upper portion of the opening 5, and may partially cover the upper portion of the opening 5.

(production method)

Next, a method for manufacturing the FET130 will be described. A method of sequentially forming the first insulating film 2, the gate electrode 3, and the second insulating film 4 on the surface of the p-type semiconductor substrate 1, and then forming the opening portion 5 and the n + impurity diffusion layer 6 is the same as that of the first embodiment, and therefore, description thereof is omitted.

After the n + impurity diffusion layer 6 is formed, Ga (gallium) as a conductive film is deposited so as to cover the entire upper portion of the opening 5 or a part thereof using an fib (focused Ion beam) apparatus. The thickness of the Ga deposition layer to be the drain 7 may be, for example, 50nm or more and 200nm or less. Alternatively, after the n + impurity diffusion layer 6 is formed, Al may be formed in a thickness of, for example, 50nm to 200nm before the formation of the n + impurity diffusion layer by a sputtering method, and then the Al may be patterned by a photolithography method or a dry etching method so as to cover the entire upper portion of the opening portion 5 or a part thereof.

(Effect)

Electrons released from n + impurity diffusion layer 6 serving as a source move to drain 7 in a vacuum space in opening 5. The drain electrode 7 is formed to extend to a larger extent than the second insulating layerThe side surface of insulating film 4 is closer to n + impurity diffusion layer 6 side and covers all or part of the upper part of opening 5, thereby increasing the number of electrons reaching drain 7, and thus, it is possible to obtain source-drain current I_DSIncreased high performance vacuum channel FETs.

(fifth embodiment)

A vacuum channel field effect transistor circuit 140 (hereinafter referred to as an FET circuit 140) of the fifth embodiment is a complementary FET circuit formed On an SOI (Silicon On Insulator) substrate. The same portions as those in the first embodiment or the second embodiment are denoted by the same reference numerals, and common descriptions may be omitted.

As shown in fig. 10, the FET140 circuit of the fifth embodiment is a complementary FET circuit including an n-type FET and a p-type FET, which is formed on an SOI substrate having a supporting substrate 12, a buried silicon oxide layer 13, and an n-type silicon active layer 14.

The n-type FET shown on the left side of fig. 10 has a first insulating film 2, a gate electrode 3, a second insulating film 4, and a drain electrode 7 formed in this order on an n-type silicon active layer 14. Further, the semiconductor device has an opening 5 which penetrates the second insulating film 4, the gate electrode 3, and the first insulating film 2, and reaches the n-type silicon active layer 14. An n + impurity diffusion layer 6 functioning as a source is formed on the n-type silicon active layer 14 in the opening 5.

In the P-type FET shown on the right side of fig. 10, the first insulating film 2, the gate electrode 3, the second insulating film 4, and the drain electrode 7 are formed in this order on the P well 15 having the P-type impurity introduced into the n-type silicon active layer 14. The bottom of the P-well 15 reaches the buried silicon oxide layer 13. Further, the semiconductor device has an opening 5 penetrating the second insulating film 4, the gate electrode 3, and the first insulating film 2 and reaching the P well 15. A P + impurity diffusion layer 10 functioning as a source is formed in the P well 15 in the opening 5. The n-type silicon active layer 14 and the P-well 15 are electrically isolated by an element isolation region 16.

As an example of a complementary FET circuit formed on an SOI substrate, a case where the FET circuit 140 is a complementary inverter circuit will be described. As shown in fig. 10, in the FET circuit 140, the gates 3 and the drains 7 of the n-type FET and the p-type FET are connected to each other, respectively. The gates 3 of the n-type FET and the p-type FET are connected to a voltage source of the complementary inverter circuit that supplies the input voltage. The output voltage of the complementary inverter circuit is output to the outside from the drains 7 of the n-type FET and the p-type FET. The n + impurity diffusion layer 6 is connected to a voltage source capable of supplying a GND voltage, and the p + impurity diffusion layer 10 is connected to a voltage source capable of supplying a positive voltage. Further, a power source capable of supplying a GND voltage may be connected to the n-type silicon active layer 14, and a voltage source capable of supplying a positive voltage may be connected to the P-well 15.

In the operation of the complementary inverter circuit, a GND voltage of, for example, 0V is applied to the n + impurity diffusion layer 6 of the n-type FET, and a positive voltage of, for example, +2V is applied to the p + impurity diffusion layer 10 of the p-type FET. Further, a positive voltage of, for example, +2V may be applied to the P well 15, and a GND voltage of, for example, 0V may be applied to the n-type silicon active layer 14. In this state, a positive voltage of, for example, +2V or a GND voltage of 0V is applied to the gates 3 of the n-type FET and the p-type FET as an input signal of the complementary inverter circuit, whereby an output voltage as an output signal of the complementary inverter circuit is output from the drains 7 of the n-type FET and the p-type FET to the outside. In this case, as in the conventional CMOS inverter circuit including NMOS and PMOS transistors, a current flows until the input signal reaches the potential of +2V or GND, but the current flowing through the circuit becomes 0 after the input signal reaches the potential of +2V or GND.

The example shown in fig. 10 is an example of a case where the FET circuit 140 is a complementary inverter circuit, and various modifications can be made within the scope of the present invention. For example, the wiring diagram of fig. 10 may be changed as necessary, and the voltages applied to the gate electrode 3, the n + impurity diffusion layer 6, and the p + impurity diffusion layer 10 may be supplied via another voltage source, another wiring, and another circuit. The FET circuit 140 can be implemented by being modified to other complementary FET circuits, for example, a differential amplifier circuit having a plurality of n-type FETs and p-type FETs, an SRAM circuit, and the like. In addition, the input signal is not limited to a positive voltage of +2V or a voltage of 0V, and for example, a negative voltage may be applied instead of the voltage of 0V in order to increase hole discharge efficiency from the p + impurity diffusion layer 10 of the p-type FET.

(Effect)

In the n-type FET of the FET circuit 140 of the present embodiment, the n + impurity diffusion layer 6 functioning as a source is formed on the n-type silicon active layer 14. By configuring the n + impurity diffusion layer 6 and the other semiconductor layer in such a manner as not to form a PN junction, as described in the first embodiment, the high speed and reliability of the n-type FET of the FET circuit 140 can be improved. Similarly, in the P-type FET of the FET circuit 140, the P + impurity diffusion layer 10 serving as a source is formed in the P well 15. By configuring the p + impurity diffusion layer 10 and the other semiconductor layer in such a manner as not to form a PN junction, the high speed and reliability of the p-type FET of the FET circuit 140 can be improved. In the n-type FET of the FET circuit 140 according to the present embodiment, the n-type silicon active layer 14 of the n-type FET and the P-well 15 of the P-type FET are provided on the embedded silicon oxide layer 13 of the SOI substrate, so that parasitic capacitance and junction leakage due to the PN junction do not occur. Therefore, the FET circuit 140 of the present embodiment is suitable for applications requiring radiation resistance and high temperature resistance that are difficult to utilize in conventional MOS transistors.

(sixth embodiment)

A vacuum channel field effect transistor 150 (hereinafter, referred to as FET150) according to the sixth embodiment has a structure in which a vacuum or air space in a side surface direction and an upper surface direction is isolated from outside air by an insulating film. The other configurations are the same as the first embodiment. The same portions as those in the first embodiment are denoted by the same reference numerals, and common descriptions may be omitted. A technique for producing a hollow structure is described in, for example, US6,268,261B1.

As shown in fig. 11, the FET150 of the sixth embodiment has a first insulating film 2, a gate electrode 3, a second insulating film 4, and a drain electrode 7 formed in this order on a p-type semiconductor substrate 1. Further, an opening 5 is formed to penetrate the second insulating film 4, the gate electrode 3, and the first insulating film 2 and reach the p-type semiconductor substrate 1. An n + impurity diffusion layer 6 functioning as a source is formed on the p-type semiconductor substrate 1 in the opening 5. A back surface electrode 8 is formed on the back surface of the p-type semiconductor substrate 1. The above-described structure is the same as the FET100 of the first embodiment.

The FET150 includes a hollow portion 22 that is isolated from the outside air around a laminated structure (hereinafter, may be simply referred to as a laminated structure) including the first insulating film 2, the gate electrode 3, the second insulating film 4, and the drain electrode 7. The hollow portion 22 is constituted by a space surrounded by the first cap layer 17, the second cap layer 19, and the cap layer 21. The first cap layer 17 is integrally formed on the side surface of the hollow portion 22. The hollow portion 22 has, on its upper surface: a second cap layer 19 having a cap opening 20, and a cap layer 21 formed on the second cap layer 19 so as to cover the cap opening 20.

The first cap layer 17 is made of, for example, a silicon nitride film, and has a thickness of, for example, 80nm or more and 200nm or less. The second cap layer 19 is made of, for example, a silicon nitride film, and has a thickness of, for example, 20nm or more and 100nm or less. The cap layer 21 is made of, for example, a silicon oxide film, and has a thickness of, for example, 100nm or more and 500nm or less.

(production method)

Next, an example of a method for manufacturing the FET150 will be described. A method of forming the first insulating film 2, the gate electrode 3, and the second insulating film 4 in this order on the surface of the p-type semiconductor substrate 1, and then forming the opening 5, the n + impurity diffusion layer 6, the drain electrode 7, and the back surface electrode 8 is the same as in the first embodiment, and therefore, the description thereof is omitted.

Then, a silicon nitride film, a silicon oxide film, or the like is formed as the first cap layer 17 by a CVD method, for example, to a thickness of 80nm or more and 200nm or less. Next, the first cap layer 17 is patterned by photolithography and dry etching. Thereby, the first cap layer 17 is formed to surround the entire periphery in the side surface direction of the laminated structure having the first insulating film 2, the gate electrode 3, the second insulating film 4, and the drain electrode 7.

Then, the filler 18 is formed to have a thickness of, for example, 100nm or more and 400nm or less. As the filler, for example, amorphous carbon can be formed into a film by a sputtering method. Next, the filler 18 on the first cap layer 17 is removed by a CMP method. Thereby, the space between the first cap layer 17 and the laminated structure is filled with the filler 18. The sectional view at this stage is fig. 12.

Then, a silicon nitride film or a silicon oxide film is formed as the second cap layer 19 by a CVD method, for example, to a thickness of 20nm or more and 100nm or less. Next, the second cap layer 19 is patterned by photolithography and dry etching, and a cap opening 20 is formed in a part of the second cap layer 19 so as to expose a part of the surface of the filler 18. Next, heat treatment is performed, for example, at 400 ℃ for 2 hours in an oxygen-containing atmosphere. By this heat treatment, the amorphous carbon as the filler 18 is vaporized and released from the lid opening 20 to the outside, thereby removing the filler 18. Fig. 13 is a sectional view of a stage at which the heat treatment is started, and the gasified amorphous carbon is released to the outside through the lid opening 20 as indicated by an arrow in fig. 13.

Then, a silicon oxide film having a thickness of, for example, 100nm or more and 500nm or less is formed as the capping layer 21 by a CVD method, and the hollow portion 22 is formed by burying the cap opening portion 20. The hollow portion 22 may be filled with air or vacuum. Alternatively, an inert gas such as nitrogen or argon may be injected into the hollow portion 22.

(Effect)

The vacuum channel transistor uses the internal space of the opening portion 5 as a vacuum channel, and therefore, there is a problem that the transistor performance deteriorates with time due to exposure to the outside air. The FET150 can suppress the deterioration of the performance and reliability of the vacuum channel transistor with time by disposing the laminated structure including the first insulating film 2, the gate electrode 3, the second insulating film 4, and the drain electrode 7 in the hollow portion 22 isolated from the outside air. Therefore, the source-drain current I can be set_DSMoreover, a high-performance and highly reliable vacuum channel FET can be obtained.

(seventh embodiment)

A structure and a manufacturing method of a vacuum channel field effect transistor 200 (hereinafter referred to as an FET200) according to a seventh embodiment will be described with reference to fig. 14 to 19. Fig. 15 is a perspective view showing the entire structure of the FET200, and fig. 14 is a sectional view in the direction indicated by an arrow in fig. 15. In fig. 15, the rear surface electrode 38 and wiring lines connected to external terminals are not shown. In the following description, a description common to the first embodiment may be omitted.

As shown in fig. 14 and 15, the FET200 of the seventh embodiment has a first insulating film 32 and a second insulating film 34 thicker than the first insulating film 32 formed adjacent to each other on a p-type semiconductor substrate 31. A gate electrode 33 is stacked on the first insulating film 32, and a drain electrode 37 is stacked on the second insulating film 34. Further, an opening 35 is formed to penetrate the gate electrode 33 and the first insulating film 32 and reach the p-type semiconductor substrate 31. An n + impurity diffusion layer 36 functioning as a source is formed on the p-type semiconductor substrate 31 in the opening 35. A back surface electrode 38 is formed on the back surface of the p-type semiconductor substrate 31. The gate 33 and the drain 37 are connected to a voltage source that can supply a positive voltage, and the n + impurity diffusion layer 36 and the back electrode 38 are connected to a voltage source that can supply a negative voltage.

When the P-type semiconductor substrate 31 is a P-type silicon substrate, the n + impurity diffusion layer 36 is formed by introducing As (arsenic) or P (phosphorus) As an n-type impurity into the P-type semiconductor substrate 31 and performing heat treatment. n + impurity diffusion layer 36 preferably covers the entire bottom surface of opening 35 and contacts first insulating film 32, but may extend outside the side surface of opening 35 and contact the bottom of first insulating film 32. In addition, n + impurity diffusion layer 36 does not necessarily need to cover the entire bottom surface of opening 35 as long as it does not affect the FET operation.

The thickness of the first insulating film 32 is, for example, 5nm to 20nm, and when the p-type semiconductor substrate 31 is a p-type silicon substrate, the material may be, for example, a silicon oxide film obtained by oxidizing the surface of the p-type semiconductor substrate 31, or an insulating film including a silicon oxide film or a silicon nitride film deposited by a CVD method or the like. The second insulating film 34 has a thickness of, for example, 50nm or more and 100nm or less, and may be an insulating film including, for example, a silicon oxide film or a silicon nitride film deposited by a CVD method or the like.

The gate electrode 33 is formed of a conductive film such as a metal or polysilicon into which an n-type impurity is introduced, and has a thickness of, for example, 10nm to 20 nm.

The drain electrode 37 is formed of a conductive film such as metal or polysilicon, and has a thickness of, for example, 50nm or more and 200nm or less.

The back electrode 38 is formed of a metal such as Al or a conductive film such as polysilicon, and has a thickness of, for example, 50nm to 200 nm.

The opening 35 may be a rectangle having a short side length of 0.02 μm or more and 0.5 μm or less and a long side length of 0.01 μm or more and 5 μm or less, for example.

(principle of action)

Then, the operation of the FET200 is the same as that of the first embodiment. When the FET200 is turned on, a voltage of, for example, 0V is applied to the n + impurity diffusion layer 36 as a source, a voltage of, for example, +2V is applied to the drain 37, a voltage of, for example, +1V is applied to the gate 33, and a voltage of, for example, 0V is applied to the back surface electrode 38. By applying the voltage in this manner, FN tunneling occurs at the vacuum interface between the n + impurity diffusion layer 36 and the inside of the opening 35, and electrons are released from the surface of the n + impurity diffusion layer 36 to the vacuum inside the opening 35. The released electrons move toward the drain electrode 37 in vacuum and reach the drain electrode 37.

(production method)

An example of a method for manufacturing the FET200 when a p-type silicon substrate is used as the p-type semiconductor substrate 31 will be described below. After a silicon oxide film having a thickness of, for example, 80nm is formed as the second insulating film 34 on the surface of the p-type semiconductor substrate 31, the second insulating film 34 is patterned by photolithography and dry etching using a photoresist as a mask. As shown in fig. 15 and 16, the second insulating film 34 is two independent patterns separated from each other. The second insulating film 34 may be formed by a thermal oxidation method or a CVD method.

Then, on the surface of the p-type semiconductor substrate 31, a silicon oxide film having a thickness of, for example, 20nm is formed as the first insulating film 32 by a thermal oxidation method or a CVD method. Next, a P (phosphorus) -doped polysilicon layer having a thickness of, for example, 20nm is formed as the gate electrode 33 on the first insulating film 32 by a CVD method. Next, patterning is performed on the first insulating film 32 and the gate electrode 33 using a photoresist as a mask by photolithography and dry etching, thereby forming a stacked structure of the first insulating film 32 and the gate electrode 33 on the surface of the p-type semiconductor substrate 31 sandwiched by the second insulating film 34. The sectional view at this stage is fig. 17. As described above, the reason why the second insulating film 34 is formed prior to the first insulating film 32 is to prevent the first insulating film 32 from being thermally oxidized and changing the film thickness when the second insulating film 34 is formed by thermal oxidation.

Next, a photoresist (not shown) is formed by opening the region where the opening 35 is formed by photolithography. Then, the exposed gate electrode 33 and the first insulating film 32 are removed by a dry etching method using a photoresist as a mask, thereby forming an opening 35.

Next, As (arsenic) ions are implanted into the p-type semiconductor substrate 31 in the opening 35 by an ion implantation method to form an n + impurity diffusion layer 36, and then the photoresist is removed. The sectional view at this stage is fig. 18.

Next, Al having a thickness of, for example, 100nm is formed by a sputtering method, and then the formed Al is processed into the shape of the drain electrode 37 by a photolithography method and a dry etching method. As shown in fig. 14 and 15, the drain electrode 37 is formed on the second insulating film 34. Next, Al having a thickness of, for example, 200nm is formed on the front surface of the back surface side of the p-type semiconductor substrate 31 by sputtering. Through the above steps, the FET200 shown in fig. 14 can be produced.

In the above-described manufacturing method, a step of forming an insulating film on the surface of the gate electrode 33 may be added. In this case, for example, after the step of forming the opening 35 and the n + impurity diffusion layer 36 shown in fig. 18, a silicon oxide film having a thickness of, for example, 5nm or more and 10nm or less is formed as the third insulating film 39 by a CVD method. Next, the opening 35a can be formed by removing a part of the third insulating film 39 on the p-type semiconductor substrate 31 by photolithography and dry etching. Next, by forming the drain electrode 37 on the third insulating film 39 in the same manner as described above, the FET200 having the structure shown in fig. 19 can be manufactured.

(Effect)

In the first embodiment, the channel length L is the total thickness of the first insulating film 2, the gate electrode 3, and the second insulating film 4. In contrast, in the present embodiment, the channel length L may be determined only by the thickness of the second insulating film 34. Therefore, the channel length L can be easily adjusted as compared with the first embodiment, and the degree of freedom in designing the FET can be improved. In the first embodiment, in order to form the opening 5, it is necessary to process a three-layer structure of the first insulating film 2, the gate electrode 3, and the second insulating film 4. In contrast, in the FET200 of the present embodiment, only the two-layer structure of the first insulating film 32 and the gate electrode 33 may be processed to form the opening 35. Therefore, the processing accuracy of the opening 35 can be improved as compared with the opening 5 of the first embodiment.

In this embodiment, by forming the third insulating film 39 on the surface of the gate electrode 33, electrons can be prevented from being trapped in the gate electrode 33 while the electrons move from the n + impurity diffusion layer 36 to the drain electrode 37 in the vacuum space inside the opening 35. Therefore, the source-drain current I can be set_DSIn addition, a high-performance vacuum channel FET can be obtained.

(eighth embodiment)

A vacuum channel field effect transistor circuit 300 (hereinafter referred to as an FET circuit 300) of the eighth embodiment is a complementary FET circuit configured by a lateral channel FET having a fin structure.

In the first to seventh embodiments, the structure of the vertical vacuum channel FET in which the charge carriers are moved in the vertical direction (vertical direction) with respect to the surface of the semiconductor substrate has been described, but the structure of the horizontal vacuum channel FET in which the charge carriers are moved in the horizontal direction (parallel direction) with respect to the surface of the semiconductor substrate may be used. As shown in fig. 20, the FET circuit 300 of the eighth embodiment has an n-type FET and a p-type FET having a lateral vacuum channel on a p-type semiconductor substrate 41. The N-type FET has a gate 45, a source 43 and a drain 47 on a p-type semiconductor substrate 41, and the p-type FET has a gate 46, a source 44 and a drain 48 on an N-well 42.

The gate 45, the source 43, and the drain 47 of the n-type FET of the FET circuit 300 are respectively fin-shaped (fin) extending in a vertical direction with respect to the surface of the p-type semiconductor substrate 41. The fins of gate 45, source 43, and drain 47 may be formed using a portion of p-type semiconductor substrate 41, for example. The source electrode 43 and the drain electrode 47 are disposed opposite to each other with a vacuum interposed therebetween, and the distance between the source electrode 43 and the drain electrode 47 is, for example, 40nm to 60 nm. The space between the source 43 and the drain 47 is a vacuum channel space of the n-type FET. The gate electrode 45 faces both sides of the vacuum channel space of the n-type FET and is formed at a predetermined interval from the source electrode 43 and the drain electrode 47.

In the case of forming the fin-like source 43 of the n-type FET of the FET circuit 300 using a part of the p-type semiconductor substrate 41, it is preferable to introduce an n-type impurity into the source 43 to form an n + impurity diffusion layer, and form a metal such as Al on the surfaces of the gate electrode 45 and the drain electrode 47 as necessary.

The gate 46, the source 44, and the drain 48 of the p-type FET of the FET circuit 300 are fins extending in a direction perpendicular to the surface of the p-type semiconductor substrate 41, as in the case of the n-type FET. The fin may be formed using a portion of the p-type semiconductor substrate 41, for example. The source 44 and the drain 48 are disposed opposite to each other with a vacuum interposed therebetween, and the distance between the source 44 and the drain 48 is, for example, 40nm to 60 nm. The space between source 44 and drain 48 is the vacuum channel space of the p-type FET. The gate 46 faces both sides of the vacuum channel space of the p-type FET and is formed at a predetermined interval from the source 44 and the drain 48.

In the case of forming the fin-like source 44 of the p-type FET of the FET circuit 300 using a part of the p-type semiconductor substrate 41, it is preferable to introduce a p-type impurity into the source 44 to form a p + impurity diffusion layer, and form a metal such as Al on the surface of the gate 46 and the drain 48 as necessary.

In the above description, the gate electrode 45 was described as being disposed so as to face both sides of the vacuum channel space of the n-type FET and the gate electrode 46 as facing both sides of the vacuum channel space of the p-type FET, but they may be provided in the respective vacuum channel spaces. In this case, for example, an insulating film is preferably formed on the surfaces of the gate electrode 45 and the gate electrode 46 to suppress the charge carriers from being attracted by the gate electrode 45 and the gate electrode 46.

(principle of action)

The operation of the n-type FET of the FET circuit 300 will be described below. The n-type FET of the FET circuit 300 has the vacuum space between the source 43 and the drain 47 as the vacuum channel space as described above. Electrons that become charge carriers are released from the source 43 into the vacuum channel space, move in the lateral direction (parallel direction) with respect to the surface of the p-type semiconductor substrate 41 in the vacuum channel space, and reach the drain 47. The electrons are discharged into the vacuum channel space by applying a gate-source voltage V_GSSet to a predetermined voltage, and the movement after the release is performed by setting a source-drain voltage V_DSSet to a predetermined voltage. In the case of turning on the n-type FET of the FET circuit 300, for example, 0V may be applied to the source 43Voltage, for example +2V to the drain 47, and +1V to the gate 45.

The operation of the p-type FET of the FET circuit 300 will be described below. Holes, which become charge carriers in the p-type FET, are released from the source 44 into the vacuum channel space, move in the lateral direction (parallel direction) with respect to the surface of the p-type semiconductor substrate 41 in the vacuum channel space, and reach the drain 48. The release of holes into the vacuum channel space is performed by applying V as in the case of the n-type FET of the FET circuit 300_GSSet to a predetermined voltage, and the movement after release is performed by setting V to a predetermined voltage_DSIs performed at a predetermined voltage. When the p-type FET of the FET circuit 300 is on, a voltage of, for example, +2V may be applied to the source 44, a voltage of, for example, 0V may be applied to the drain 48, and a voltage of, for example, +1V may be applied to the gate 46.

As an example of a complementary FET circuit including a lateral channel FET, a case where the FET circuit 140 is a complementary inverter circuit will be described. As shown in fig. 20, in the FET circuit 300, the gate 45 of the n-type FET is connected to the gate 46 of the p-type FET. In addition, the drain 47 of the n-type FET is connected to the drain 48 of the p-type FET. The gate 45 of the n-type FET and the gate 46 of the p-type FET are connected to a voltage source of the complementary inverter circuit that supplies the input voltage. The output voltage of the complementary inverter circuit is output to the outside from the drain 47 of the n-type FET and the drain 48 of the p-type FET. The source 43 of the N-type FET is connected to a voltage source that can supply the GND voltage, and the source 44 and N-well 42 of the p-type FET are connected to a voltage source that can supply a positive voltage.

In the complementary inverter circuit operation, a GND voltage of, for example, 0V is applied to the source 43 of the N-type FET, and a positive voltage of, for example, +1V is applied to the source 44 and the N-well 42 of the p-type FET. Further, for example, GND voltage is applied to the p-type semiconductor substrate 41. In this state, by applying a positive voltage of, for example, +1V or a GND voltage of 0V as an input signal of the complementary inverter circuit to the gate 45 of the n-type FET and the gate 46 of the p-type FET, an output voltage as an output signal of the complementary inverter circuit is outputted from the drain 47 of the n-type FET and the drain 48 of the p-type FET to the outside.

The example shown in fig. 20 is an example of a case where the FET circuit 300 is a complementary inverter circuit, and various modifications can be made within the scope of the present invention. The wiring diagram of fig. 20 may be changed as necessary, and each voltage may be supplied via another voltage source, another wiring, or another circuit. The FET circuit 300 can be implemented by being modified to other complementary FET circuits, for example, a differential amplifier circuit having a plurality of n-type FETs and p-type FETs, an SRAM circuit, and the like. The input signal is not limited to a positive voltage of +2V or a voltage of 0V, and for example, a negative voltage may be applied instead of the voltage of 0V in order to improve the hole discharge efficiency from the source 44 of the p-type FET.

(Effect)

In the lateral vacuum channel FET of the present embodiment, the source and drain areas can be increased as compared with the vertical vacuum channel FET, and therefore the inter-source-drain current I can be increased_DSAnd (4) increasing. Further, since it is not necessary to insulate the source and the drain by an insulating film, the size and arrangement of the gate can be easily adjusted, and thus the degree of freedom in designing the FET is increased. Therefore, a semiconductor device having a high-performance complementary vacuum channel FET can be obtained.

In the first to eighth embodiments, the example in which the silicon substrate is used as the semiconductor substrate has been described, but the semiconductor substrate may be implemented using another semiconductor substrate such as GaAs, GaN, or the like.

Description of the symbols

1. 31: a p-type semiconductor substrate;

2. 32: a first insulating film;

3. 33: a gate electrode;

4. 34: a second insulating film;

5. 35: an opening part;

6. 36: n + impurity diffusion layer (source)

7. 37: a drain electrode;

8. 38: a back electrode;

9: an N well;

10: a p + impurity diffusion layer (source);

11: a sidewall insulating film;

12: supporting a substrate;

13: an embedded silicon oxide layer;

14: an n-type silicon active layer;

15: a P well;

16: an element isolation region;

17: a first cap layer;

18: a filler;

19: a second cap layer;

20: a cover opening part;

21: a cover layer;

22: a hollow part;

39: a third insulating film;

41: a p-type semiconductor substrate;

42: an N well;

43. 44: a source electrode;

45. 46: a gate electrode;

47. 48: a drain electrode;

100、120、130、150、200：FET；

110. 140, 300: an FET circuit.