阅读说明：本技术 可调式谐振器及其制造方法 (Tunable resonator and method of manufacturing the same ) 是由 吴明 唐兆云 赖志国 杨清华 王家友 于 2020-07-24 设计创作，主要内容包括：一种可调式谐振器及其制造方法,谐振器包括：谐振腔,在衬底中,至少包括中心的第一谐振腔和外围的第二谐振腔；第一堆叠结构,在第一谐振腔上,依次包括下电极第一部分、压电层第一部分和上电极第一部分；第二堆叠结构,在第二谐振腔上,依次包括下电极第二部分、压电层第二部分和上电极第二部分；第一绝缘层,在衬底上,位于下电极第一部分和下电极第二部分之间。依照本发明的可调式谐振器及其制造方法,在主谐振器外围增设副谐振器以主动地调节谐振状态,有利于提高器件集成度和效率。(A tunable resonator and a method of manufacturing the same, the resonator comprising: the resonant cavity is arranged in the substrate and at least comprises a first central resonant cavity and a second peripheral resonant cavity; the first stacked structure is arranged on the first resonant cavity and sequentially comprises a first lower electrode part, a first piezoelectric layer part and a first upper electrode part; the second stacked structure is arranged on the second resonant cavity and sequentially comprises a second lower electrode part, a second piezoelectric layer part and a second upper electrode part; a first insulating layer on the substrate between the first portion of the lower electrode and the second portion of the lower electrode. According to the adjustable resonator and the manufacturing method thereof, the auxiliary resonator is additionally arranged on the periphery of the main resonator to actively adjust the resonance state, so that the integration level and the efficiency of the device are improved.)

1. A tunable resonator, comprising:

the resonant cavity is arranged in the substrate and at least comprises a first central resonant cavity and a second peripheral resonant cavity;

the first stacked structure is arranged on the first resonant cavity and sequentially comprises a first lower electrode part, a first piezoelectric layer part and a first upper electrode part;

the second stacked structure is arranged on the second resonant cavity and sequentially comprises a second lower electrode part, a second piezoelectric layer part and a second upper electrode part;

a first insulating layer on the substrate between the first portion of the lower electrode and the second portion of the lower electrode.

2. The resonator ofclaim 1 further comprising a second insulating layer on the first portion ofthe piezoelectric layer and the second portion ofthe piezoelectric layer between the first portion ofthe upper electrode and the second portion ofthe upper electrode; preferably, the first portion of the piezoelectric layer and the second portion of the piezoelectric layer are connected or spaced apart by a second insulating layer.

3. The tunable resonator according to claim 1, wherein the first resonant cavity, the lower electrode first portion, the upper electrode first portion are polygonal, circular or elliptical in plan view; preferably, the size of the top of the first resonant cavity is larger than the size of the first part of the lower electrode or the first part of the upper electrode, and optionally, the size of the top of the second resonant cavity is larger than the size of the second part of the lower electrode or the second part of the upper electrode; preferably, the first portion of the lower electrode is edge aligned with the first portion of the upper electrode, and the second portion of the lower electrode is edge aligned with the second portion of the upper electrode.

4. The tunable resonator of claim 1, wherein a different signal is applied to the second stacked structure than the first stacked structure to adjust a resonance state of the resonator, the resonance state comprising at least one of amplitude, frequency, phase, or a combination thereof.

5. The tunable resonator according to any one of claims 1 to 4, wherein the substrate material is Si, SOI, Ge, GeOI, compound semiconductor; optionally, the materials of the first and second parts of the piezoelectric layer are ZnO, AlN, BST (barium strontium titanate), BT (barium titanate), PZT (lead zirconate titanate), PBLN (lead barium lithium niobate), PT (lead titanate), further preferably the piezoelectric material is doped with rare earth elements; optionally, the material of the first or second insulating layer is a nitride, such as silicon nitride, silicon oxynitride, aluminum nitride, boron nitride; optionally, the material of any one of the lower electrode first portion, the lower electrode second portion, the upper electrode first portion, and the upper electrode second portion is a simple metal or a metal alloy selected from Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr, Fe, Mg, or a conductive oxide or a conductive nitride of these metals, and any combination of the above materials.

6. A tunable resonator manufacturing method, comprising:

forming a sacrificial layer in the substrate, wherein the sacrificial layer comprises a first sacrificial layer pattern in the center and a second sacrificial layer pattern on the periphery;

forming a lower electrode layer on the sacrificial layer, including a lower electrode first portion on the first sacrificial layer pattern and a lower electrode second portion on the second sacrificial layer pattern;

forming a first insulating layer between the lower electrode first portion and the lower electrode second portion;

forming a piezoelectric layer on the first insulating layer and the lower electrode layer, including at least a first portion of the piezoelectric layer over the first sacrificial layer pattern and a second portion of the piezoelectric layer over the second sacrificial layer pattern;

forming an upper electrode layer on the piezoelectric layer, including an upper electrode first portion on the piezoelectric layer first portion and an upper electrode second portion on the piezoelectric layer second portion;

the sacrificial layer is removed, leaving a resonant cavity in the substrate, including a central first resonant cavity and a peripheral second resonant cavity.

7. The tunable resonator manufacturing method according to claim 6, further comprising, after forming the upper electrode layer, forming a second insulating layer at least between the first portion of the upper electrode and the second portion of the upper electrode; preferably, the first portion of the piezoelectric layer and the second portion of the piezoelectric layer are connected or spaced apart by a second insulating layer.

8. The tunable resonator manufacturing method according to claim 6, wherein the first resonant cavity, the lower electrode first portion, and the upper electrode first portion are polygonal, circular, or elliptical in plan view; preferably, the size of the top of the first resonant cavity is larger than the size of the first part of the lower electrode or the first part of the upper electrode, and optionally, the size of the top of the second resonant cavity is larger than the size of the second part of the lower electrode or the second part of the upper electrode; preferably, the first portion of the lower electrode is edge aligned with the first portion of the upper electrode, and the second portion of the lower electrode is edge aligned with the second portion of the upper electrode.

9. The tunable resonator fabricating method according to claim 6, wherein the substrate material is Si, SOI, Ge, GeOI, compound semiconductor; optionally, the materials of the first and second parts of the piezoelectric layer are ZnO, AlN, BST (barium strontium titanate), BT (barium titanate), PZT (lead zirconate titanate), PBLN (lead barium lithium niobate), PT (lead titanate), further preferably the piezoelectric material is doped with rare earth elements; optionally, the material of the first or second insulating layer is a nitride, such as silicon nitride, silicon oxynitride, aluminum nitride, boron nitride; optionally, the material of any one of the lower electrode first portion, the lower electrode second portion, the upper electrode first portion, and the upper electrode second portion is a simple metal or a metal alloy selected from Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr, Fe, Mg, or a conductive oxide or a conductive nitride of these metals, and any combination of the above materials; optionally, the sacrificial layer material is an oxide, such as boron doped silicon oxide (BSG), phosphorous doped silicon oxide (PSG), undoped silicon oxide (USG), porous silicon oxide.

10. The tunable resonator manufacturing method according to claim 7, further comprising, after forming the upper electrode layer and before removing the sacrificial layer, etching the piezoelectric layer between the first portion of the upper electrode and the second portion of the upper electrode to form an opening exposing the substrate, and forming a second insulating layer on the upper electrode layer and on a bottom and a sidewall of the opening.

Technical Field

The present invention relates to tunable resonators and methods for fabricating the same, and more particularly, to a tunable resonator and a method for fabricating the same.

Background

In wireless communication, the rf filter is used as an intermediary for filtering signals with specific frequencies, and is used to reduce signal interference in different frequency bands, and to implement functions such as image cancellation, spurious filtering, and channel selection in the wireless transceiver. With the deployment of 4GLTE networks and the growth of the market, the design of the radio frequency front end is developing towards miniaturization, low power consumption and integration, and the market has higher and higher requirements on filtering performance. Because the film bulk acoustic resonator (FBAR, also called bulk acoustic wave, or "BAW") has the characteristics of small size, high working frequency, low power consumption, high quality factor (Q value), direct output of frequency signals, compatibility with CMOS process, etc., it has become an important device in the field of radio frequency communication and is widely used at present.

FBAR is a thin film device with a sandwich structure of electrodes-piezoelectric film-electrodes fabricated on a substrate material. The FBAR has a structure of a cavity type, a bragg reflection type (SMR), and a back surface etching type. The Q value of the cavity type FBAR is higher than that of the SMR type FBAR, the loss is small, and the electromechanical coupling coefficient is high; compared with the back etching FBAR, the back etching FBAR does not need to remove a large-area substrate, and has higher mechanical strength. Therefore, the cavity FBAR is the first choice for integration in CMOS devices.

Conventionally, after the resonant cavity is prepared in the substrate, the resonant frequency of the device is determined accordingly. When it is necessary to apply to different frequencies or a wide range of frequency bands, in order to improve the filtering accuracy, a large number of resonant cavities of different sizes must be made on the same substrate, which unnecessarily increases the size of the system, and the system utilization is low when some resonators are operated while most other resonators are in an idle state.

Disclosure of Invention

It is therefore an object of the present invention to provide a tunable resonator and a method for manufacturing the same that overcomes the above technical obstacles.

The invention provides an adjustable resonator, comprising:

the resonant cavity is arranged in the substrate and at least comprises a first central resonant cavity and a second peripheral resonant cavity;

the first stacked structure is arranged on the first resonant cavity and sequentially comprises a first lower electrode part, a first piezoelectric layer part and a first upper electrode part;

the second stacked structure is arranged on the second resonant cavity and sequentially comprises a second lower electrode part, a second piezoelectric layer part and a second upper electrode part;

a first insulating layer on the substrate between the first portion of the lower electrode and the second portion of the lower electrode.

Further comprising a second insulating layer on the first portion of the piezoelectric layer and the second portion of the piezoelectric layer between the first portion of the upper electrode and the second portion of the upper electrode; preferably, the first portion of the piezoelectric layer and the second portion of the piezoelectric layer are connected or spaced apart by a second insulating layer.

The first resonant cavity, the first part of the lower electrode and the first part of the upper electrode are polygonal, circular or elliptical in plan view; preferably, the size of the top of the first resonant cavity is larger than the size of the first part of the lower electrode or the first part of the upper electrode, and optionally, the size of the top of the second resonant cavity is larger than the size of the second part of the lower electrode or the second part of the upper electrode; preferably, the first portion of the lower electrode is edge aligned with the first portion of the upper electrode, and the second portion of the lower electrode is edge aligned with the second portion of the upper electrode.

Wherein a different signal is applied to the second stacked structure than the first stacked structure to adjust a resonance state of the resonator, the resonance state including at least one of an amplitude, a frequency, a phase, or a combination thereof.

Wherein the substrate material is Si, SOI, Ge, GeOI, compound semiconductor; optionally, the materials of the first and second parts of the piezoelectric layer are ZnO, AlN, BST (barium strontium titanate), BT (barium titanate), PZT (lead zirconate titanate), PBLN (lead barium lithium niobate), PT (lead titanate), further preferably the piezoelectric material is doped with rare earth elements; optionally, the material of the first or second insulating layer is a nitride, such as silicon nitride, silicon oxynitride, aluminum nitride, boron nitride; optionally, the material of any one of the lower electrode first portion, the lower electrode second portion, the upper electrode first portion, and the upper electrode second portion is a simple metal or a metal alloy selected from Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr, Fe, Mg, or a conductive oxide or a conductive nitride of these metals, and any combination of the above materials.

The invention also provides a manufacturing method of the adjustable resonator, which comprises the following steps:

forming a sacrificial layer in the substrate, wherein the sacrificial layer comprises a first sacrificial layer pattern in the center and a second sacrificial layer pattern on the periphery;

forming a lower electrode layer on the sacrificial layer, including a lower electrode first portion on the first sacrificial layer pattern and a lower electrode second portion on the second sacrificial layer pattern;

forming a first insulating layer between the lower electrode first portion and the lower electrode second portion;

forming a piezoelectric layer on the first insulating layer and the lower electrode layer, including at least a first portion of the piezoelectric layer over the first sacrificial layer pattern and a second portion of the piezoelectric layer over the second sacrificial layer pattern;

forming an upper electrode layer on the piezoelectric layer, including an upper electrode first portion on the piezoelectric layer first portion and an upper electrode second portion on the piezoelectric layer second portion;

the sacrificial layer is removed, leaving a resonant cavity in the substrate, including a central first resonant cavity and a peripheral second resonant cavity.

Forming the upper electrode layer further includes, at least, forming a second insulating layer between the upper electrode first portion and the upper electrode second portion; preferably, the first portion of the piezoelectric layer and the second portion of the piezoelectric layer are connected or spaced apart by a second insulating layer.

The first resonant cavity, the first part of the lower electrode and the first part of the upper electrode are polygonal, circular or elliptical in plan view; preferably, the size of the top of the first resonant cavity is larger than the size of the first part of the lower electrode or the first part of the upper electrode, and optionally, the size of the top of the second resonant cavity is larger than the size of the second part of the lower electrode or the second part of the upper electrode; preferably, the first portion of the lower electrode is edge aligned with the first portion of the upper electrode, and the second portion of the lower electrode is edge aligned with the second portion of the upper electrode.

Wherein the substrate material is Si, SOI, Ge, GeOI, compound semiconductor; optionally, the materials of the first and second parts of the piezoelectric layer are ZnO, AlN, BST (barium strontium titanate), BT (barium titanate), PZT (lead zirconate titanate), PBLN (lead barium lithium niobate), PT (lead titanate), further preferably the piezoelectric material is doped with rare earth elements; optionally, the material of the first or second insulating layer is a nitride, such as silicon nitride, silicon oxynitride, aluminum nitride, boron nitride; optionally, the material of any one of the lower electrode first portion, the lower electrode second portion, the upper electrode first portion, and the upper electrode second portion is a simple metal or a metal alloy selected from Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr, Fe, Mg, or a conductive oxide or a conductive nitride of these metals, and any combination of the above materials; optionally, the sacrificial layer material is an oxide, such as boron doped silicon oxide (BSG), phosphorous doped silicon oxide (PSG), undoped silicon oxide (USG), porous silicon oxide.

After forming the upper electrode layer and before removing the sacrificial layer, etching the piezoelectric layer between the first part of the upper electrode and the second part of the upper electrode to form an opening exposing the substrate, and forming a second insulating layer on the upper electrode layer and on the bottom and the side wall of the opening.

According to the adjustable resonator and the manufacturing method thereof, the auxiliary resonator is additionally arranged on the periphery of the main resonator to actively adjust the resonance state, so that the integration level and the efficiency of the device are improved.

The stated objects of the invention, as well as other objects not listed here, are met within the scope of the independent claims of the present application. Embodiments of the invention are defined in the independent claims, with specific features being defined in the dependent claims.

Drawings

The technical solution of the present invention is explained in detail below with reference to the accompanying drawings, in which:

FIG. 1 shows a cross-sectional view of a resonator fabrication process according to an embodiment of the present invention;

FIG. 2 shows a cross-sectional view of a resonator fabrication process according to an embodiment of the present invention;

FIG. 3 shows a cross-sectional view of a resonator fabrication process according to an embodiment of the present invention;

FIG. 4 shows a cross-sectional view of a resonator fabrication process according to an embodiment of the present invention;

FIG. 5 shows a cross-sectional view of a resonator fabrication process according to an embodiment of the present invention;

FIG. 6 shows a cross-sectional view of a resonator fabrication process according to an embodiment of the present invention;

FIG. 7 shows a cross-sectional view of a resonator fabrication process according to an embodiment of the present invention;

FIG. 8 shows a cross-sectional view of a resonator fabrication process according to an embodiment of the present invention;

FIG. 9 shows a cross-sectional view of a resonator fabrication process according to an embodiment of the present invention; and

figure 10 shows a plan view of a resonator top electrode in accordance with an embodiment of the present invention.

Detailed Description

The features and technical effects of the technical scheme of the invention are described in detail below with reference to the accompanying drawings and in combination with exemplary embodiments, and a resonator and a manufacturing method thereof are disclosed, which are beneficial to improving the integration level and efficiency of devices. It is noted that like reference numerals refer to like structures and that the terms "first", "second", "upper", "lower", and the like as used herein may be used to modify various device structures. These modifications do not imply a spatial, sequential, or hierarchical relationship to the structures of the modified devices unless specifically stated.

As shown in fig. 1, a sacrificial layer 2 is formed in a substrate 1. The substrate 1 is provided as a material which may be bulk Si or silicon-on-insulator (SOI) or bulk Ge, GeOI for compatibility with CMOS processes and integration with other digital, analog circuits, or may be a compound semiconductor such as GaN, GaAs, SiC, InP, GaP, etc. for MEMS, optoelectronic devices, power devices, and further preferably, the substrate 1 is a single crystal material. The substrate 1 is etched to form a plurality of cavities (not shown in figure 1) and a sacrificial layer 2 is deposited to fill them. The etching process is preferably anisotropic dry etching or wet etching, such as reactive ion etching with a fluorocarbon-based etching gas, or wet etching with TMAH. The deposition process is a low temperature process (deposition temperature is lower than 500 ℃, preferably 100 to 400 ℃) such as LPCVD, APCVD, PECVD, etc., and the material of the sacrificial layer 2 is a silicon oxide-based material, such as boron doped silicon oxide (BSG), phosphorous doped silicon oxide (PSG), undoped silicon oxide (USG), porous silicon oxide, etc., so that the residual thermal stress in the substrate 1 can be reduced, and the subsequent etching removal speed can be increased to save time cost. As shown in fig. 1, the sacrificial layer 2 includes at least two portions, i.e., a first portion 2a for filling the main cavity and a second portion 2b for filling the sub-cavity at the periphery of the main cavity. Preferably, the sacrificial layer 2 is treated with a CMP planarization process until the surface of the substrate 1 is exposed. In a preferred embodiment of the present invention, the central portion of the cavity formed by etching the substrate 1, i.e. the projection of the main resonant cavity in plan view, is polygonal (e.g. quadrilateral, pentagonal, hexagonal, octagonal, etc.), circular, elliptical, etc., while the peripheral portion, i.e. the projection of the sub-resonant cavity in plan view is in a similar pattern concentric with the main resonant cavity, so that a portion of the substrate 1S sandwiched between the main and sub-resonant cavities in a ring shape is used as a subsequent mechanical support or isolation structure, and the first portion 2a and the second portion 2b of the filled sacrificial layer also have corresponding features.

As shown in fig. 2, a patterned lower electrode 3 is formed on a substrate 1. The conductive material layer is formed by magnetron sputtering, thermal evaporation, MOCVD or other processes, and is made of a single metal or a metal alloy such as Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr, Fe, Mg or the like, or a conductive oxide, a conductive nitride of these metals, or any combination of these materials. Preferably, before forming the conductive material layer, a seed layer (not shown) is further formed on the substrate 1 and the sacrificial layer 2 to improve the crystal orientation of the electrode layer and the overlying functional layer. In a preferred embodiment of the present invention, the seed layer is AlN, HfN, HfAlN, TiN, TaN, etc., and preferably can also be used as a barrier layer for preventing the metal material of the lower electrode from migrating downward to avoid affecting the interface state between the top of the resonant cavity and the film layer below. The conductive material layer is then patterned using a photo-etching process such as spin-on resist, exposure and development to form a resist pattern, and etching the conductive material layer using the resist pattern as a mask to form the lower electrode 3 shown in fig. 2. The lower electrode 3 includes at least a first portion 3a at the center and a second portion 3b at the periphery. The lower electrode first portion 3a has a polygonal (e.g., quadrilateral, pentagonal, hexagonal, octagonal, etc.), circular, elliptical, etc. projection in plan view as the sacrificial layer first portion 2a, the main resonator, and the second portion 3b is a ring-shaped structure concentric with the first portion 3a with a gap therebetween. It should be noted that, in order to ensure sufficient insulation between the lower electrodes of the main resonator and the adjusting sub-resonator, the distance between the peripheral second portion 3b and the central first portion 3a is at least greater than the width of the top of the substrate support structure 1S sandwiched between the main and sub-resonators. Preferably, the edge of the first portion 3a of the lower electrode is set back from the edge of the first portion 2a of the sacrificial layer by 0.1-10 microns, preferably 0.05-5 microns, most preferably 1-3 microns. Further or similarly, the edge of the second portion 3b of the lower electrode is also set back from the edge of the second portion 2b of the sacrificial layer by the same distance. After the patterned lower electrode 3 is formed, the photoresist pattern is removed by wet etching.

As shown in fig. 3, an insulating layer 4 is filled between the lower electrode patterns. An insulating dielectric material is filled between the first portion 3a and the second portion 3b of the lower electrode layer by, for example, LPCVD, PECVD, spin coating, spray coating, screen printing, etc., thereby constituting an annular insulating layer pattern 4. The insulating layer 4 is made of a different material than the sacrificial layer 2 so as to avoid excessive erosion during subsequent removal of the sacrificial layer 2 to form a resonant cavity. In a preferred embodiment of the present invention, the insulating layer 4 material is a nitride, such as silicon nitride, silicon oxynitride, aluminum nitride, boron nitride, or the like. Preferably, the insulating layer is processed until the lower electrode patterns 3a and 3b are exposed using a planarization process of etch-back or CMP.

As shown in fig. 4, a piezoelectric layer 5 is formed on the lower electrode patterns 3a, 3b and the insulating layer 4. The piezoelectric layer 5 is formed, for example, by PECVD, UHVCVD, HDPCVD, MOCVD, MBE, ALD, magnetron sputtering, thermal evaporation, etc., and is preferably made of a material different from that of the insulating layer 4. In a preferred embodiment of the present invention, the material of the piezoelectric layer 5 is, for example, a piezoelectric ceramic material such as ZnO, AlN, BST (barium strontium titanate), BT (barium titanate), PZT (lead zirconate titanate), PBLN (lead barium lithium niobate), PT (lead titanate), etc., and preferably, the piezoelectric layer 5 is doped with a rare earth element such as any one including scandium (Sc), yttrium (Y), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb) and lutetium (Lu), and a combination thereof, to improve the piezoelectric coefficient. In a preferred embodiment of the invention the piezoelectric layer 5 is doped with Sc, or Sc mixed with Yb, or Sc mixed with Gd, or Sc, Yb, Sm mixed. Subsequently, an upper conductive material layer 6 is formed on the piezoelectric layer 5. The preparation process and material of the conductive material layer 6 are the same as those of the lower electrode layer 3, and are not described in detail herein.

As shown in fig. 5, the conductive material layer 6 is patterned to form an upper electrode first portion 6a and an upper electrode second portion 6 b. Spin-coating a photoresist, forming a photoresist pattern through an exposure and development process, and etching the conductive material layer 6 using the photoresist pattern as a mask to form a first portion 6a of the upper electrode at the center and a second portion 6b of the upper electrode at the periphery in a ring shape. Preferably, the edges of the upper electrode first portions 6a are aligned with the edges of the lower electrode first portions 3a and the edges of the upper electrode second portions 6b are aligned with the edges of the lower electrode second portions 3b, leaving a gap between the first and second portions 6a, 6b that is aligned with the insulating layer 4 between the lower electrode patterns 3a, 3 b. Thereafter, the photoresist pattern is removed preferably by a wet etching process.

As shown in fig. 6, a second insulating layer 7 is formed on the piezoelectric layer 5 and the upper electrode pattern 6a/6 b. The material and process of the second insulating layer 7 are the same as or similar to those of the insulating layer 4, and are not described herein again.

As shown in fig. 7, the sacrificial layer pattern 2 is removed, leaving a resonant cavity in the substrate 1. By being arranged atRelease holes (not shown) in the periphery of the device and a wet etchant is applied to remove the sacrificial layer pattern. For the silicon oxide-based material, HF-based etchant such as dHF (diluted HF), dBOE (slow release etchant, HF and NH) is used₄F) is removed, leaving a plurality of resonant cavities including at least a first portion 1c at the center and a second portion 1 c' of a ring shape at the periphery. As previously shown, the width of the insulating layer 4 is greater than the width of the top of the support structure 1S, and the widths of the first portion 3a and the second portion 3b of the lower electrode are smaller than those of the sacrificial layer patterns 2a and 2b, so that the width of the main cavity 1c is greater than that of the first portion 3a of the lower electrode, and the width of the sub cavity 1 c' is greater than that of the second portion 3b of the lower electrode.

As shown in fig. 8, the second insulating layer 7 is processed by a planarization process such as etching back, CMP, etc. until the upper electrode patterns 6a, 6b are exposed. The resulting resonator structure is shown in fig. 8, and includes a substrate 1, a first resonant cavity portion 1c and a second resonant cavity portion 1c 'in the substrate 1, where the first lower electrode portion 3a, the piezoelectric layer 5 and the first upper electrode portion 6a above the first resonant cavity portion 1c constitute a main resonator, and the second lower electrode portion 3b, the piezoelectric layer 5 and the second upper electrode portion 6b above the second resonant cavity portion 1 c' constitute a sub-resonator. The distribution shapes of the upper electrodes 6a/6b and the second insulating layer 7 are as shown in fig. 10, and are the same as, conformal to, or similar to the lower electrodes 3a/3b and the insulating layer patterns 4, and are all concentric polygonal, circular or elliptical structures, that is, the second insulating layer 7 is sandwiched between the central portion of the upper electrode, that is, the first portion 6a, and the peripheral second portion 6b, and the second portion 6b has at least one notch to accommodate the lead-out portion of the first portion 6a to pass through under the second insulating layer 7 to achieve external electrical connection. During the operation of the device, the secondary resonator at the periphery of the main resonator generates different vibration with the main resonator by applying signals different from the main resonator, such as at least one of amplitude, frequency and phase difference, to the electrodes (3b and 6b) of the secondary resonator, and two mechanical waves with different states are superposed, so that the final signal waveform is changed. Therefore, the vibration state of the secondary resonator can be flexibly changed by controlling the input waveform of the secondary resonator in real time, the working state of the whole resonator is further influenced, the frequency response of the whole resonator system is adjusted when needed, the chip area is saved, the integration level is improved, the product cost is reduced, and the utilization rate of devices is improved.

In another preferred embodiment of the present invention, as shown in fig. 9, the piezoelectric layers 5 are not connected as a whole, but penetrate through the support structure 1S up to the surface of the substrate 1 by the second insulating layer 7, thereby improving the insulating and isolating effect between the electrodes of the main resonator and the sub-resonator, and preventing the lateral crosstalk of signals between the upper and lower electrodes of different resonators. The manufacturing process is basically the same as that shown in fig. 1 to 8, except that in the process step shown in fig. 5, after the patterned upper electrodes 6a and 6b are etched, the piezoelectric layer 5 is further etched by using the photoresist pattern or the upper electrode pattern as a mask until the supporting structure 1S on the surface of the substrate 1 is exposed, and in the process step shown in fig. 6, the second insulating layer 7 is filled by using the PECVD, HDPCVD, magnetron sputtering and other processes with good step coverage. The resulting device structure is similar to that shown in fig. 8, except that a second insulating layer 7 is sandwiched not only between the upper electrode first portion 6a and the second portion 6b, but also through the piezoelectric layer 5 to the substrate surface, and between the lower electrode first portion 3a and the second portion 3 b.

According to the adjustable resonator and the manufacturing method thereof, the auxiliary resonator is additionally arranged on the periphery of the main resonator to actively adjust the resonance state, so that the integration level and the efficiency of the device are improved.

While the invention has been described with reference to one or more exemplary embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the disclosure without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the disclosed device structure and its method of manufacture will include all embodiments falling within the scope of the present invention.