阅读说明：本技术 倍增寄存器结构以及包括该倍增寄存器结构的emccd (Multiplication register structure and EMCCD (electron-multiplying charge coupled device) comprising same ) 是由 白雪平 杨洪 郑渝 曲鹏程 于 2020-06-19 设计创作，主要内容包括：本发明属于半导体器件技术领域,涉及一种能够提高EMCCD响应线性度的结构,具体涉及倍增寄存器结构以及包括该倍增寄存器结构的EMCCD；所述倍增寄存器结构,包括衬底和位于衬底之上的埋沟；在埋沟上覆盖有栅介质,在栅介质上形成有第一电极Ф1、第二电极Фdc、第三电极Фem和第四电极Ф3；这四个电极依次对应为第一转移相、直流相、倍增相以及第二转移相；将倍增相对应的埋沟划分为倍增埋沟和电荷埋沟,所述倍增埋沟用于电荷倍增；所述电荷埋沟用于存储倍增后的电荷；本发明提供了倍增寄存器结构以及EMCCD,将倍增寄存器分成两部分,一部分用来倍增,一部分用来存储电荷,这样可以有效避免倍增电场的降低。(The invention belongs to the technical field of semiconductor devices, and relates to a structure capable of improving the response linearity of an EMCCD (electron-multiplying charge coupled device), in particular to a multiplication register structure and an EMCCD (electron-multiplying charge coupled device) comprising the multiplication register structure; the multiplication register structure comprises a substrate and a buried channel positioned above the substrate; a gate medium is covered on the buried channel, and a first electrode phi 1, a second electrode phi dc, a third electrode phi em and a fourth electrode phi 3 are formed on the gate medium; the four electrodes are sequentially corresponding to a first transfer phase, a direct current phase, a multiplication phase and a second transfer phase; dividing the buried channel corresponding to multiplication into a multiplication buried channel and a charge buried channel, wherein the multiplication buried channel is used for charge multiplication; the charge buried channel is used for storing multiplied charges; the invention provides a multiplication register structure and an EMCCD (electron-multiplying charge coupled device), wherein the multiplication register is divided into two parts, one part is used for multiplication, and the other part is used for storing charges, so that the reduction of a multiplication electric field can be effectively avoided.)

1. A multiplication register structure for improving EMCCD response linearity comprises a substrate and a buried channel positioned on the substrate; a gate medium is covered on the buried channel, and a first electrode phi 1, a second electrode phi dc, a third electrode phi em and a fourth electrode phi 3 are formed on the gate medium; the four electrodes are sequentially corresponding to a first transfer phase, a direct current phase, a multiplication phase and a second transfer phase; the method is characterized in that the buried channel is divided into a first buried channel, a second buried channel, a third buried channel and a fourth buried channel corresponding to each electrode; dividing a third buried channel corresponding to the multiplication phase down of the third electrode Φ em into a multiplication buried channel and a charge buried channel, the multiplication buried channel being used for charge multiplication; the charge buried channel is used for storing the multiplied charges, and the depth of the charge buried channel is larger than that of the multiplication buried channel.

2. The multiplication register structure for improving response linearity of an EMCCD as claimed in claim 1, wherein said substrate is a P-type substrate, said buried channel is an N-type buried channel or said substrate is an N-type substrate, said buried channel is a P-type buried channel.

3. The multiplication register structure for improving the response linearity of the EMCCD of claim 1, wherein the concentration of the multiplication buried channel is consistent with the concentration of other buried channels, the concentration of the charge buried channel is slightly higher than the concentration of the multiplication buried channel, wherein the other buried channels comprise a first buried channel, a second buried channel and a fourth buried channel, and the concentration of the charge buried channel is 1/3-1 times higher than the concentration of the multiplication buried channel.

4. The multiplication register structure for improving the response linearity of the EMCCD of claim 3, wherein phosphorus is added at the charge buried channel for improving the charge buried channel concentration.

5. An EMCCD for improving response linearity, comprising a storage region, a photosensitive region, a horizontal register and a sense amplifier, wherein a plurality of multiplication register structures according to any one of claims 1 to 4 are installed between the horizontal register and the sense amplifier.

Technical Field

The invention belongs to the technical field of semiconductor devices, relates to a structure capable of improving the response linearity of an EMCCD, and particularly relates to a multiplication register structure and an EMCCD comprising the multiplication register structure.

Background

The avalanche multiplication effect is common in semiconductor devices, in silicon semiconductors, when the electron passage is higher than 10⁵Avalanche multiplication occurs at a V/cm electric field. A common Charge-coupled Device (CCD) applies a 10V driving voltage to generate 10V⁵The avalanche multiplication effect exists in the ordinary CCD due to the electric field of V/cm, and the avalanche multiplication effect is not easy to be found by people due to the low multiplication rate. An Electron-Multiplying CCD (EMCCD for short) is an Electron-Multiplying CCD in which a transfer electrode is applied with a high voltage to cause avalanche multiplication of carriers, and the multiplication rate is higher than that of a general CCD, thereby realizing Electron multiplication.

The EMCCD is different from the ordinary CCD in that a series of multiplication registers are added between a horizontal register and a read-out amplifier, signal electrons realize multiplication and amplification in the multiplication registers, and infinitesimal light signals are amplified by the multiplication registers and then read by the read-out amplifier, so that the detection sensitivity of a CCD device is not limited by the noise of the read-out amplifier any more, and the detection sensitivity of the CCD device is improved. The multiplication register realizes multiplication and amplification of signal electrons by using the 'impact ionization' effect of charges, so that the EMCCD technology is also called as 'on-chip gain' technology and is an all-solid-state micro-light imaging device in the true sense.

The EMCCD multiplication register structure is shown in fig. 1. The electrodes phi 1 and phi 3 are driven by a standard amplitude clock (about 10V), phi dc is a direct current phase (direct current level is about 2V), the voltage added by phi 2 is much higher than the voltage only used for transferring charges (about 40-50V), and due to the huge voltage difference between phi 2 and phi dc, huge electric field intensity is generated between phi 2 and phi dc, so that electrons generate an impact ionization effect in the transfer process, also called an avalanche multiplication effect, and new electrons are generated, namely the multiplication or gain is generated.

The potential distribution when the multiplication register is multiplied is shown in FIG. 2, the huge voltage difference between the phase phi 2 and the direct current phase phi dc is multiplied, and the huge electric field intensity is generated to ensure thatElectrons transit from the valence band to the conduction band and "impact ionization effect" occurs during charge transfer in a CCD, the ionization coefficient (also called the ionization rate) being the inverse of the average distance that an electron-hole pair needs to travel to generate a new electron-hole pair due to impact ionization when the electron or hole is accelerated along the direction of the electric field, the ionization rate α_nIs dependent on the magnitude of the multiplication electric field, as shown in equation (1) below:

α_n＝A_nexp(-b_n/E) (1)

where An, bn are empirical values, the multiplication electric field E is represented by the following formula (2):

E＝ΔV/w (2)

w is the multiplied electric field width, and DeltaV is the buried channel potential difference between the faim and the faidc.

The number of electrons generated in the multiplication electric field region is represented by the following formula (3):

dn(x)/dx＝α_n(x)n(x) (3)

α_n(x) Is the ionization rate at x, and n (x) is the number of electrons at x.

The gain g in the region with the multiplication electric field width W is:

substituting formula (2) and formula (1) of the multiplied electric field E into formula (5) of gain obtains formula of gain and potential difference:

according to the CCD buried channel potential theory, Δ V is the potential difference between the faim phase and the faic phase buried channel, and is influenced by the quantity of filling electrons under the multiplication phase, and as the electrons are continuously filled under the multiplication phase, Δ V gradually decreases, and the more the number of filling electrons increases, the more Δ V decreases, as shown in FIG. 3. Accordingly, Δ V decreases, and the multiplication electric field decreases, and the gain decreases accordingly.

Electrons in the same charge packet pass through the multiplication register, are multiplied by the electric charge of the multiplication electric field and then are stored in the multiplication register, so that the multiplication electric field is reduced, the gain of the electric charge passing through the multiplication electric field is reduced, and the multiplication multiples of the successively multiplied electrons in the same charge packet are different. For the same multiplication voltage, the larger the charge packet, the larger the multiplication factor difference. The larger the multiplication voltage is, the higher the multiplication factor is, and the larger the electric field reduction degree is after the multiplication of the charge packet is, the larger the multiplication factor difference is. Therefore, the larger the charge packet before multiplication, the larger the gain factor, and the worse the device response nonlinearity.

Disclosure of Invention

Due to the instability of gain, the response linearity of the device is obviously reduced, and the application of the device in the aspect of accurate measurement is seriously influenced, such as the fields of photon counting, spectrum observation, rapid photometry and the like; in order to overcome the problem of instability of device gain and improve the response linearity of the EMCCD, the invention provides a multiplication register structure and the EMCCD comprising the multiplication register structure.

In a first aspect of the invention, the invention provides a multiplication register structure for improving response linearity of an EMCCD, which comprises a substrate and a buried channel positioned above the substrate; a gate medium is covered on the buried channel, and a first electrode phi 1, a second electrode phi dc, a third electrode phi em and a fourth electrode phi 3 are formed on the gate medium; the four electrodes are sequentially corresponding to a first transfer phase, a direct current phase, a multiplication phase and a second transfer phase; dividing the buried channel into a corresponding first buried channel, a second buried channel, a third buried channel and a fourth buried channel according to each electrode; dividing a third buried channel corresponding to the multiplication phase down of the third electrode Φ em into a multiplication buried channel and a charge buried channel, the multiplication buried channel being used for charge multiplication; the charge buried channel is used for storing the multiplied charges, and the depth of the charge buried channel is larger than that of the multiplication buried channel.

Further, the substrate is a P-type substrate, and the buried channel is an N-type buried channel.

Optionally, the substrate is an N-type substrate, and the buried trench is a P-type buried trench.

Further, the concentration of the multiplication buried channel is consistent with the concentration of other buried channels, the concentration of the charge buried channel is slightly higher than the concentration of the multiplication buried channel, and the other buried channels comprise a first buried channel, a second buried channel and a fourth buried channel.

Preferably, the concentration of the charge buried channel is 1/3 to 1 times higher than the multiplication buried channel concentration.

Optionally, the multiplication buried channel in the multiplication phase is set to N-normal concentration, the charge buried channel in the multiplication phase is set to N + phosphorus injection, and the concentration of the charge buried channel is slightly higher than that of the whole buried channel.

In a second aspect of the present invention, the present invention further provides an EMCCD for improving response linearity, including a storage region, a photosensitive region, a horizontal register, and a sense amplifier, wherein a plurality of the above-mentioned multiplication register structures are installed between the horizontal register and the sense amplifier, and the plurality of multiplication register structures are connected in series.

The invention has the beneficial effects that:

the original multiplication phase of the multiplication register is divided into two parts, wherein one part is used for normal multiplication, and the other part is used for storing charges; the normal multiplication can effectively utilize the multiplication electric field to multiply the charges; the stored charges can store a large amount of multiplied charges; since the electric charges of the multiplication buried channel, i.e., the multiplication electric field, are transferred into the charge buried channel, the total amount of electric charges in the multiplication buried channel is substantially in a stable state; therefore, the multiplied electron multiplication multiples in the same charge packet are not different due to the sequence of multiplication, so that the multiplied electric field is reduced; the invention effectively avoids the great reduction of the multiplication electric field, ensures the stability of the gain and improves the response linearity.

Drawings

FIG. 1 is a diagram of a conventional multiplier register structure;

FIG. 2 is a schematic diagram of potential distribution during multiplication of a conventional multiplication register structure;

FIG. 3 is a diagram illustrating the potential distribution of a conventional multiplication register structure after filling the multiplication phase with electrons;

FIG. 4 is a diagram of a multiplication register structure of the present invention;

FIG. 5 is a diagram of the buried channel potential profile of the multiplication register of the present invention;

fig. 6 shows an EMCCD structure according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

FIG. 4 is a multiplication register structure for improving the response linearity of an EMCCD employed in the present invention, including a substrate and a buried channel located above the substrate; a gate medium is covered on the buried channel, and a first electrode phi 1, a second electrode phi dc, a third electrode phi em and a fourth electrode phi 3 are formed on the gate medium; the four electrodes are sequentially corresponding to a first transfer phase, a direct current phase, a multiplication phase and a second transfer phase; dividing the buried channel into a corresponding first buried channel, a second buried channel, a third buried channel and a fourth buried channel according to each electrode; dividing a third buried channel corresponding to the multiplication phase down of the third electrode Φ em into a multiplication buried channel and a charge buried channel, the multiplication buried channel being used for charge multiplication; the charge buried channel is used for storing the multiplied charges, and the depth of the charge buried channel is larger than that of the multiplication buried channel.

Wherein, the first transfer phase and the second transfer phase are both normal transfer phases, and those skilled in the art can make corresponding settings with reference to the prior art.

In one embodiment, regarding the buried trench division, the depths of four buried trenches, that is, the first buried trench, the second buried trench, the third buried trench, and the fourth buried trench may be different from each other, but in general, the depths of the first buried trench and the fourth buried trench may be set to be the same, and the depth of the second buried trench is located between the first buried trench (fourth buried trench) and the third buried trench; the depth of the third buried channel is the deepest of all the buried channels as multiplication; the depth refers to the height of the bottom of the buried trench from the gate dielectric.

For the invention, the third buried channel is mainly improved, and the third buried channel is divided into a multiplication buried channel and a charge buried channel; wherein the depth of the multiplication buried channel is lower than the depth of the charge buried channel, so that the charge buried channel can effectively store charges. Because the multiplication buried channel is only responsible for multiplication, the area of the multiplication buried channel is not specially limited on the premise of normal multiplication function. The charge buried channel is responsible for storing charges, so the larger the charge buried channel area is, the better the charge buried channel area is. That is, when the multiplication phase area is constant, the multiplication buried channel has the area as small as possible under the premise of ensuring the normal multiplication function, so that the charge buried channel area is as large as possible, and more multiplication charges can be stored.

The substrate is a P-type substrate, and the buried channel is an N-type buried channel. The concentration of the multiplication buried channel is consistent with that of other buried channels, and the concentration of the charge buried channel is slightly higher than that of other buried channels.

The multiplication buried channel in the multiplication phase is set to be N-normal concentration, the charge buried channel in the multiplication phase is set to be N + phosphorus injection, and the concentration of the charge buried channel is slightly higher than that of the whole buried channel.

Through the arrangement, the buried channel potential distribution of the multiplication register structure is shown in fig. 5, the concentration of the charge buried channel is higher than that of the multiplication buried channel by arranging the charge buried channel in the multiplication phase as N + and adding phosphorus, and multiplication charges can move to the charge buried channel with high potential under the action of an electric field; the electric charge buried channel potential of the rear half part is slightly higher than that of the front half part, and the electric charge is stored in the rear half part after multiplication, so that the reduction of a multiplication electric field is effectively avoided, the stability of gain is ensured, and the response linearity is improved.

Considering that the movement of the multiplication charges into the charge burying channel causes the potential at the charge burying channel to gradually decrease, the present embodiment can ensure the normal use of the multiplication register structure within the effective range by setting the charge capacity.

In a preferred embodiment, the charge buried channel is arranged in an open structure for better increasing the charge capacity, so that the multiplied charges can be received and stored more effectively.

As one possible implementation example, a thin layer of N + ions may be coated on the surface of the charge buried channel for maintaining the potential difference between the multiplication buried channel and the charge buried channel, so as to facilitate the flow of the multiplication charges into the charge buried channel.

The basis of the above embodiments is that the substrate is a P-type substrate, the buried trench is an N-type buried trench, and the substrate is an N-type substrate, and the arrangement of the buried trench as a P-type buried trench can be adjusted accordingly based on the above embodiments.

Fig. 6 is an EMCCD for improving response linearity according to the present invention, which includes a storage region, a photosensitive region, a horizontal register and a sense amplifier, wherein a plurality of the above-mentioned multiplication register structures are installed between the horizontal register and the sense amplifier, and the plurality of multiplication register structures are connected in series.

It is understood that the multiplication register structure and the corresponding features of the EMCCD can be mutually cited in the present invention, and the present invention is not illustrated.

In the description of the present invention, it is to be understood that the terms "coaxial", "bottom", "one end", "top", "middle", "other end", "upper", "one side", "top", "inner", "outer", "front", "center", "both ends", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "disposed," "connected," "fixed," "rotated," and the like are to be construed broadly, e.g., as meaning fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; the terms may be directly connected or indirectly connected through an intermediate, and may be communication between two elements or interaction relationship between two elements, unless otherwise specifically limited, and the specific meaning of the terms in the present invention will be understood by those skilled in the art according to specific situations.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.