阅读说明：本技术 掩模板、闪存存储器及其制造方法 (Mask plate, flash memory and manufacturing method thereof ) 是由 汤志林 王卉 付永琴 曹子贵 于 2020-07-17 设计创作，主要内容包括：本发明提供一种掩模板、闪存存储器及其制造方法,本发明的掩模板包括依次交替设置的透过区和第一掩模结构,该掩模板应用在闪存存储器的制造方法中的离子注入工艺以形成漏极区,通过第一遮挡结构对至少位于该漏极区侧边的字线进行掩模,以防止离子穿透字线造成字线漏电,减少所制造出的闪存存储器出现编程串扰失效的次数和程度,以提升闪存存储器的性能。(The invention provides a mask plate, a flash memory and a manufacturing method thereof, wherein the mask plate comprises a transmission area and a first mask structure which are alternately arranged in sequence, the mask plate is applied to an ion implantation process in the manufacturing method of the flash memory to form a drain area, and a word line at least positioned on the side edge of the drain area is masked by a first shielding structure, so that the word line leakage caused by the fact that ions penetrate through the word line is prevented, the frequency and degree of programming crosstalk failure of the manufactured flash memory are reduced, and the performance of the flash memory is improved.)

1. A mask plate is used in an ion implantation process of a drain region in a flash memory and is characterized by comprising a first mask area, wherein the first mask area comprises a plurality of first shielding structures and transmission areas which are alternately arranged in parallel, when the mask plate is used for an ion implantation mask of the drain region in the manufacturing process of the flash memory, the transmission areas correspond to the drain region to be implanted, and the first shielding structures at least shield word lines of the flash memory.

2. The mask blank of claim 1, wherein the first mask area further comprises a plurality of second blocking structures that divide the transmissive area into a plurality of sub-transmissive areas that alternate with the second blocking structures; when the mask plate is used for a drain region ion implantation mask in the manufacturing process of the flash memory, the second shielding structure shields a spacing medium layer between adjacent drain regions to be implanted.

3. The mask plate according to claim 2, wherein the cross-sectional shape of the first shielding structure and/or the second shielding structure is a square or a rectangle.

4. The mask plate according to claim 2, wherein the cross-sectional shape of the first shielding structure and/or the second shielding structure is a regular trapezoid or an inverted trapezoid.

5. The mask plate according to claim 1, wherein the width of the transmissive region in a direction perpendicular to the extending direction thereof is 0.15um to 0.25 um.

6. A method for manufacturing a flash memory is characterized in that,

providing a substrate;

forming a device layer on the substrate, wherein the device layer comprises a plurality of sub device layers arranged at intervals, a drain region to be injected is arranged between every two adjacent sub device layers, and each sub device layer at least comprises a floating gate layer and a word line formed on the side edge of the floating gate layer;

providing a mask plate according to any one of claims 1 to 5, and performing an ion implantation process on the drain region to be implanted by using the mask plate, wherein the transmissive region of the mask plate corresponds to the drain region to be implanted, and the first shielding structure at least shields a word line of the flash memory;

and carrying out ion implantation on the drain region to be implanted.

7. The method of manufacturing a flash memory of claim 6, wherein prior to providing the mask plate, the method further comprises:

and forming a plurality of spacing medium layers on the substrate, wherein the spacing medium layers are used for spacing the adjacent drain regions to be implanted.

8. The method of claim 6, wherein the mask plate is offset from the device layer by an amount between-0.03 um and 0.03 um.

9. The method of claim 6, wherein the ions implanted into the drain region to be implanted comprise phosphorus ions and/or arsenic ions, the implantation temperature is 50 ℃ -60 ℃, the implantation energy is 10 Kev-40 Kev, and the implantation dose is 1E¹⁵～6E¹⁵cm³。

10. A flash memory manufactured by the method of any one of claims 6 to 9.

Technical Field

The invention relates to the technical field of semiconductors, in particular to a mask plate, a flash memory and a manufacturing method thereof.

Background

With the improvement of living standard of people, electronic products are more and more widely applied, and various semiconductor products are generally used in the electronic products. With the development of technology and the increase of demand, the performance requirements of semiconductor products are higher and higher.

For example, for flash memory, the frequency and degree of the occurrence of the program crosstalk failure are important indicators for detecting the performance of the flash memory. In the flash memory prepared based on the existing flash memory process, word lines are prone to electric leakage, so that the frequency and degree of crosstalk failure of the flash memory are increased, and the overall performance of the flash memory is further affected.

Disclosure of Invention

The invention aims to provide a mask plate, a flash memory and a manufacturing method thereof, which are used for solving the problem that the frequency and the degree of crosstalk failure in the flash memory are increased so as to improve the performance of the flash memory.

In order to solve the technical problem, the invention provides a mask plate which is used in an ion implantation process of a drain region in a flash memory, and the mask plate comprises a first mask area, wherein the first mask area comprises a plurality of first shielding structures and transmission areas which are alternately arranged in parallel, when the mask plate is used for an ion implantation mask of the drain region in the manufacturing process of the flash memory, the transmission areas correspond to the drain region to be implanted, and the first shielding structures at least shield word lines of the flash memory.

Preferably, the first mask region further comprises a plurality of second shielding structures, and the plurality of second shielding structures divide the transmissive region into a plurality of sub-transmissive regions arranged alternately with the second shielding structures; when the mask plate is used for a drain region ion implantation mask in the manufacturing process of the flash memory, the second shielding structure shields a spacing medium layer between adjacent drain regions to be implanted.

Preferably, the cross-sectional shape of the first shielding structure and/or the second shielding structure is a square or a rectangle.

Preferably, the cross-sectional shape of the first shielding structure and/or the second shielding structure is a regular trapezoid or an inverted trapezoid.

Preferably, the width of the transmission area perpendicular to the extending direction of the transmission area is 0.15 um-0.25 um.

Preferably, a substrate is provided;

forming a device layer on the substrate, wherein the device layer comprises a plurality of sub device layers arranged at intervals, a drain region to be injected is arranged between every two adjacent sub device layers, and each sub device layer at least comprises a floating gate layer and a word line formed on the side edge of the floating gate layer;

providing a mask plate according to any one of claims 1 to 5, and performing an ion implantation process on the drain region to be implanted by using the mask plate, wherein the transmissive region of the mask plate corresponds to the drain region to be implanted, and the first shielding structure at least shields a word line of the flash memory;

and carrying out ion implantation on the drain region to be implanted.

Preferably, before providing the mask plate, the method further comprises:

and forming a plurality of spacing medium layers on the substrate, wherein the spacing medium layers are used for spacing the adjacent drain regions to be implanted.

Preferably, the offset of the mask plate relative to the device layer is between-0.03 um and 0.03 um.

Preferably, the ions implanted into the drain region to be implanted comprise phosphorus ions and/or arsenic ions, the implantation temperature is 50-60 ℃, the implantation energy is 10-40 KeV, and the implantation dose is 1E¹⁵～6E¹⁵cm³。

In order to solve the above problems, the present invention further provides a flash memory, which is manufactured by using the method for manufacturing the flash memory.

The mask plate is used for masking when the flash memory is prepared and ion implantation is carried out to form a drain electrode region, and the word line at least positioned on the side edge of the drain electrode region is masked through the first shielding structure, so that the word line leakage caused by the fact that ions penetrate through the word line is prevented, the frequency and the degree of programming crosstalk failure of the prepared flash memory are reduced, and the performance of the flash memory is improved.

Drawings

Fig. 1 is a schematic structural diagram of a mask plate according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a mask blank according to another embodiment of the present invention;

FIG. 3a is a schematic view of one of the cross-sectional structures of FIG. 2 taken along direction BB';

FIG. 3b is a schematic view of another cross-sectional structure taken along the direction BB' in FIG. 2;

FIG. 3c is a schematic view of a further cross-sectional structure taken along the direction BB' in FIG. 2;

FIG. 4 is a flow chart of a method for manufacturing a flash memory according to an embodiment of the present invention;

FIGS. 5 a-5 b are schematic process diagrams illustrating a method for manufacturing a flash memory according to an embodiment of the invention;

wherein the reference numbers are as follows:

10-a substrate;

20-a device layer; 200-a sub-device layer;

201-a first dielectric layer; 202-a floating gate layer;

203-a first retaining wall; 204-word line;

205-bit lines;

30-a drain region; 30' -a drain region to be implanted;

1-a first mask region;

11-a first shielding structure;

12-a second shielding structure;

13-a permeable zone; 131-sub transmission region;

2-a second mask region;

3-a frame;

100-mask plate; 101-an opening;

Detailed Description

The mask plate, the flash memory and the manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.

Fig. 1 is a schematic structural diagram of a mask plate according to an embodiment of the present invention; as shown in fig. 1, a mask blank 100 of this embodiment is used in an ion implantation process of a drain region in a flash memory, and the mask blank 100 includes a first mask region 1, where the first mask region 1 includes a plurality of first shielding structures 11 and transmissive regions 13 alternately arranged in parallel. When the mask plate 100 of the present embodiment is used for forming a drain region for masking by ion implantation in a flash memory manufacturing process, the transmission region 13 corresponds to the drain region to be implanted, and the first shielding structure 11 at least shields a word line of the flash memory.

In the mask blank 100 of the present embodiment, the first shielding structure 11 is disposed to mask the word line at least located at the side of the drain region when the drain region of the flash memory is formed by ion implantation, so as to prevent the word line from leaking current due to ions penetrating through the word line, reduce the number of times and degree of programming crosstalk failures of the flash memory, and improve the performance of the flash memory.

With continued reference to fig. 1, in the present embodiment, the width d of the transmissive region 13 perpendicular to the extending direction thereof is 0.15um to 0.25 um. The width of the transmission region 13 is set within this range, so that the drain region to be implanted can be ensured to be effectively implanted with ions, and the word line can be prevented from being implanted.

With reference to fig. 1, the mask blank 100 of this embodiment further includes a second mask area 2, in this embodiment, the second mask area 2 is used to mask the non-active area of the flash memory, so as to prevent ions from being implanted into the non-active area during ion implantation, which reduces the performance of the flash memory. Further, as shown in fig. 1, in the present embodiment, the first mask region 1 and the second mask region 2 are rectangles disposed adjacently.

And, as shown in fig. 1, the mask blank 100 of the present embodiment further includes a frame 3, and the frame 3 surrounds the first mask area 1 and the second mask area 2.

Fig. 2 is a schematic structural diagram of a mask blank according to another embodiment of the present invention. As shown in fig. 2, in the present embodiment, the first mask region 1 further includes a plurality of second blocking structures 12, and the plurality of second blocking structures 12 divides the transmissive region 13 into a plurality of sub-transmissive regions 131 alternately arranged with the second blocking structures 12. When the mask plate 100 is used for a drain region ion implantation mask in a flash memory manufacturing process, the second shielding structure 12 shields a spacing medium layer between adjacent drain regions to be implanted. In this embodiment, since the second shielding structure 12 shields the spacing dielectric layer between the adjacent to-be-implanted drain regions of the flash memory, the problem that the adjacent drain regions are connected due to the ions penetrating through the intermediate dielectric layer in the ion implantation process, thereby preventing crosstalk between adjacent flash memory cells in the flash memory, can be effectively avoided.

FIG. 3a is a schematic view of one of the cross-sectional structures of FIG. 2 taken along direction BB'; referring to fig. 3a, in the present embodiment, the cross-sectional shape of the first shielding structure 11 is rectangular, and the cross-sectional shape of the first shielding structure 11 is rectangular. Therefore, the side wall of the first shielding structure 11 is perpendicular to the bottom surface of the first shielding structure 11, so that ions can be directly injected into the drain region to be injected into the flash memory during ion implantation, thereby preventing the ions from remaining on the side wall of the first shielding structure 11 and causing capacity loss. In other embodiments, the cross-sectional shape of the first shielding structure 11 may also be a square. In other embodiments, the cross-sectional shape of the second shielding structure 12 may also be rectangular or square, or the cross-sectional shapes of the first shielding structure 11 and the second shielding structure 12 are both rectangular or square.

FIG. 3b is a schematic view of another cross-sectional structure taken along the direction BB' in FIG. 2; referring to fig. 3b, in the present embodiment, the cross-sectional shape of the first shielding structure 11 is a regular trapezoid, because the cross-sectional shape of the first shielding structure 11 is a regular trapezoid. Therefore, the opening 101 between adjacent first shielding structures 11 is formed in a shape with a large top and a small bottom, that is, the area of the opening 101 near the top surface of the first shielding structure 11 is increased, and the area near the bottom surface of the first shielding structure 11 is decreased, so that the amount of ions entering the opening 101 during ion implantation can be increased, the amount of ions used is reduced, and the cost is saved. In other embodiments, the cross-sectional shape of the second shielding structure 12 may also be a regular trapezoid, or the cross-sectional shapes of the first shielding structure 11 and the second shielding structure 12 are both a regular trapezoid.

FIG. 3c is a schematic view of a further cross-sectional structure taken along the direction BB' in FIG. 2; referring to fig. 3b, in the present embodiment, the cross-sectional shape of the first shielding structure 11 is an inverted trapezoid, and since the cross-sectional shape of the first shielding structure 11 is an inverted trapezoid, the opening 101 between adjacent first shielding structures 11 is formed in a shape with a smaller top and a larger bottom, that is, the area of the opening 101 near the top surface of the first shielding structure 11 is reduced, and the area near the bottom surface of the first shielding structure 11 is increased. Therefore, the sidewall close to the bottom surface of the first shielding structure 11 is retracted, thereby further preventing the ions from remaining on the sidewall of the first shielding structure 11, which results in a loss of productivity. In other embodiments, the cross-sectional shape of the second shielding structure 12 may also be an inverted trapezoid, or the cross-sectional shapes of the first shielding structure 11 and the second shielding structure 12 are both inverted trapezoids.

Based on the mask plate as described above, a method of forming a flash memory by performing drain ion implantation using the mask plate will be described below. FIG. 4 is a flow chart of a method for manufacturing a flash memory according to an embodiment of the present invention; fig. 5 a-5 b are schematic process diagrams of a method for manufacturing a flash memory according to an embodiment of the invention. The steps of the method for manufacturing a semiconductor device according to the present embodiment will be described in detail with reference to the accompanying drawings.

In step S10, as shown in fig. 5a, the substrate 10 is provided.

The substrate may include a semiconductor material, an insulating material, a conductor material, or any combination thereof, and may have a single-layer structure or a multi-layer structure. Thus, the substrate may be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III/V or II/VI compound semiconductors. Layered substrates such as, for example, Si/SiGe, Si/SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator may also be included.

In step S20, as shown in fig. 5a, a device layer 20 is formed on a substrate 10, and the device layer 20 includes a plurality of sub device layers 200 arranged at intervals, a drain region to be implanted 30' is sandwiched between adjacent sub device layers 200, and each sub device layer 200 includes at least a floating gate layer 202 and a word line 204 formed at a side of the floating gate layer 202.

Specifically, referring to fig. 5a, the method for forming the sub-device layer 200 includes: forming a floating gate material layer and a mask layer on the substrate 10, forming a first sidewall 203 on a sidewall of the mask layer, etching the floating gate material layer using the first sidewall 203 and the mask layer as a mask to form a floating gate layer 202, and forming a word line 204 on a side of the floating gate layer 202. The floating gate layer 202 and the word line 204 may be polysilicon. The mask layer and the spacers 203 may be silicon oxide or silicon nitride.

With continued reference to fig. 5a, while forming the sub-device layers 200, the floating gate material layer between adjacent sub-device layers 200 is simultaneously etched such that the substrate 10 between adjacent sub-device layers 200 forms the to-be-implanted drain region 30'. Generally, when the to-be-implanted drain region 30 'is formed by etching, the substrate 10 is continuously etched toward the substrate 10 to form a trench between the adjacent sub-device layers 200, and the to-be-implanted drain region 30' is formed by the substrate 10 in the trench region.

In addition, in this embodiment, before forming the floating gate material layer, a first dielectric material layer is formed on the substrate 10, and the material of the first dielectric material layer includes silicon oxide. And etching the first dielectric material layer to form a first dielectric layer 201 while etching the floating gate material layer to form a floating gate layer 202.

Continuing to refer to fig. 5a, in this embodiment, a bit line 205 may also be formed on the side of the floating gate layer 202 away from the word line at the same time or after the word line 204 is formed on the word line side of the floating gate layer 202. The first dielectric layer 201, the floating gate 202, the first sidewall 203, the word line 204 and the bit line 205 form the sub-device layer 200. And, in this embodiment, the bit lines 205 and the word lines 204 in each sub-device layer 200 are alternately arranged, and the first retaining walls 203 are disposed between the adjacent bit lines 205 and word lines 204. Further, a second bank is formed on the word line side or the bit line side of the floating gate layer 202, and the second bank insulates the floating gate layer 202 from the word line 204 and insulates the floating gate layer 202 from the bit line 205.

In step S30: continuing with fig. 5a, the mask plate 100 is provided to perform an ion implantation process, wherein the transmission region 3 of the mask plate 100 corresponds to the drain region 30' to be implanted, and the first shielding structure 11 at least corresponds to shield the word line 204 of the flash memory.

In the present embodiment, a certain distance is provided between the mask plate 100 and the substrate 10, and the distance between the mask plate 100 and the substrate 10 is based on actual situations, and is not particularly limited herein.

And, the flash memory saving device in this embodiment includes an active area and a non-active area, wherein the first mask area 1 of the mask plate 100 corresponds to the active area of the flash memory, and the second mask area 2 of the mask plate 100 corresponds to the non-active area of the flash memory. The transmission region 3 located in the first mask region 1 corresponds to the to-be-implanted drain region 30', so that the to-be-implanted drain region 30' is exposed, and when ions are implanted subsequently, the to-be-implanted ions can pass through the transmission region 3 to implant ions into the to-be-implanted drain region 30' of the substrate 1.

In addition, in the embodiment, the first shielding structure 11 correspondingly shields the word line 204 and the bit line 205 of the flash memory. When the first shielding structure 11 shields the word line 204 and the bit line 205 of the flash memory, not only the word line leakage caused by the penetration of ions through the word line can be prevented, but also the bit line leakage caused by the penetration of ions through the bit line can be prevented. In addition, in other embodiments, to ensure that the ion implantation is performed on the to-be-implanted drain region 30', the first shielding structure 11 may also shield only the word line 204. The shielding region of the first shielding structure 11 is not particularly limited, and at least the word line 204 may be shielded based on actual conditions.

With continued reference to fig. 5b, the width d of the transmissive region 13 in the direction perpendicular to the extension direction of the transmissive region 13 is 0.15um to 0.25 um. Setting the width d of the transmission region 13 within the above range ensures that the drain region 30' to be implanted can be effectively implanted and prevents at least the region of the word line 204 from being blocked. The mask plate 100 is made of a material including, but not limited to, metal, silicon dioxide, photoresist, etc.

In addition, in the embodiment, the offset of the mask plate 100 relative to the flash memory is between-0.03 um and 0.03 um. When the offset amount of the mask plate 100 with respect to the flash memory is within the above range, it is ensured that the ion implantation region does not shift too much when ions are implanted through the transmission region 13.

With continued reference to fig. 5a, before providing the mask plate 100, the method for manufacturing a flash memory further includes forming a plurality of spacer dielectric layers on the substrate 10, wherein the spacer dielectric layers are located in the active area of the flash memory.

With continued reference to fig. 5a in combination with fig. 2, in other embodiments, the first mask area 1 of the mask blank 100 further comprises a plurality of second shielding structures 12 perpendicular to the first shielding structures 11; the plurality of second shielding structures 12 divides the transmissive area 13 into a plurality of sub transmissive areas 131 alternately arranged with the second shielding structures 12. When the mask plate 100 is used for an ion implantation mask of a to-be-implanted drain region 30 'in a flash memory manufacturing process, the second shielding structure 12 shields a spacer dielectric layer between adjacent to-be-implanted drain regions in the to-be-implanted drain region 30', wherein the spacer dielectric layer is perpendicular to the word line 204. In this embodiment, since the second shielding structure 12 shields the spacer dielectric layer between the adjacent to-be-implanted drain regions 30' of the flash memory, the problem of crosstalk between adjacent flash memory cells in the flash memory due to the fact that ions penetrate the spacer dielectric layer to connect the adjacent sub-drain regions in the ion implantation process can be effectively avoided.

Continuing with fig. 5a, in step S40, the drain region to be implanted 30' is ion implanted.

In this step, the ions to be implanted into the drain region 30' are phosphorus ions and arsenic ions, the implantation temperature is 50C-60C, the implantation energy is 10 Kev-40 KeV, and the implantation number is 1E¹⁵～6E¹⁵cm³. In this step, as shown in fig. 5b, the drain region 30' to be implanted is ion implanted to form the drain region 30 as shown.

The method for manufacturing the flash memory of the embodiment is applied to the preparation of the flash memory, and the flash memory is masked when ion implantation is performed to form the drain region, and the word line 204 at least positioned on the side of the drain region is masked by the first shielding structure 11, so as to prevent the word line 204 from electric leakage caused by the penetration of ions through the word line 204, which is beneficial to reducing the times and degree of programming crosstalk failure of the flash memory, and improving the performance of the flash memory.

Further, the present embodiment also discloses a flash memory, which is manufactured by using the above method for manufacturing a flash memory, and in the process of manufacturing the flash memory, the word line 204 is blocked by the first blocking structure 11 of the mask plate 100, so as to prevent the flash memory from leaking electricity due to the penetration of ions through the word line 204. The times and the degree of programming crosstalk failure of the flash memory are reduced, so that the performance of the flash memory is improved.

It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, similar parts between the embodiments may be referred to each other, and different parts between the embodiments may also be used in combination with each other, which is not limited by the present invention.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.