阅读说明：本技术 集成型GaN器件及其制备方法 (Integrated GaN device and preparation method thereof ) 是由 马飞 邹鹏辉 郑礼锭 蔡泉福 于 2020-08-20 设计创作，主要内容包括：本发明提供一种集成型GaN器件及其制备方法,制备方法包括：在半导体外延结构上制备不同器件的源漏电极,制备器件隔离结构,刻蚀外延帽层和势垒层,制备显露GaN沟道层的栅极开口,外延帽层及势垒层采用不同工艺去除,制备栅介质层及栅极结构,得到不同器件,再制备互连电极结构,实现器件互连。本发明在同一半导体外延衬底上有效集成了第一器件和第二器件,为电路设计提供多种可行性设计,减少了寄生及成本。通过工艺设计,除栅极开口的刻蚀外,其他步骤都同时进行,不增加工艺难度,在提升器件整体性能的同时节约了后道封装成本。对于形成栅极开口过程中的外延帽层及势垒层的刻蚀,可以更好的控制刻蚀精度,避免传统刻蚀对材料造成的破坏。(The invention provides an integrated GaN device and a preparation method thereof, wherein the preparation method comprises the following steps: preparing source and drain electrodes of different devices on a semiconductor epitaxial structure, preparing a device isolation structure, etching an epitaxial cap layer and a barrier layer, preparing a grid opening for exposing a GaN channel layer, removing the epitaxial cap layer and the barrier layer by adopting different processes, preparing a grid dielectric layer and a grid structure to obtain different devices, and then preparing an interconnection electrode structure to realize interconnection of the devices. The invention effectively integrates the first device and the second device on the same semiconductor epitaxial substrate, provides a plurality of feasible designs for circuit design, and reduces the parasitic and cost. Through the process design, except for the etching of the grid opening, other steps are carried out simultaneously, the process difficulty is not increased, the overall performance of the device is improved, and meanwhile the subsequent packaging cost is saved. The etching precision of the epitaxial cap layer and the barrier layer in the process of forming the gate opening can be better controlled, and the damage of the traditional etching to materials is avoided.)

1. A method for manufacturing an integrated GaN device, the method comprising:

providing a semiconductor epitaxial structure, wherein the semiconductor epitaxial structure comprises a semiconductor substrate, a GaN channel layer, a barrier layer and an epitaxial cap layer from bottom to top;

preparing a first source electrode, a first drain electrode, a second source electrode and a second drain electrode on the semiconductor epitaxial structure;

performing ion implantation on the semiconductor epitaxial structure to form a device isolation structure, wherein the device isolation structure extends from the epitaxial cap layer to the GaN channel layer, and the device isolation structure isolates the first source electrode and the first drain electrode from the second source electrode and the second drain electrode;

etching to remove part of the epitaxial cap layer between the first source electrode and the first drain electrode and the barrier layer below the epitaxial cap layer so as to form a gate opening, wherein the GaN channel layer is exposed from the gate opening, and the epitaxial cap layer and the barrier layer are respectively etched by adopting different processes;

forming a gate dielectric layer on the surface of the semiconductor epitaxial structure, wherein the gate dielectric layer between the first source electrode and the first drain electrode forms a first gate dielectric layer, the first gate dielectric layer also covers the bottom and the side wall of the gate opening, and the gate dielectric layer between the second source electrode and the second drain electrode forms a second gate dielectric layer;

forming a first grid structure on the surface of the first grid dielectric layer to obtain a first device, wherein the first grid structure at least fills the grid opening, and a second grid structure is formed on the surface of the second grid dielectric layer to obtain a second device;

preparing an interconnect electrode structure to electrically connect the first device to the second device.

2. According to claimThe method of claim 1, wherein during the step of performing ion implantation to form the device isolation structure, a plurality of ion implantations are performed to form the isolation structure, wherein the ion implantation energy is between 5 and 200KeV, and the implantation dose is between 5 x 10¹²-5*10¹³cm^-2Wherein the implant particles comprise N₂、He、O₂Ar, Fe, C, Al and Xe.

3. The method of claim 1, wherein the barrier layer comprises an AlN layer, the barrier layer having a thickness between 2nm and 5 nm; the epitaxial cap layer comprises a GaN layer, and the thickness of the epitaxial cap layer is between 1nm and 3 nm.

4. The method of claim 1, wherein the process of etching the epitaxial cap layer comprises:

1) carrying out surface modification treatment on the epitaxial cap layer in an ICP (inductively coupled plasma) chamber to form a surface modification layer;

2) and carrying out plasma treatment on the modified epitaxial cap layer in the same chamber to remove the surface modified layer and realize the etching of the epitaxial cap layer.

5. The method according to claim 4, wherein in step 1), the surface modification treatment comprises modifying the surface of the epitaxial cap layer with chlorine gas, and the surface modification layer comprises a chloride layer to reduce dissociation energy of chemical bonds in the epitaxial cap layer; in the step 2), the ions subjected to the plasma treatment include Ar ions.

6. The method for preparing an integrated GaN device according to claim 5, wherein in step 1) and step 2), the source power in the ICP chamber is the same, and the pressure in the ICP chamber is the same; the source power in the ICP chamber is between 80W and 120W, and the pressure in the ICP chamber is between 25mTorr and 35 mTorr; in the step 2), the radio frequency power of the plasma treatment is between 1W and 4W.

7. The method for manufacturing an integrated GaN device according to claim 5, further comprising step 3) after step 2): and circularly performing the step 1) and the step 2) until the epitaxial cap layer is removed.

8. The method for preparing an integrated GaN device according to claim 7, wherein in each cycle, the time for performing the chlorine modification treatment in step 1) is between 30s and 60s, the time for performing the plasma treatment in step 2) is between 10s and 30s, and the etching thickness of the epitaxial cap layer is less than 0.5nm, so as to realize the damage-free etching of the epitaxial cap layer through multi-step cycles.

9. The method of claim 4, wherein the barrier layer is removed by a wet selective process, and the agent for removing the barrier layer comprises at least one of KOH and AZ 400K.

10. The method of claim 1, wherein the gate dielectric layer is formed by an atomic layer deposition process, the gate dielectric layer comprises a BeO material layer, the deposition temperature of the BeO material layer is between 100 ℃ and 300 ℃, and the thickness of the BeO material layer is between 5nm and 50 nm.

11. The method of claim 1, further comprising a step of forming a continuous native oxide layer on the surface of the epitaxial structure before forming the gate dielectric layer, wherein the native oxide layer and the gate dielectric layer are formed based on a same atomic layer deposition process chamber, the native oxide layer is formed based on ozone, and an oxygen source of the gate dielectric layer comprises ozone.

12. The method for manufacturing an integrated GaN device according to any of claims 1-11 wherein the step of manufacturing the interconnect electrode structure comprises: forming a dielectric passivation layer on the semiconductor epitaxial structure forming the first and second gate structures; forming an interconnection through hole in the medium passivation layer by adopting a photoetching process; and depositing metal in the interconnection through hole to form a metal connecting column so as to obtain the interconnection electrode structure.

13. An integrated GaN device, comprising:

the semiconductor epitaxial structure comprises a semiconductor substrate, a GaN channel layer, a barrier layer and an epitaxial cap layer from bottom to top;

a first source electrode, a first drain electrode, a second source electrode and a second drain electrode which are formed on the semiconductor epitaxial structure, wherein a gate opening is formed in the epitaxial cap layer between the first source electrode and the first drain electrode and the barrier layer below the epitaxial cap layer, and the GaN channel layer is exposed out of the gate opening;

a device isolation structure extending from the epitaxial cap layer into the GaN channel layer, isolating the first source electrode, the first drain electrode from the second source electrode, the second drain electrode;

the gate dielectric layer is formed on the surface of the semiconductor epitaxial structure and comprises a first gate dielectric layer positioned between the first source electrode and the first drain electrode and a second gate dielectric layer positioned between the second source electrode and the second drain electrode, and the first gate dielectric layer also covers the bottom and the side wall of the gate opening;

the first grid structure is formed on the surface of the first grid dielectric layer and at least fills the grid opening to form a first device, and the second grid structure is formed on the surface of the second grid dielectric layer to form a second device; and

and the interconnection electrode structure is positioned on the semiconductor epitaxial structure and used for realizing interconnection of the first device and the second device.

14. The integrated GaN device of claim 13 wherein the gate dielectric layer comprises a layer of BeO material having a thickness between 5nm and 50 nm; the interconnect electrode structure includes a dielectric passivation layer formed on the epitaxial structure and a metal connection stud formed in the dielectric passivation layer.

15. The integrated GaN device of any of claims 13-14 wherein the barrier layer comprises an AlN layer, the barrier layer having a thickness between 2nm-5 nm; the epitaxial cap layer comprises a GaN layer, and the thickness of the epitaxial cap layer is between 1nm and 3 nm.

Technical Field

The invention belongs to the field of semiconductor integrated circuit manufacturing, and particularly relates to an integrated GaN device and a preparation method thereof.

Background

The research and application of GaN material is the leading edge and hot spot of the current global semiconductor research, is a novel semiconductor material for developing microelectronic devices and optoelectronic devices, and is praised as the third generation semiconductor material following the first generation Ge, Si semiconductor material, the second generation GaAs, InP compound semiconductor material together with semiconductor materials such as SIC, diamond and the like. The material has the properties of wide direct band gap, strong atomic bond, high thermal conductivity, good chemical stability (hardly corroded by any acid) and the like, and strong irradiation resistance, and has wide prospects in the application aspects of photoelectrons, high-temperature high-power devices and high-frequency microwave devices.

The working mode of the traditional GaN device is mostly depletion type normally-on device, and the problems of high power consumption and complex design of an application circuit exist. As a normally-on device, an external device such as a Si device is usually required for switching control, and thus the performance is limited to the Si material device. Because the GaN material has excellent performance, not only high power density, but also high frequency, in order to better utilize the material performance characteristics, develop different performance and function, it is necessary to integrate different types of devices on the same wafer as much as possible, but in the prior art, it is difficult to effectively integrate the different devices, and the device performance is greatly affected by the inevitable etching defects existing in the conventional process.

Therefore, how to provide an integrated GaN device and a method for manufacturing the same are necessary to solve the above problems.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide an integrated GaN device and a method for manufacturing the same, which can solve the problem of the prior art that it is difficult to efficiently integrate GaN-based heterogeneous devices on the same wafer.

To achieve the above and other related objects, the present invention provides a method for manufacturing an integrated GaN device, the method comprising the steps of:

providing a semiconductor epitaxial structure, wherein the semiconductor epitaxial structure comprises a semiconductor substrate, a GaN channel layer, a barrier layer and an epitaxial cap layer from bottom to top;

preparing a first source electrode, a first drain electrode, a second source electrode and a second drain electrode on the semiconductor epitaxial structure;

performing ion implantation on the semiconductor epitaxial structure to form a device isolation structure, wherein the device isolation structure extends from the epitaxial cap layer to the GaN channel layer, and the device isolation structure isolates the first source electrode and the first drain electrode from the second source electrode and the second drain electrode;

etching to remove part of the epitaxial cap layer between the first source electrode and the first drain electrode and the barrier layer below the epitaxial cap layer so as to form a gate opening, wherein the GaN channel layer is exposed from the gate opening, and the epitaxial cap layer and the barrier layer are respectively etched by adopting different processes;

forming a gate dielectric layer on the surface of the semiconductor epitaxial structure, wherein the gate dielectric layer between the first source electrode and the first drain electrode forms a first gate dielectric layer, the first gate dielectric layer also covers the bottom and the side wall of the gate opening, and the gate dielectric layer between the second source electrode and the second drain electrode forms a second gate dielectric layer;

forming a first grid structure on the surface of the first grid dielectric layer to obtain a first device, wherein the first grid structure at least fills the grid opening, and a second grid structure is formed on the surface of the second grid dielectric layer to obtain a second device; and

preparing an interconnect electrode structure to electrically connect the first device to the second device.

Optionally, in the process of performing ion implantation to form the device isolation structure, the isolation structure is formed by using multi-step ion implantation, wherein the implantation energy of the ion implantation is between 5KeV and 200KeV, and the implantation dose is between 5 × 10¹²-5*10¹³cm^-2Wherein the implant particles comprise N₂、He、O₂Ar, Fe, C, Al and Xe.

Optionally, the barrier layer comprises an AlN layer, the barrier layer having a thickness between 2nm-5 nm; the epitaxial cap layer comprises a GaN layer, and the thickness of the epitaxial cap layer is between 1nm and 3 nm.

Optionally, the process of etching the epitaxial cap layer includes:

1) carrying out surface modification treatment on the epitaxial cap layer in an ICP (inductively coupled plasma) chamber to form a surface modification layer;

2) and carrying out plasma treatment on the modified epitaxial cap layer in the same chamber to remove the surface modified layer and realize the etching of the epitaxial cap layer.

Optionally, in step 1), the surface modification treatment process includes modifying the surface of the epitaxial cap layer with chlorine gas, and the formed surface modification layer includes a chloride layer to reduce dissociation energy of chemical bonds in the epitaxial cap layer; in the step 2), the ions subjected to the plasma treatment include Ar ions.

Optionally, in step 1) and step 2), the source power in the ICP chamber is the same, and the pressure in the ICP chamber is the same.

Optionally, in step 1) and step 2), the source power in the ICP chamber is between 80W-120W, and the pressure in the ICP chamber is between 25mTorr-35 mTorr; in the step 2), the radio frequency power of the plasma treatment is between 1W and 4W.

Optionally, step 2) is followed by step 3): and circularly performing the step 1) and the step 2) until the epitaxial cap layer is removed.

Optionally, in each cycle, the time for performing the chlorine modification treatment in step 1) is between 30s and 60s, the time for performing the plasma treatment in step 2) is between 10s and 30s, and the etching thickness of the epitaxial cap layer is less than 0.5nm, so that the damage-free etching of the epitaxial cap layer is realized through multiple cycles.

Optionally, the barrier layer is removed by a wet selective process, and the agent for removing the barrier layer comprises at least one of KOH and AZ 400K.

Optionally, an atomic layer deposition process is adopted to form the gate dielectric layer, the gate dielectric layer includes a BeO material layer, the deposition temperature of the BeO material layer is between 100 ℃ and 300 ℃, and the thickness of the BeO material layer is between 5nm and 50 nm.

Optionally, before forming the gate dielectric layer, a step of forming a continuous natural oxide layer on the surface of the epitaxial structure is further included, wherein the natural oxide layer and the gate dielectric layer are completed based on the same atomic layer deposition process chamber, the natural oxide layer is formed based on ozone, and an oxygen source of the gate dielectric layer includes ozone.

Optionally, the step of preparing the interconnect electrode structure comprises: forming a dielectric passivation layer on the semiconductor epitaxial structure forming the first and second gate structures; forming an interconnection through hole in the medium passivation layer by adopting a photoetching process; and depositing metal in the interconnection through hole to form a metal connecting column so as to obtain the interconnection electrode structure.

The present invention also provides an integrated GaN device, which is preferably prepared by the integrated GaN device preparation method of the present invention, and of course, may be prepared by other methods, the integrated GaN device comprising:

the semiconductor epitaxial structure comprises a semiconductor substrate, a GaN channel layer, a barrier layer and an epitaxial cap layer from bottom to top;

a first source electrode, a first drain electrode, a second source electrode and a second drain electrode which are formed on the semiconductor epitaxial structure, wherein a gate opening is formed in the epitaxial cap layer between the first source electrode and the first drain electrode and the barrier layer below the epitaxial cap layer, and the GaN channel layer is exposed out of the gate opening;

a device isolation structure extending from the epitaxial cap layer into the GaN channel layer, isolating the first source electrode, the first drain electrode from the second source electrode, the second drain electrode;

the gate dielectric layer is formed on the surface of the semiconductor epitaxial structure and comprises a first gate dielectric layer positioned between the first source electrode and the first drain electrode and a second gate dielectric layer positioned between the second source electrode and the second drain electrode, and the first gate dielectric layer also covers the bottom and the side wall of the gate opening;

the first grid structure is formed on the surface of the first grid medium and at least fills the grid opening to form a first device, and the second grid structure is formed on the surface of the second grid medium to form a second device; and

and the interconnection electrode structure is positioned on the semiconductor epitaxial structure and is used for realizing the electric connection of the first device and the second device.

Optionally, the gate dielectric layer includes a BeO material layer, and a thickness of the BeO material layer is between 5nm and 50 nm.

Optionally, the interconnect electrode structure includes a dielectric passivation layer formed on the epitaxial structure and a metal connection stud formed in the dielectric passivation layer.

Optionally, the barrier layer comprises an AlN layer, the barrier layer having a thickness between 2nm-5 nm; the epitaxial cap layer comprises a GaN layer, and the thickness of the epitaxial cap layer is between 1nm and 3 nm.

As described above, the integrated GaN device and the method for manufacturing the same according to the present invention effectively integrate the first device and the second device on the same semiconductor epitaxial substrate, thereby providing a variety of feasible designs for circuit design, facilitating circuit design and interconnection, avoiding the need to manufacture separate discrete devices, and finally reducing parasitic and cost by wire bonding connection. Through the process design, other steps are simultaneously carried out except the nondestructive etching of the grid opening of the first device, the process difficulty is not increased, the process is simple and convenient, the cost is low, and the subsequent packaging cost is saved while the overall performance of the device is improved. For the etching of the epitaxial cap layer and the barrier layer in the process of forming the gate opening, a step-by-step selective and nondestructive etching process is adopted, the etching precision can be better controlled, and meanwhile, the etching and wet etching are carried out after the Cl-based surface is modified, the damage of the traditional dry ion beam etching to the material is avoided, and the process cost is lower.

Drawings

Fig. 1 shows a process flow diagram for the fabrication of an integrated GaN device in accordance with an embodiment of the present invention.

Fig. 2 shows a schematic diagram of providing a semiconductor epitaxial structure in the fabrication of an integrated GaN device according to an embodiment of the present invention.

Fig. 3 is a schematic structural diagram illustrating the formation of a first source, a first drain, a second source, a second drain and a device isolation structure in the fabrication of an integrated GaN device according to an embodiment of the present invention.

Fig. 4 is a schematic structural diagram illustrating the formation of a patterned dielectric layer in the fabrication of an integrated GaN device according to an embodiment of the present invention.

FIG. 5 is a schematic diagram illustrating the etching of the epitaxial cap layer to form an initial opening in the fabrication of the integrated GaN device according to the embodiment of the invention.

Fig. 6 is a schematic structural diagram illustrating the formation of a gate opening in the fabrication of an integrated GaN device according to an embodiment of the present invention.

Fig. 7 is a schematic structural diagram illustrating the formation of the first gate dielectric layer and the second gate dielectric layer in the integrated GaN device fabrication according to an embodiment of the present invention.

Fig. 8 is a schematic structural diagram illustrating the formation of a first gate structure and a second gate structure in the fabrication of an integrated GaN device according to an embodiment of the present invention.

Fig. 9 is a schematic structural diagram illustrating the formation of an interconnection electrode structure in the fabrication of an integrated GaN device according to an embodiment of the present invention.

Description of the element reference numerals

100-a semiconductor epitaxial structure, 101-a semiconductor substrate, 102-a buffer layer, 103-a GaN channel layer, 104-a barrier layer, 105-an epitaxial cap layer, 106-a first source electrode, 107-a first drain electrode, 108-a second source electrode, 109-a second drain electrode, 110-a device isolation structure, 111-an imaging photoresist layer, 111 a-an etching opening, 112-an initial opening, 113-a gate opening, 114-a gate dielectric layer, 114 a-a first gate dielectric layer, 114 b-a second gate dielectric layer, 115-a first gate structure, 116-a second gate structure, 117-a first device, 118-a second device, 119-a passivation dielectric layer, 120-a metal connecting column and S1-S7.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. In addition, "between … …" as used herein includes both endpoints.

In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.

As shown in fig. 1, the present invention provides a method for manufacturing an integrated GaN device, the method comprising the steps of:

s1: providing a semiconductor epitaxial structure, wherein the semiconductor epitaxial structure comprises a semiconductor substrate, a GaN channel layer, a barrier layer and an epitaxial cap layer from bottom to top;

s2: preparing a first source electrode, a first drain electrode, a second source electrode and a second drain electrode on the semiconductor epitaxial structure;

s3: performing ion implantation on the semiconductor epitaxial structure to form a device isolation structure, wherein the device isolation structure extends from the epitaxial cap layer to the GaN channel layer, and the device isolation structure isolates the first source electrode and the first drain electrode from the second source electrode and the second drain electrode;

s4: etching to remove part of the epitaxial cap layer between the first source electrode and the first drain electrode and the barrier layer below the epitaxial cap layer so as to form a gate opening, wherein the GaN channel layer is exposed from the gate opening, and the epitaxial cap layer and the barrier layer are respectively etched by adopting different processes;

s5: forming a gate dielectric layer on the surface of the semiconductor epitaxial structure, wherein the gate dielectric layer between the first source electrode and the first drain electrode forms a first gate dielectric layer, the first gate dielectric layer also covers the bottom and the side wall of the gate opening, and the gate dielectric layer between the second source electrode and the second drain electrode forms a second gate dielectric layer;

s6: forming a first grid structure on the surface of the first grid dielectric layer to obtain a first device, wherein the first grid structure at least fills the grid opening, and a second grid structure is formed on the surface of the second grid dielectric layer to obtain a second device; and

s7: preparing an interconnect electrode structure to electrically connect the first device to the second device.

The method for manufacturing an integrated GaN device according to the present invention will be described in detail with reference to the accompanying drawings, wherein it should be noted that the above-mentioned sequence does not strictly represent the manufacturing sequence of the integrated GaN device protected by the present invention, and those skilled in the art can change the sequence according to the actual process steps, and fig. 1 shows only one exemplary manufacturing step of the integrated GaN device.

First, as shown in S1 in fig. 1 and fig. 2, step S1 is performed to provide a semiconductor epitaxial structure 100, where the semiconductor epitaxial structure 100 includes, from bottom to top, a semiconductor substrate 101, a GaN channel layer 103, a barrier layer 104, and an epitaxial cap layer 105. The material layers of the semiconductor epitaxial structure 100 may be grown by an epitaxial technique, or may be obtained by an outsourcing method, as long as the functions required by the material layers are realized.

Specifically, the semiconductor substrate 100 may include, but is not limited to, a sapphire substrate, a SiC substrate, a Si substrate, a GaN substrate, and the like, and in other embodiments, the semiconductor substrate 100 may also be a substrate of other elemental semiconductors or compound semiconductors. In addition, the semiconductor substrate 100 may have a single-layer material layer structure or a stacked structure. In this embodiment, the semiconductor substrate 100 is a Si substrate, and silicon is used as the substrate, so that heteroepitaxy of GaN material can be realized on a large-sized wafer, and the unit-size epitaxy cost is saved.

In addition, the semiconductor epitaxial structure 100 further includes a buffer layer 102 formed between the semiconductor substrate 101 and the GaN channel layer 103, which can release stress generated between the epitaxially grown heterostructure and the substrate due to lattice mismatch and thermal mismatch, and the buffer layer 102 may be, but is not limited to, an AlGaN buffer layer, and is selected to be an AlGaN buffer layer in this embodiment.

By way of example, the barrier layer 104 comprises an AlN layer, and the barrier layer 104 has a thickness between 2nm and 5nm, and may be, for example, 2.5nm, 3nm, or 4 nm; the epitaxial cap layer 105 comprises a GaN layer, and the thickness of the epitaxial cap layer 105 is between 1nm and 3nm, and may be, for example, 1.5nm, 2nm, or 2.5 nm. In the present embodiment, the barrier layer 104 is selected as an AlN layer, on one hand, AlN has a greater polarization effect than AlGaN, and more two-dimensional electron density can be polarized in the GaN channel by depositing AlN (2-5 nm) with a thickness smaller than that of conventional AlGaN (20-30 nm). Moreover, the AlN barrier layer is thinner, so that the distance between a grid and a channel is shortened, and grid control is improved; on the other hand, the AlN layer is selected as the barrier layer, and the etching of a gate opening is formed subsequently based on the characteristic that the AlN layer is used as the barrier layer, namely, the selective etching of the AlN relative to the GaN can be realized by utilizing wet etching, so that the defects generated in the etching process are reduced, and the performance of the device is improved. In this embodiment, the epitaxial cap layer 105 is selected as a GaN layer, which is more stable than an AlN layer and is beneficial to effectively protecting the AlN layer, and in addition, the GaN layer is selected as the epitaxial cap layer, and the setting of thickness, doping, and the like can be performed based on the characteristics of the GaN layer as the epitaxial cap layer (the process steps of the present embodiment are applicable to a p-GaN enhancement device, i.e., p-GaN is formed by doping, and the preparation of an enhancement GaN HEMT device can be performed), so as to facilitate the subsequent etching for forming a gate opening, thereby facilitating the reduction of defects generated in the etching process and the improvement of the device performance.

Next, as shown in S2 of fig. 1 and fig. 3, step S2 is performed to fabricate the first source 106, the first drain 107, the second source 108 and the second drain 109 on the semiconductor epitaxial structure 100. In one example, the first source 106, the first drain 107, the second source 108, and the second drain 109 are fabricated based on the same process.

In an example, each of the source and drain electrodes may be prepared by photolithography, metal deposition, metal lift-off, and an annealing process, so as to obtain an ohmic contact electrode. In this step, source and drain electrodes of different devices integrated on the same semiconductor substrate 101 may be defined through the above process. For example, the first source 106 and the first drain 107 may form a source/drain electrode of an enhancement device, and the second source 108 and the second drain 109 may form a source/drain electrode of a depletion device. In a specific example, the positions of the source and drain electrodes may be defined through a photoresist photolithography process, the photoresist layer has electrode openings exposing the electrodes of the epitaxial cap layer 105, and then the source and drain electrodes are obtained on the surface of the epitaxial cap layer 105. The material of each source-drain electrode can be a metal stack, such as Ti/Al/Ni/Au. Of course, other material depositions may be performed as desired. In the present example, the semiconductor substrate 101 is selected as a Si substrate, in which non-gold stack, such as Ti/Al/TaN, is used for each source/drain electrode, and then annealing is performed at 550 ℃ to 850 ℃ to realize ohmic contact.

Continuing to perform step S3, as shown in S3 of fig. 1 and fig. 3, ion implantation is performed on the semiconductor epitaxial structure 100 to form a device isolation structure 110, the device isolation structure 110 extends from the epitaxial cap layer 105 into the GaN channel layer 103, and the device isolation structure 110 isolates the first source 106 and the first drain 107 from the second source 108 and the second drain 109. In this step, the device isolation structure 110 is prepared by ion implantation, so as to achieve isolation of the first device and the second device formed subsequently. The isolation of the device can be firstly carried out according to the functional requirements of the actual circuit, and then interconnection is formed according to the requirements, so that the diversity of circuit design is facilitated. In this embodiment, the device isolation structure 110 is selected to be prepared after the preparation of each source/drain electrode of different devices is completed and before the formation of the gate opening of the device. In one example, the device isolation structure 110 extends below the two-dimensional electron gas of the GaN channel layer 103 to achieve device isolation, and in an alternative example, the device isolation structure 110 extends through the epitaxial cap layer 105, the barrier layer 104, and through the GaN channel layer 103. In another example, the device isolation structure 110 extends into the buffer layer.

As an example, in the process of performing ion implantation to form the device isolation structure 110, the implantation energy of the ion implantation is between 5KeV and 200KeV, for example, 10 KeV, 50KeV, 80KeV, 100KeV, and 150KeV, and the implantation dose is between 5 × 10¹²-5*10¹³cm^-2May be, for example, 8 x 10¹²、2*10¹³The implant particles include N₂、He、O₂Ar, Fe, C, Al, Xe, N being chosen as the choice in this example₂Performing implantation, and performing multiple energy and dose injections to obtainUniformly stepped vacancies in the 500nm to 600nm depth region at a density of 5 x 10²⁰cm^-3。

In one example, the ion implantation is performed in a distributed manner to achieve a flat ion implantation effect. Wherein, a Gaussian distribution is formed when the first ion implantation is carried out, and then, a plurality of steps of ion implantation with different energies and dosages are carried out, so that the distribution is flattened. In one embodiment, the multi-step ion implantation energy may be varied linearly (from large to small) to achieve a desired uniform implantation effect. For example, the implant energy is 200KeV (the depth of implant is deepest) and the implant dose is 1X 10¹³cm^-2Implant N2 and then implant dose 2 x 10 at an implant energy of 150keV (shallow implant depth)¹³cm^-2Implanting N2, sequentially reducing the implantation energy to make the implantation depth gradually shallow, and finally implanting 5 × 10 at an implantation energy of 5KeV (the implantation depth is the shallowest)¹³cm^-2N2 was implanted to maximize the surface implant concentration and ensure good isolation.

Next, as shown in S4 of fig. 1 and fig. 4-6, step S4 is performed to etch and remove a portion of the epitaxial cap layer 105 between the first source 106 and the first drain 107 and the barrier layer 104 thereunder to form a gate opening 113, and the gate opening 113 exposes the GaN channel layer 103, wherein the epitaxial cap layer 105 and the barrier layer 104 are respectively etched by different processes.

In this step, the epitaxial cap layer 105 and the barrier layer 104, which correspond to each other, are etched away at the same time to prepare a gate recess of a first device, for example, the first device may be a MOS transistor. Removing the epitaxial cap layer 105 and removing the underlying barrier layer 104 to form the gate opening 113 exposing the GaN channel layer 103 to achieve ensuring that there is no two-dimensional electron gas without applying a forward gate voltage to form an enhanced device (first device). The two-dimensional electron gas of the GaN channel layer is a polarization effect generated only by the existence of a barrier layer (such as an AlN or AlGaN barrier layer), the barrier layer is etched, so that the two-dimensional electron gas which is not polarized in the GaN channel layer under the condition of no electricity is applied, an enhancement type MOSFET device can be prepared, the GaN device is an MOS enhancement type device, namely, the threshold value is positive, and the size can be correspondingly adjusted according to the thickness of subsequent gate oxide deposition and the type of gate oxide materials. Furthermore, the invention can form a lossless, clear and smooth GaN interface through wet selective etching, is beneficial to the performance of devices, has low process cost and difficulty and high repeatability, and has higher etching selectivity compared with GaN.

As an example, the epitaxial cap layer 105 and the barrier layer 104 are etched by different processes. As shown in fig. 4, firstly, a patterned photoresist layer 111 is formed on the surface of the semiconductor epitaxial structure 100, the patterned photoresist layer 111 has an etching opening 111a, the etching opening 111a defines a position of a gate opening to be formed subsequently, then, the epitaxial cap layer 105 is etched first to form an initial opening 112, and finally, the barrier layer 104 is etched to form the gate opening 113. In an alternative example, the epitaxial cap layer 105 is selected to be a GaN layer and the barrier layer 104 is selected to be an AlN layer.

In an alternative example, the process of etching the epitaxial cap layer 105 includes:

first, step 1) of performing a surface modification process on the epitaxial cap layer 105 in an ICP chamber to form a surface modification layer (not shown in the figure); and then, performing step 2), performing plasma treatment on the modified epitaxial cap layer 105 in the same chamber to remove the surface modification layer, so as to realize etching of the epitaxial cap layer 105. That is, the present invention employs a chlorination + plasma process to achieve the etching of the epitaxial cap layer 105. Based on the atomic layer etching method (ALE), the epitaxial cap layer 105 can be etched without damage, the etching thickness is accurate and controllable, and compared with an ICP or RIE etching process, the damage of etching to materials is effectively relieved, so that the influence of etching damage on the grid function is avoided. The invention ensures the etching quality and thickness control of the grid electrode by removing the epitaxial cap layer and the subsequent barrier layer.

In addition, step 1) and step 2) are followed by step 3): and circularly performing the step 1) and the step 2) until the epitaxial cap layer 105 is removed, namely alternately performing chlorination-plasma treatment-chlorination-plasma treatment processes to realize one-layer etching of the material layer, and realizing the etching removal of the epitaxial cap layer 105 through multiple circulations, thereby being beneficial to preventing the over-etching of the material layer. In one example, the time for performing the chlorine modification treatment in step 1) is between 30s and 60s, such as 40s, 50s and the like, in each cycle, namely, each time of performing the processes of step 1) and step 2), so as to ensure that the GaN on the surface layer is modified to form a surface with Ga-Cl bonds; the plasma treatment in step 2) is performed for a time between 10s and 30s, for example, 12s, 15s, and 20s, and the etching thickness of the epitaxial cap layer 105 is less than 0.5nm, for example, 0.1nm, 0.2nm, and 0.3nm, so as to remove the modified Ga — Cl. By the process, atomic-level etching control can be realized on the gate opening, and etching after full chlorination is ensured.

Specifically, the barrier layer 104 includes an AlN layer, and the thickness of the barrier layer 104 is between 2nm and 5nm, and may be, for example, 2.5nm, 3nm, or 4 nm; the epitaxial cap layer 105 comprises a GaN layer, and the thickness of the epitaxial cap layer 105 is between 1nm and 3nm, and may be, for example, 1.5nm, 2nm, or 2.5 nm. In an example, in step 1), the surface modification treatment is performed by modifying the surface of the epitaxial cap layer 105 with chlorine gas, and the surface modification of the epitaxial cap layer 105 (such as a GaN layer or an AlGaN layer) is performed in the ICP chamber by using Cl2 gas instead of plasma Cl2 to form chloride, so as to reduce dissociation energy of chemical bonds (Ga-related bonds, such as Ga-N bonds) in the epitaxial cap layer 105, thereby significantly reducing plasma ion energy and bombardment of the GaN barrier by plasma, and reducing RF power of the plasma in step 2); in the step 2), the ions subjected to the plasma treatment include Ar ions. The process can accurately control the etching thickness, and cannot damage materials due to high-energy plasma bombardment. That is to say, based on the scheme of this application, through the cap layer after step 1) modification, can very easily get rid of the modified material layer through step 2), because material dissociation can reduce, and relative to traditional sculpture, traditional plasma sculpture needs plasma bombardment material surface to remove, can cause the damage to the material. Further, the barrier layer 104 is selected as an AlN layer, the epitaxial cap layer 105 is selected as a GaN layer, and the thickness of the epitaxial cap layer 105 can be designed to be between 1nm and 3nm, so that the material layer serves as a device structure foundation, and the performance of the epitaxial cap layer 105 can be improved through a surface modification and removal process. The chlorine modification can be carried out by introducing Cl2 gas into an ICP cavity, not applying RF power, so that no plasma gas exists in the cavity, the material is not bombarded, and only the surface of the material is modified. Different from the traditional Cl-based ICP etching, the material can not be damaged by plasma etching. For example, chlorine gas is ultimately acted upon in the form of chloride ions, i.e., a chemical reaction occurs, Cl2+ GaN- > Ga-Cl + NCl.

In a further alternative example, the source power in the ICP chamber in steps 1) and 2) is between 80W-120W, for example, may be 90W, 100W, 110W; the pressure in the ICP chamber is between 25mTorr and 35mTorr, and may be, for example, 28mTorr, 30mTorr, 32 mTorr; in step 2), the rf power of the plasma treatment is between 1W and 4W, for example, 1.5W, 2W, or 3W. By the above process, the dissociation energy of Ga-N bond can be significantly reduced by the surface chlorination process, therefore, the RF power of Ar plasma is very low (1-4W), and the corresponding self-bias tends to 0V, such as 0V.

In the example, step 1) and step 2) are both selected as ICP chambers, and both can be selected as the same chamber, without special ALE equipment or ALD equipment, and the process is performed in conventional etching equipment without additional purchase of other equipment. In one example, the source power in the ICP chamber is the same and the pressure in the ICP chamber is the same in step 1) and step 2). Wherein, in step 1) and step 2), the source power and the pressure are the same, then in step 2), the RF power is started to form plasma, and Ar plasma is used for removing the modified GaN layer. The power and the pressure in the step 1) and the step 2) are the same, the condition in the cavity can be stable, the step 1) and the step 2) can be integrated in the same process (recipe), the process is stable, and the repeatability is high. Therefore, stable parameters can be kept in the steps of circulating, the parameters do not need to be changed repeatedly, the disadvantages of equipment and the like caused by circulating change are prevented, the stability of the set parameters is also adversely affected, and a parameter change process and a parameter stabilizing process are needed for parameter adjustment. Therefore, the arrangement based on the scheme of the application can facilitate the process and save time.

Specifically, after the GaN epitaxial cap layer 105 is removed, the barrier layer 104 (e.g., AlN layer) is removed by using a wet selective process, where the wet etching is selective etching, stops on the surface of the GaN channel layer, is non-destructive etching, and is different from the conventional ICP plasma etching, and there is no material damage caused by plasma etching. Wherein the agent for removing the barrier layer 104 comprises at least one of KOH and AZ 400K. The two reagent etching can easily etch and remove AlN, stop on the surface of the GaN channel layer and have no damage to the surface of the material. In other words, the epitaxial cap layer 105 and the barrier layer 104 can be selectively etched without damage, so that the damage to the material is ensured, the control can be accurately performed, the GaN cap layer is etched by ALE, and the ALN barrier layer is etched by a wet method.

Next, as shown in S5 of fig. 1 and fig. 7, step S5 is performed to form a gate dielectric layer 114 on the surface of the semiconductor epitaxial structure 100, the gate dielectric layer between the first source 106 and the first drain 107 forms a first gate dielectric layer 114a, the first gate dielectric layer 114a further covers the bottom and the sidewall of the gate opening 113, and the gate dielectric layer between the second source 108 and the second drain 109 forms a second gate dielectric layer 114 b.

Illustratively, the gate dielectric layer 114 is formed using an atomic layer deposition process, and the gate dielectric layer includes a high-K dielectric layer, which is Al₂O₃、HfO₂、ZrO₂And BeO, and the like, and the thickness of the gate dielectric layer 114 is between 5nm and 50nm, for example, 8nm, 10nm, and 15 nm. In one example, the method further comprises the step of removing the patterned photoresist layer in the previous step and cleaning the surface of the material before depositing the gate dielectric layer 114.

In a preferred example, the gate dielectric layer 114 includes a BeO material layer, the deposition temperature of the BeO material layer is between 100 ℃ and 300 ℃, and the thickness of the BeO material layer is between 5nm and 50 nm. In this example, a layer of BeO material is used as the gate oxide, and in one example, the deposition conditions are in the temperature range of 100 deg.C-300 deg.C, which may be, for example, 150 deg.C, 180 deg.C, 200 deg.C. In one example, Be (CH) is utilized₃)₂And O₃As a gas source. In one example, the BeO material layer is deposited to a thickness of 5-50nm, e.g., selected from 10nm, 15nm, 20nm, 25nm, 30nm, 40nm, 45nm, etc.

The BeO obtained based on the mode is used as the gate oxide, and has the advantages of higher thermal conductivity (330W/Km), band gap energy (-11 eV) and dielectric constant (-7) compared with the conventional gate oxide layer such as SiO 2. In addition, diamond is the only material on earth with thermal conductivity exceeding BeO as an insulating material, so BeO can enhance the heat dissipation capability of GaN devices. BeO is used as gate oxide, and heat can be dissipated on the surface of the GaN and the grid in time through the BeO material. Based on the good heat dissipation characteristic of the BeO, heat sinks (such as diamond and graphene films) do not need to be additionally prepared on the surfaces of the devices, and the process is greatly simplified. Further, the BeO material layer is used as a gate oxide layer, so that additional polarization function can be provided in AlN/GaN HEMTs. BeO films exhibit strong spontaneous and piezoelectric polarization due to their non-centrosymmetric crystal structure. The formation of the 2DEG channel in AlN/GaN HEMTs is caused by polarization-induced hetero-interface charges. Therefore, when the BeO thin film is combined with the AlN/GaN heterojunction, the polarization field in the thin film can change the polarization of HEMTs, so that the 2DEG carrier density is improved, and the device performance is enhanced. Meanwhile, the structure of BeO/AlN/GaN and BeO/GaN enhances the polarization effect in the corresponding GaN channel, improves the carrier concentration and is beneficial to the electrical property optimization of the device. In addition, BeO gate oxide preparation is carried out through ozone O3, the quality of the BeO single crystal film can be ensured, and the conventional H is avoided₂O is used as a gas source to cause the film to be non-crystallized, thereby effectively inhibiting the leakage current of the grid electrode and being integrated with the formed natural oxide layer.

Illustratively, the step of forming the gate dielectric layer 114 further includes a step of forming a continuous native oxide layer (not shown) on the surface of the semiconductor epitaxial structure 100. The natural oxide layer can be an oxide thin layer with the thickness of 0.5nm-1nm, such as 0.6nm and 0.8nm, the natural oxide layer can be used as a transition medium, the interface quality of GaN-GaO is better because of natural oxidation, the interface between subsequent gate dielectric layers (such as BeO)/GaO oxide layers is also better, and the corresponding total interface defect is lower. In one example, the gate dielectric layer 104 is formed using an atomic layer deposition process (ALD) after the native oxide layer is formed, further resulting in good interface contact. In one example, ozone is used to form the native oxide layer. In a further alternative example, in the ALD chamber, ozone O3 is introduced to perform surface oxidation on the material to form a GaO thin layer, and then an atomic layer deposition process is used to form a gate dielectric layer (e.g., BeO deposition is performed again) in the same ALD chamber, preferably, the gate dielectric layer is formed by using O3 as an oxygen source. The surface oxidation treatment is carried out in the same ALD cavity, then the gate oxide deposition is directly carried out without leaving the cavity, the sample is prevented from being exposed to air, meanwhile, O3 is used as a gas source for depositing the gate oxide, the deposited gate oxide can be more compact, the defects in a gate medium are reduced, and the quality is better. And O3 used as an oxygen source in the gate dielectric layer and O3 used for forming the natural oxidation layer are the same gas, and the two-step process can be regarded as the same procedure, so that an oxygen-rich environment is formed in the ALD chamber, and the forming quality of the material film layer is improved. Meanwhile, the oxygen source is O3, H2O in the traditional process is replaced by the oxygen source, and the ALD chemical method using O3 as the oxygen source gas reduces hydroxyl impurities (OH-) and residual hydrogen (H), so that the oxygen layer body and interface traps are reduced.

Next, as shown in S6 of fig. 1 and fig. 8, step S6 is performed to form a first gate structure 115 on the surface of the first gate dielectric layer 114a to obtain a first device 117, where the first gate structure 115 at least fills the gate opening 113, and a second gate structure 116 is formed on the surface 114b of the second gate dielectric layer to obtain a second device 118. In the step, the gate structures of the two devices are prepared, namely the gates of the enhancement device and the depletion device are prepared simultaneously. In one example, the gates of the enhancement device and the depletion device can be defined by a photolithography process, and then metal is deposited and stripped to obtain the gate electrode. The metal material of the gate structure may be a gate electrode material commonly used in the art. In one example, the first device 117 is an enhancement mode device, the first gate structure 115 may be designed as a t-shaped structure, and fills the gate opening 113 after the first gate dielectric layer 114a is formed, and the second gate structure 116 may be designed as a square pillar.

Finally, as shown in S7 in fig. 1 and fig. 9, step S7 is performed to prepare an interconnection electrode structure to electrically connect the first device 117 and the second device 118. The invention prepares different devices on the same GaN epitaxial substrate, such as enhancement type and depletion type GaN devices, can realize the integration of the enhancement type GaN device and the depletion type GaN device, finally realizes the interconnection of the two devices on the same single wafer through metal interconnection, forms a functional module, forms an interconnection circuit on the single wafer, greatly reduces the parasitic effect generated by routing interconnection, and provides various possibilities for circuit design.

As an example, the step of preparing the interconnect electrode structure comprises: forming a dielectric passivation layer 119 on the semiconductor epitaxial structure 100 forming the first gate structure 115 and the second gate structure 116; forming an interconnection through hole in the dielectric passivation layer 119 by using a photolithography and etching process; and depositing metal in the interconnection through hole to form a metal connecting column 120, thereby obtaining the interconnection electrode structure. The material of the dielectric passivation layer 119 includes, but is not limited to, SiN, and the interconnection via defines an electrode interconnection position of the first device and the second device, which may be selected according to practical applications, as shown in fig. 9, in this example, the first drain electrode of the first device is electrically connected to the second source electrode of the second device, and the first source electrode and the second drain electrode are respectively electrically led out. The interconnect via can be fabricated using RIE dry etching.

The invention also provides an integrated GaN device, which is preferably prepared by the preparation method of the integrated GaN device, and can be prepared by other methods. For the structural features and the related descriptions of the integrated GaN device in this embodiment, reference may be made to the description of the integrated GaN device manufacturing method in this embodiment, which is not repeated herein. In this embodiment, the integrated GaN device includes:

a semiconductor epitaxial structure 100 including, from bottom to top, a semiconductor substrate 101, a GaN channel layer 103, a barrier layer 104, and an epitaxial cap layer 105;

a first source 106, a first drain 107, a second source 108 and a second drain 109 formed on the semiconductor epitaxial structure 100, wherein a gate opening 113 is formed in the epitaxial cap layer 105 between the first source 106 and the first drain 107 and the barrier layer 104 thereunder, and the gate opening 113 exposes the GaN channel layer 103;

a device isolation structure 110 extending from the epitaxial cap layer 105 into the GaN channel layer 103, isolating the first source electrode 106, the first drain electrode 107 from the second source electrode 108, the second drain electrode 109;

a gate dielectric layer 114 formed on the surface of the semiconductor epitaxial structure 100, including a first gate dielectric layer 114a located between the first source and the first drain, and a second gate dielectric layer 114b located between the second source and the second drain, wherein the first gate dielectric layer 114a further covers the bottom and the sidewall of the gate opening 113;

a first gate structure 115 and a second gate structure 116, wherein the first gate structure 115 is formed on the surface of the first gate dielectric layer 114a and at least fills the gate opening 113 to form a first device 117, and the second gate structure 116 is formed on the surface of the second gate dielectric layer 114b to form a second device 118; and

an interconnect electrode structure enabling electrical connection of said first device 117 with said second device 118.

Illustratively, the gate dielectric layer 114 includes a high-K dielectric layer, and the thickness of the gate dielectric layer 114 is between 5nm and 50 nm.

By way of example, the gate dielectric layer includes a BeO material layer.

By way of example, the interconnect electrode structure includes a dielectric passivation layer 119 formed on the epitaxial structure and a metal connection stud 120 formed in the dielectric passivation layer.

Illustratively, the barrier layer 104 comprises an AlN layer, and the barrier layer 104 has a thickness of between 2nm and 5 nm.

Illustratively, the epitaxial cap layer 105 comprises a GaN layer, and the thickness of the epitaxial cap layer 105 is between 1nm and 3 nm.

As an example, a natural oxide layer is further formed between the epitaxial structure and the gate dielectric layer.

In summary, the present invention provides an integrated GaN device and a method for manufacturing the same, in which a first device and a second device are effectively integrated on the same semiconductor epitaxial substrate, and a plurality of feasible designs are provided for circuit design, thereby facilitating circuit design and interconnection, and reducing parasitic and cost by not preparing an independent discrete device, and finally performing wire bonding connection, for example, an enhancement device and a depletion device, thereby realizing a CMOS function such as a Si device, and expanding the application range of the GaN device. According to the invention, through process design, except for etching of the grid opening of the first device, other steps are simultaneously carried out, the process difficulty is not increased, the process is simple and convenient, the cost is low, and the subsequent packaging cost is saved while the overall performance of the device is improved. The etching of the epitaxial cap layer and the barrier layer in the process of forming the gate opening can be controlled better in etching precision by adopting a step-by-step etching process, and meanwhile, the damage of the traditional dry ion beam etching to the material is avoided by adopting wet etching, and the process cost is lower. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.