Apparatus and method for sub-array addressing
阅读说明：本技术 用于子阵列寻址的设备及方法 (Apparatus and method for sub-array addressing ) 是由 G·E·胡申 R·C·墨菲 于 2018-12-10 设计创作，主要内容包括：本发明描述涉及用于电子存储器及/或存储装置的子阵列寻址的系统、设备及方法。可经由独立子阵列寻址而实现对不同子阵列内的不同行的同时存取,使得所述子阵列中的每一者可用作“虚拟存储体”。如此存取所述不同行可提供对从相应行存取的数据值被发送到目的地位置的经改进吞吐量。举例来说,一个此种设备包含在存储器装置的存储体内的多个子阵列。所述存储体内的电路耦合到所述多个子阵列。所述电路可经配置以在一时间周期期间激活第一子阵列中的特定序数位置处的行且在同一时间周期期间激活所述多个子阵列中的第二子阵列中的不同序数位置处的行。(Systems, apparatuses, and methods related to sub-array addressing for electronic memories and/or storage devices are described. Simultaneous access to different rows within different sub-arrays may be achieved via independent sub-array addressing, so that each of the sub-arrays may be used as a "virtual bank. Such access to the different rows may provide improved throughput for data values accessed from the respective rows to be sent to the destination location. For example, one such apparatus includes a plurality of sub-arrays within a bank of a memory device. Circuitry within the memory banks is coupled to the plurality of sub-arrays. The circuit may be configured to activate a row at a particular ordinal position in a first subarray during a period of time and to activate a row at a different ordinal position in a second subarray of the plurality of subarrays during the same period of time.)
1. An apparatus, comprising:
a plurality of sub-arrays within a bank of a memory device; and
circuitry coupled to the plurality of sub-arrays and configured to:
activating a row at a particular ordinal position in a first subarray of the plurality of subarrays during a period of time; and
activating rows at different ordinal positions in a second subarray of the plurality of subarrays during the time period.
2. The apparatus of claim 1, wherein the circuit comprises:
a subarray decoder whose output is independently latched in a subarray latch circuit for each subarray, the latched output indicating an activation state of the corresponding subarray; and
a row decoding circuit, comprising:
a row latch circuit per sub-array to independently latch received row addresses on a per sub-array basis; and
a row decoder per subarray each configured to receive:
an output of the sub-array latch circuit corresponding to the sub-array; and
the output of the row latch circuit corresponding to the sub-array.
3. The apparatus of claim 2, wherein the circuit further comprises:
a first subarray latch circuit and a first row latch circuit selectably coupled to the first subarray; and
a second subarray latch circuit and a second row latch circuit selectably coupled to the second subarray;
wherein the first latch circuit and the second latch circuit are configured to enable independent subarray access and the row activation during the time period.
4. The apparatus of claim 1, wherein the circuit comprises:
a first row decoder coupled to the first sub-array;
a second row decoder coupled to the second sub-array; and
a sub-array decoder coupled to the first row decoder via a first latch and to the second row decoder via a second latch.
5. The apparatus of claim 4, further comprising:
a row address circuit that:
coupled to the first row decoder via a third latch; and is
Coupled to the second row decoder via a fourth latch.
6. The apparatus of any one of claims 1-5, further comprising:
first sensing circuitry coupled to the first subarray and second sensing circuitry coupled to the second subarray, the first and second sensing circuitry each including a sense amplifier coupled to a respective sense line;
wherein the first sensing circuitry and the second sensing circuitry are physically separate from the circuitry configured to enable the row activation during the time period.
7. The apparatus of any one of claims 1-5, wherein, based on different subarray addresses, the row at the particular ordinal position and the row at the different ordinal positions are configured to be activated during the period of time.
8. The apparatus of any of claims 1-5, wherein, based on different subarray addresses directing activation of the row at the particular ordinal position and the row at the different ordinal positions, sensing circuitry coupled to the first subarray is configured to sense the activated row at the particular ordinal position and sensing circuitry coupled to the second subarray is configured to sense the activated row at the different ordinal positions.
9. A system, comprising:
a memory device comprising a plurality of sub-arrays of memory cells in a bank;
a host configured to provide subarray addressing commands to the memory device;
a control bus between the host and the memory device over which signals of the subarray addressing command are moved from the host to the memory device to achieve simultaneous storage as follows:
storing, by a first sense amplifier, a first data value sensed at a particular ordinal position of a row of a first subarray of the memory device; and
second data values sensed at different ordinal positions of rows of a second subarray of the memory device are stored by a second sense amplifier.
10. The system of claim 9, wherein:
the memory device is configured to receive the subarray addressing command from the host via the control bus; and is
The sub-array addressing commands include:
a first subarray address signal corresponding to the first subarray and a second subarray address signal corresponding to the second subarray; and
a first row address signal corresponding to the particular ordinal position of the row of the first subarray and a second row address signal corresponding to the different ordinal position of the row of the second subarray.
11. The system of claim 9, further comprising:
a subarray decoder configured to decode different subarray address signals included in the subarray addressing command received from the host for selecting a different subarray;
a sub-array address latch circuit that enables selection of a different sub-array based on the different sub-array address signal;
a first subarray address signal sent from the subarray decoder, stored by a first subarray latch circuit coupled to the first subarray, for selecting the first subarray; and
a second subarray address signal sent from the subarray decoder, which is stored by a second subarray latch circuit coupled to the second subarray for selecting the second subarray.
12. The system of any one of claims 9 to 11, further comprising:
a row address latch circuit configured to store different row address signals included in the subarray addressing command received from the host for selecting different rows of the different subarrays;
a row decoder circuit configured to decode the different row address signals to enable selection of the different rows in the different subarrays based on the different row address signals;
a first row latch circuit coupled to the first subarray to store a first signal sent from the row address latch circuit to activate the row at the particular ordinal position of the first subarray;
a first row decoder coupled to the first subarray and configured to decode the first signal sent from the first subarray latch circuit for selecting the first subarray and decode a first signal sent from the first row latch circuit for selecting the row at the particular ordinal position of the first subarray;
a second row latch circuit coupled to the second subarray to store a second signal sent from the row address latch circuit to activate the row at the different ordinal position of the second subarray; and
a second row decoder coupled to the second subarray and configured to decode the second signal sent from the second subarray latch circuit for selecting the second subarray and decode the second signal sent from the second row latch circuit for selecting the row at the different ordinal position of the second subarray.
13. The system of any one of claims 9 to 11, further comprising:
a controller of the memory device configured to:
receiving the sub-array addressing commands from the host via the control bus; and
directing simultaneous storage as follows: storing the first data value from the row of the first subarray by the first sense amplifier and the second data value from the row of the second subarray by the second sense amplifier.
14. The system of any one of claims 9 to 11, further comprising:
a controller of the memory device;
input/output (I/O) circuitry configured to enable input of data for storage by the memory device and output of data accessed in the memory device; and
a data bus between the host and the memory device configured to move data from the host for the storing and to move the accessed data to the host;
wherein the control bus is coupled to the controller and the data bus is coupled to the I/O circuitry.
15. The system of any one of claims 9 to 11, further comprising:
a data bus between the host and the memory device configured to move data accessed in the memory device to the host; and
a processor coupled to the host;
wherein the data bus moves the first data value accessed from the row of the first subarray and the second data value accessed from the row of the second subarray to enable data processing of the first and second data values by the processor to the memory device via the control bus in response to the subarray addressing command.
16. A method for operating a memory device, comprising:
receiving an address signal by a subarray decoder within a bank of the memory device; and
directing circuitry coupled to a plurality of sub-arrays in response to the address signals:
activating a row at a particular ordinal position in a first subarray of the plurality of subarrays during a first time period; and
activating rows at different ordinal positions in a second subarray of the plurality of subarrays during the first time period.
17. The method of claim 16, further comprising addressing the row in the first subarray and the row in the second subarray with a row address corresponding to the particular ordinal position in the first subarray and a different row address corresponding to the different ordinal position in the second subarray via the address signal.
18. The method of claim 16, further comprising:
during the first time period, activating the row at the particular ordinal position in the first subarray and activating the row at the different ordinal position in the second subarray and thereby;
reducing latency between sensing a first data value stored in the row at the particular ordinal position in the first subarray and sensing a second data value stored in the row at the different ordinal position in the second subarray relative to;
switching from activating the row at the particular ordinal position in the first and second subarrays to activating the row at the different ordinal position in the first and second subarrays.
19. The method of any one of claims 16-18, further comprising:
directing, via a signal from a controller, coupling a shared I/O line to sensing circuits of the first sub-array and to sensing circuits of the second sub-array and thereby in a second time period;
increasing throughput capability of the shared I/O line for data values stored in the row at the particular ordinal position in the first subarray and the row at the different ordinal position in the second subarray via increasing relative to;
activating the row at the particular ordinal position in the first subarray and the second subarray and coupling the sensing circuits of the first subarray and the sensing circuits of the second subarray to the shared I/O line, followed by;
activating the row at the different ordinal position in the first subarray and the second subarray and recoupling the sensing circuits of the first subarray and the sensing circuits of the second subarray to the shared I/O line.
20. The method of any one of claims 16-18, further comprising:
moving, in a physical bank of the memory device, a first data value stored in the row at the particular ordinal position in the first subarray and a second data value stored in the row at the different ordinal position in the second subarray;
wherein the address signals include addressing the first subarray with a particular subarray address and addressing the second subarray with a different subarray address to form a virtual memory bank.
Technical Field
The present disclosure relates generally to semiconductor memories and methods, and more particularly, to apparatus and methods for sub-array addressing.
Background
Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic systems. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data (e.g., host data, error data, etc.) and includes Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Synchronous Dynamic Random Access Memory (SDRAM), and Thyristor Random Access Memory (TRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered, and can include NAND flash memory, NOR flash memory, and resistance variable memory, such as Phase Change Random Access Memory (PCRAM), Resistive Random Access Memory (RRAM), and Magnetoresistive Random Access Memory (MRAM), such as spin torque transfer random access memory (sttram), among others.
Electronic systems typically include a number of processing resources (e.g., one or more processors) that can retrieve and execute instructions and store the results of the executed instructions in a suitable location. A processor may include a number of functional units, such as Arithmetic Logic Unit (ALU) circuitry, Floating Point Unit (FPU) circuitry, AND combinatorial logic blocks, for example, that may be used to execute instructions by performing logical operations on data (e.g., one OR more operands), such as AND, OR, NOT, NAND, NOR, AND XOR, as well as inverting (e.g., negating) logical operations. For example, functional unit circuitry may be used to perform arithmetic operations on operands, such as addition, subtraction, multiplication, and division, through a number of logical operations.
In many examples, the processing resource may be external to the memory array, and data is accessed via a bus between the processing resource and the memory array to execute a set of instructions. However, accessing data and/or moving such data within a bank of a memory device or from the bank to a processor external to the memory device may affect the time for data processing.
Drawings
FIG. 1A is a block diagram of an apparatus in the form of a computing system including a memory device, according to a number of embodiments of the invention.
FIG. 1B is a block diagram of a bank section of a portion of a memory device, according to a number of embodiments of the invention.
FIG. 2 is a schematic diagram of a portion of a memory device, according to several embodiments of the invention.
FIG. 3 is a schematic diagram illustrating circuitry for sub-array addressing according to several embodiments of the invention.
Fig. 4A and 4B are schematic diagrams illustrating circuits for data movement, according to a number of embodiments of the disclosure.
Fig. 5 is a flow diagram for sub-array addressing according to several embodiments of the invention.
Detailed Description
The present disclosure includes systems, apparatuses, and methods associated with sub-array addressing. In a number of embodiments, an apparatus includes a plurality of sub-arrays within a bank of a memory device. The apparatus further includes circuitry within the bank coupled to the plurality of subarrays and configured to activate a row at a particular ordinal position in a first subarray of the plurality of subarrays during a period of time and to activate a row at a different ordinal position in a second subarray of the plurality of subarrays during the period of time.
Implementations of address circuitry (e.g., for DRAM configurations utilizing protocols such as DDR3, DDR4, etc.) may be configured to activate only one particular row at a time (e.g., per write/read cycle) within a subarray bank of memory cells. This can lead to various drawbacks, such as not having the ability to activate/access different rows (e.g., rows at different ordinal positions) in different subarrays at the same time.
For example, implementation of addressing utilizing such address circuits and/or protocols may be performed by: the row at a particular ordinal position in a first subarray of the bank is addressed using a first address signal which simultaneously addresses the row at the same ordinal position in a second subarray of the bank. The second address signal may be used to switch from activation of a row at a particular ordinal position in the first and second subarrays to activation of a row at a different ordinal position in the first and second subarrays. When only data values from rows at particular ordinal positions in the first subarray and rows at different ordinal positions in the second subarray are intended to be accessed (e.g., for data processing), for example, the deactivation of a row at a particular ordinal position in the first and second subarrays of a bank may be unnecessarily slow and/or inefficient followed by the activation of a row at a different ordinal position in the first and second subarrays (achieved by the second address signal).
In contrast, several embodiments of the present disclosure describe activating a row at a particular ordinal position in a first subarray during a period of time and activating a row at a different ordinal position in a second subarray (e.g., within the same bank) during the same period of time. For example, as described herein, a row at a particular ordinal position in a first subarray may be activated during the time period without activating a row at a particular ordinal position in a second subarray, and a row at a different ordinal position in the second subarray may be activated during the same time period without activating a row at a different ordinal position in the first subarray. Relative to implementations consistent with the implementations presented above, activating a row at a particular ordinal position in a first subarray and a row at a different ordinal position in a second subarray during the same time period may enable a reduced latency between sensing circuitry (e.g., read/latch circuitry) that senses a first data value stored in the row at the particular ordinal position in the first subarray and read/latch circuitry that senses a second data value stored in the row at the different ordinal position in the second subarray. The following operations may be performed during the same time period: an I/O line is coupled to the read/latch circuitry of the first subarray to move data values stored by activated rows at particular ordinal positions, and an I/O line is coupled to the read/latch circuitry of the second subarray to move data values stored by activated rows at different ordinal positions.
Several embodiments of the present invention can provide various benefits due to, for example, independent sub-array addressing enabling access to different rows in different sub-arrays of a bank within a particular time period (e.g., simultaneously). Such independent access of the different sub-arrays and rows may allow each of the sub-arrays to be used as a "virtual bank," relative to other protocol implementations (e.g., various DDR protocols that do not provide the ability to access different rows in different sub-arrays simultaneously).
Such benefits may include improved throughput (e.g., increased speed, rate, and/or efficiency) associated with accessing (e.g., reading, writing, etc.) different rows within different sub-arrays of a bank of a memory device. For example, embodiments of the present disclosure may provide reduced latency associated with moving data from subarrays to data input/output (I/O), which may increase system processing speed (e.g., by providing increased throughput of processing resources).
The figures herein follow a numbering convention in which the first digit or digits of a reference number correspond to the figure number and the remaining digits identify an element or component in the figure. Similar elements or components between different figures may be identified by the use of similar digits. For example, 130 may refer to element "30" in fig. 1A, and a similar element may be referred to as 230 in fig. 2.
FIG. 1A is a block diagram of an apparatus in the form of a computing system 100 including a memory device 120, according to a number of embodiments of the invention. System 100 may be a laptop computer, a tablet computer, a personal computer, a digital camera, a digital recording and playback device, a mobile phone, a Personal Digital Assistant (PDA), a memory card reader, an interface hub, a sensor, an internet of things (IoT) -enabled device, and other systems. As used herein, the memory device 120, the
As described in more detail below, embodiments may allow the computing system 100 to allocate a number of locations (e.g., sub-arrays) in a bank to hold (e.g., store) data. Embodiments of a bank including multiple sub-arrays are shown at 121 and 321 and described in connection with fig. 1B and 3, respectively, although other configurations are within the scope of the invention. A host (e.g., as shown at 110) and/or a controller (e.g., as shown at 140) can perform address resolution on instructions (e.g., commands associated with executing a program) and entire blocks of data and direct (e.g., control) allocation and storage of data and commands into allocated locations within a bank (e.g., sub-arrays and portions of sub-arrays) and/or to external destinations.
In a number of embodiments, read and/or write data and associated commands can utilize data paths and timing in DRAM devices based on pre-existing protocols (e.g., DDR3, DDR4, etc.). In contrast, the circuits and/or address signals described herein for sub-array addressing and timing and/or associated with data movement (e.g., to a destination location for processing) have not previously been implemented. As used herein, data movement is an inclusive term that includes, for example, copying, transferring, and/or transporting data values from a source location to a destination location. As the reader will appreciate, although DRAM-type memory devices are discussed with respect to the examples presented herein, embodiments are not limited to DRAM implementations.
The speed, rate, and/or efficiency of data movement for subarray addressing, data access (e.g., to and from read/latch circuitry), and/or within a bank (e.g., from a subarray and portions of a subarray therein and/or a controller) may affect whether a data processing operation is completed (performed) efficiently. Accordingly, the present disclosure presents structures and processes that can increase the speed, rate, and/or efficiency of sub-array addressing, data access, and/or associated data movement in a bank and/or to a processor through the use of improved sub-array addressing circuits and address signals, which can facilitate the use of improved data path throughput capabilities (as compared to previous approaches).
In a number of embodiments, a row of virtual address space in a memory device (e.g., as shown at 120 in FIG. 1A) (e.g., as shown at 119 in FIG. 1B and at corresponding reference numbers elsewhere herein) can have a bit length of 16K bits (e.g., corresponding to 16,384 memory cells or complementary pairs of memory cells in a DRAM configuration). Read/latch circuitry for such a 16K bit row (e.g., as shown at 150 in fig. 1A and corresponding reference numbers elsewhere herein) can include corresponding 16K sense amplifiers and associated circuitry formed co-spaced with sense lines (e.g., as shown at 206 in fig. 2 and corresponding reference numbers elsewhere herein) that can be selectively coupled to corresponding memory cells in the 16K bit row. Sense amplifiers in the memory device can be operated as a cache memory for a single data value (bit) from a row of memory cells sensed (e.g., sensed by and/or stored in the sense amplifiers) by read/latch circuitry 150.
Several embodiments of the present invention include read/latch circuitry (e.g., sense amplifier 206 and associated circuitry) that can be formed co-spaced with sense lines of a memory cell array. The read/latch circuits and other data storage components described herein are capable of performing data sensing and/or storage (e.g., caching, latching, buffering, etc.) of data local to an array of memory cells.
To appreciate the improved subarray addressing and associated data movement techniques described herein, apparatus (e.g., memory devices 120 and associated hosts 110 with these capabilities) for implementing such techniques are subsequently discussed. According to various embodiments, program instructions (e.g., commands) relating to memory devices with sub-array addressing and associated data movement capabilities described herein may distribute implementations of commands (e.g., address signals) and data across multiple read/latch and sub-array addressing circuits that may implement operations and that may move and store commands and data within a memory array (e.g., without transferring such commands and data back and forth between a host and a memory device over a bus). Thus, data of a memory device with subarray addressing and associated data movement capabilities may be accessed and used in less time and with less power. For example, time and power advantages may be achieved by: the speed, rate, and/or efficiency of moving and storing data throughout a computing system is increased in order to process requested memory array operations (e.g., reads, writes, logical operations, etc.) at a destination location.
The system 100 may include a host 110 coupled (e.g., connected) to a memory device 120, including a memory array 130 and a
The controller 140 (e.g., bank control logic and sequencer) may include control circuitry in the form of hardware, firmware, or software, or a combination thereof. As an example, the
For clarity, the description of the system 100 has been simplified to focus on features of particular relevance to the present invention. For example, the array 130 may be a DRAM array, SRAM array, STT RAM array, PCRAM array, TRAM array, RRAM array, FeRAM array, phase change memory array, 3DX dot array, NAND flash array, and/or NOR flash array (for example). The memory array 130 may include memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines (which may be referred to herein as data lines or digit lines). Although a single bank 121 and a single memory array 130 are shown in FIG. 1A, embodiments are not so limited. For example, memory device 120 may represent a plurality of banks 121 that may each include, in addition to a plurality of sub-arrays, a plurality of memory arrays 130 (e.g., memory arrays included in a number of banks of DRAM cells, NAND flash cells, etc.), as described herein. Accordingly, the description in this disclosure may be made with respect to a DRAM architecture by way of example and/or clarity. However, unless expressly stated otherwise, the scope of the present invention and claims is not limited to DRAM architectures.
The memory device 120 may include address circuitry 142 to latch address signals provided by the I/O circuitry 144 (e.g., to external ALU circuitry and DRAM DQs via local I/O lines and global I/O lines) via a data bus 156 (e.g., an I/O bus from the host 110). Status and exception information may be provided from
The
FIG. 1B is a block diagram of a
The bank 121 or
Each
FIG. 2 is a schematic diagram of a portion of a memory device, according to several embodiments of the invention. FIG. 2 illustrates an example including 1T1C memory cells in a folded DRAM configuration each coupled to a sense amplifier 206. Embodiments, however, are not so limited so that some embodiments may have memory cells configured in 2T2C DRAM.
In the embodiment illustrated in FIG. 2, the memory array 230 is an array of memory cells (e.g., a DRAM array) that may each include an access device 202 (e.g., a transistor) and a storage element 203 (e.g., a capacitor). The memory cells of memory array 230 can be arranged in rows (as shown at 119 in FIG. 1B, 319 in FIG. 3, and 419-1 and 419-2 in FIGS. 4A and 4B) coupled by access lines 204-X (row X), 204-Y (row Y), etc., and columns coupled by complementary sense lines to numbers (n-1)/numbers (n-1) _, numbers (n)/numbers (n) _, and numbers (n + 1)/numbers (n +1) _ etc. The individual sense lines corresponding to each pair of complementary data lines may be referred to as sense line 205-1 (number (n)) and 205-2 (number (n) _), respectively. Although only three pairs of complementary sense lines are shown in FIG. 2, embodiments of the invention are not so limited, and the memory cell array can include additional columns of memory cells and/or sense lines (e.g., 4,096, 8,192, 16,384, etc.). As shown in FIG. 2, the gate of a particular memory cell transistor 202 can be coupled to its corresponding access line 204-X, 204-Y, etc., a first source/drain region can be coupled to its corresponding sense line (e.g., 205-1 (number (n)), 205-2 (number (n) _), and a second source/drain region of the particular memory cell transistor can be coupled to its corresponding capacitor 203.
The memory cells can be coupled to different sense lines and/or access lines. For example, a first source/drain region of transistor 202-1 can be coupled to sense line 205-1, a second source/drain region of transistor 202-1 can be coupled to capacitor 203-1, and the gate of transistor 202-1 can be coupled to access line 204-Y. A first source/drain region of transistor 202-2 may be coupled to sense line 205-2, a second source/drain region of transistor 202-2 may be coupled to capacitor 203-2, and a gate of transistor 202-2 may be coupled to access line 204-X. A cell plate as shown in fig. 2 may be coupled to each of capacitors 203-1 and 203-2. The cell plates may be a common node to which a reference voltage (e.g., ground) may be applied in various memory array configurations.
As described herein, the transistor 202 and the capacitor 203 can facilitate formation of a complementary pair of memory cells coupled to complementary sense lines (e.g., sense lines 205-1 and 205-2) in a single row of the memory array 230. The number of data values (e.g., voltages) sensed from the memory cells (e.g., in a read operation) may correspond to the number of columns of memory cells and/or pairs of sense lines (e.g., 4,096, 8,192, 16,384, etc.) that intersect the rows of subarray 125 shown in, for example, fig. 1B and described in connection with fig. 1B.
The memory array 230 illustrated in fig. 2 is coupled to read/latch circuitry (e.g., as shown at 150 in fig. 1A and 1B and described in connection with read/latch stripe 124). In a number of embodiments, the read/latch circuitry can include sense amplifiers 206 corresponding to respective columns of memory cells (e.g., coupled to respective pairs of complementary data lines 205-1, 205-2). The sense amplifier 206 is operable to determine a data value (e.g., a logic state) stored in a selected memory cell. The sense amplifier 206 may include cross-coupled latches (not shown). Sense amplifier 206 may be coupled to a balancing circuit (not shown) that may be configured to balance sense lines 205-1 and 205-2.
FIG. 3 is a schematic diagram illustrating circuitry for sub-array addressing according to several embodiments of the invention. As described herein, an apparatus (e.g., computing system 100 shown in fig. 1A) may include a plurality of sub-arrays (e.g., as shown at 325-0, 325-1,. eta., 325-N-1) within a bank 321 of memory device 120. The apparatus may further include circuitry within bank 321 (as shown in fig. 3) that may be coupled to the plurality of subarrays and configured to activate a row (e.g., selected from row 319) at a particular ordinal position in a first subarray (e.g., 325-0) of the plurality of subarrays during a period of time and to activate a row (e.g., selected from row 319) at a different ordinal position in a second subarray (e.g., 325-N-1) of the plurality of subarrays during the same period of time.
The rows may each include a plurality of memory cells corresponding to (e.g., coupled to) respective columns 322 (e.g., as shown and described in connection with fig. 2). In a number of embodiments, each subarray of the plurality of memory cells may include a same number of rows. For example, rows 319 in respective subarrays 325-0, 325-1, 325-N-1 may each be 1024 rows. A first subarray and a second subarray among the plurality of subarrays may be physically separated by read/latch circuitry (e.g., as shown at 150 in fig. 1A, 124 in fig. 1B, and 450 in fig. 4A and 4B). The read/latch circuitry may include a plurality of sense amplifiers and associated circuitry (e.g., as shown at 206 in fig. 2 and 406 in fig. 4A and 4B) coupled to a respective plurality of columns 322.
In a number of embodiments, bank 321 can include a controller (e.g., as shown at 140 in fig. 1A and 1B) configured to provide signals to write data to and read data from a plurality of sub-arrays. The
Subarray decoder 373 may output signals that may be latched in subarray latch circuits (e.g., 375-0, 375-1,... gtoreq., 375-N-1) independently for each subarray 325-0, 325-1,. gtoreq., 325-N-1. The latched signal may indicate an activation state of the corresponding subarray. For example, a signal value of 1 latched to sub-array latch 375-0 may indicate that sub-array 325-0 is activated in response to receiving a signal value of 1, while a signal value of 0 latched to sub-array latch 375-N-1 may indicate that sub-array 325-N-1 is not activated.
The circuitry illustrated in FIG. 3 may also include row decode circuitry. In a number of embodiments, the address circuitry may include row latch circuitry (e.g., 377-0, 377-1, 377-N-1) per sub-array to independently latch row address signals (e.g., received from row address latch circuitry 378, as directed by
Thus, the circuit may, for example, include a first sub-array latch circuit 375-0 and a first row latch circuit 377-0 selectably coupled to the first sub-array 325-0 and a second sub-array latch circuit 375-N-1 and a second row latch circuit 377-N-1 selectably coupled to the second sub-array 325-N-1. The first and second latch circuits 375-0, 377-0, 375-N-1, 377-N-1 may be configured to enable independent sub-array and row activation and/or access during the same time period. The circuit may also, for example, include a first row decoder 379-0 coupled to the first subarray 325-0, a second row decoder 379-N-1 coupled to the second subarray 379-N-1, and a subarray decoder 373 coupled to the first row decoder 379-0 via a first latch (e.g., subarray latch circuit 375-0) and to the second row decoder 379-N-1 via a second latch (e.g., subarray latch circuit 375-N-1). The circuitry may also, for example, include a row address circuit (e.g., including a row address latch circuit 378) coupled to the first row decoder 379-0 via a third latch (e.g., row latch circuit 377-0) and coupled to the second row decoder 379-N-1 via a fourth latch (e.g., row latch circuit 377-N-1).
The circuit illustrated in connection with FIG. 3 and just described is different and physically separate from the read/latch circuit shown at 150 in FIG. 1A and at 450 in FIGS. 4A and 4B. For example, a first read/latch circuit may be coupled to a first subarray 325-0 and a second (e.g., different) read/latch circuit may be coupled to a second subarray 325-N-1. However, the first read/latch circuit and the second read/latch circuit may be physically separate from the circuitry illustrated and described in connection with FIG. 3 that is configured to effect the row activation during the time period.
First subarray 325-0 and second subarray 325-N-1 may be addressed with different subarray addresses (e.g., sent from
The circuitry illustrated in FIG. 3 may include a sub-array address latch circuit 374 that may latch a received sub-array address (e.g., an address signal sent from the host 110 and/or the controller 140). The latched subarray address may be decoded via subarray decoder 373. In the example shown in FIG. 3, the subarray address is used to select 64 (e.g., 2)6) A 6-bit address of one of the sub-arrays (e.g., 325-0 to 325-63). Thus, the sub-array address latch circuit 374 can store (e.g., latch) different sub-array addresses for the first and second sub-arrays. In a number of embodiments, as described herein, more than two subarray addresses may be latched by subarray address latch circuit 374 to activate more than two subarrays during the same time period (e.g., in addition to activating a different row in each activated subarray).
The output of sub-array decoder 373 may be provided to sub-array latches 375-0 through 375-N-1 that are configured to latch an indication of whether the respective sub-array is activated (or not activated) during a particular address access cycle. For example, in this example, sub-array latches 375-0-375-N-1 may each comprise a single latch whose value (e.g., "1" or "0") indicates whether the corresponding sub-array is activated. The outputs of the sub-array latches 375 may be provided to corresponding respective row decoders 379-0-379-N-1.
The row address latch circuit 378 is configured to latch a received row address (e.g., a row address signal provided from the host 110 and/or the controller 140). The latched row address may be stored (e.g., latched) in respective latches of the row latch circuits 377-0 to 377-N-1 and may be decoded via the row decoders 379-0 to 379-N-1. In thatIn the example shown in FIG. 3, the row address is for selecting 1024 (e.g., 2)10) A 10-bit address of one of the rows (e.g., each subarray comprising 1024 rows 319). Thus, the row address latch circuit 378 may store (e.g., latch) a different row address for the sub-array to be accessed.
As an example, a first row latch circuit 377-0 coupled to the first subarray 325-0 (e.g., via a first row decoder 379-0) may latch a first row address provided by the row address latch circuit 378 to activate a row at a corresponding particular ordinal position within the first subarray. A second row latch circuit 377-N-1 coupled to the second subarray 325-N-1 (e.g., via a second row decoder 379-N-1) may latch a second (e.g., different) row address provided by the row address latch circuit 378 to activate rows at corresponding different ordinal positions within the second subarray. In contrast to some previous approaches in which the same row address is provided to all row decoders corresponding to a particular bank (e.g., such that rows at different ordinal positions in different subarrays cannot be activated simultaneously during a particular subarray access cycle), the row latch circuits 377-0 to 377-N-1 provide the ability to independently latch different row addresses on a per subarray basis.
The row decoders 379-0-379-N-1 are configured to decode the latched rows provided by the respective row latch circuits 377-0-377-N-1 (e.g., to select one of the 1024 rows 319 to activate). In an example, a first row decoder 379-0 can be coupled to the first subarray 325-0 and can be configured to decode a first subarray selection signal sent from a corresponding subarray latch circuit 375-0 and decode a first row address sent from a corresponding row latch circuit 377-0 to select a row at a particular ordinal position of the first subarray 325-0. A second row decoder 379-N-1 may be coupled to the second subarray 325-N-1 and may be configured to decode a second subarray selection signal sent from a corresponding subarray latch circuit 375-N-1 and decode a second address sent from a corresponding row latch circuit 377-N-1 to select rows at different ordinal positions of the second subarray 325-N-1.
In response to the first row decoder 379-0 decoding the first signal to select the first subarray and the row at a particular ordinal position of the first subarray and the second row decoder 379-N-1 decoding the second signal to select the second subarray and the row at a different ordinal position of the second subarray, the first and second subarrays along with the different rows in each subarray may be activated during the same time period. Activation of the appropriate row in each sub-array may be accomplished, for example, by 1024 signal lines coupled to the respective 1024 rows in each sub-array, as indicated by the numeral 1024 associated with the line connecting each of the row decoders 379-0,...., 379-N-1 with the respective sub-array 325-0,..., 325-N-1. In a number of embodiments, more than two rows and more than two corresponding subarrays may be activated during the same time period, as described herein.
In a number of embodiments, the sub-array address latch circuits 374 and/or the row address latch circuits 378 can be physically associated with (e.g., part of and/or coupled to) address circuitry utilized when performing read/write DRAM operations (e.g., shown at 142 and described in connection with FIG. 1A). In a number of embodiments, in addition to or as an alternative to circuitry for other implementations in which subarray addressing may be performed by addressing rows at a particular ordinal position in a first subarray using address signals that simultaneously address rows at the same ordinal position in a second subarray, subarray decoder 373 and/or row decoder 379 may be circuitry configured to perform subarray addressing operations and row addressing operations, respectively, as described herein. However, the sub-array latch circuits per sub-array (e.g., 375-0, 375-1, 377.., 375-N-1) and/or the row latch circuits per sub-array (e.g., 377-0, 377-1, 377.., 377-N-1) shown in FIG. 3 represent circuits that are utilized separately from and/or not in association with the circuits used for other implementations, as they do not, for example, utilize appropriate address signals to address different positioned rows in different sub-arrays simultaneously and/or individually.
In a number of embodiments, the
The
Fig. 4A and 4B provide schematic diagrams illustrating circuitry for data movement, according to a number of embodiments of the disclosure. As illustrated in FIGS. 1A and 1B and shown in greater detail in FIGS. 4A and 4B, the bank 121 or
Fig. 4A and 4B, which are considered to be connected horizontally, illustrate that each subarray (e.g., subarray 425-0 shown partially in fig. 4A and partially in fig. 4B) may have a number of associated sense amplifiers 406-0, 406-1. For example, each sub-array 425-0, 425-N-1 may have one or more associated read/latch stripes (e.g., 124-0,.., 124-N in fig. 1B). In a number of embodiments, each sub-array 425-0,.., 425-N-1 may be divided into a number of portions 462-1 (shown in FIG. 4A), 462-2,.., 462-M (shown in FIG. 4B). Portions 462-1, 455-2, 455-M may be defined by configuring a predetermined number of sense amplifiers (e.g., read/latch circuit 450) along with corresponding columns (e.g., 422-0, 422-1, 455-7 out of columns 422-0, 455-1) to a given shared I/O line (e.g., 455-1, 455-2, 455-M).
In some embodiments, as shown in fig. 4A and 4B, the predetermined number of sense amplifiers per shared I/O line along with corresponding columns may be eight (for example). The number of portions 462-1, 462-2, 455-2, 462-M of the subarray may be the same as the number of shared I/O lines 455-1, 455-2, 455-M configured to couple to the subarray. The sub-arrays may be arranged according to various DRAM architectures to couple shared I/O lines 455-1, 455-2, and 455-M between sub-arrays 425-0, 425-1, and 425-N-1.
For example, portion 462-1 of subarray 425-0 in FIG. 4A may have sense amplifier 406-0 coupled to column 422-0. As described herein, a column can include a single digit line 405-0 (sense line) for a single column of memory cells. However, alternative embodiments may include a pair of complementary digit lines referred to as digit line 0 and digit line 0. Embodiments are not so limited.
As illustrated in FIG. 1B and shown in greater detail in FIGS. 4A and 4B, in various embodiments, a sensing circuit strip (e.g., a read/latch strip) may extend from one end of a subarray to an opposite end of the subarray. For example, as shown for subarray 0(425-0), read/latch stripe 0(424-0, shown schematically above and below the DRAM columns in a folded sense line architecture) may include and extend from sense amplifier 0(406-0) in portion 462-1 and sense amplifier X-1(406-X-1) in portion 462-M of subarray 0(425-0) to sense amplifier X-1.
The configuration of the combination of sense amplifiers 406-0, 406-1, and 406-X-1 and shared I/O lines 455-1, 455-2, and 455-M illustrated in FIGS. 4A and 4B is not limited to: in the folded DRAM architecture, half of the combination of sense amplifiers of the read/latch circuit 450 are formed above the columns of memory cells and half are formed below the columns of memory cells 422-0, 422-1. For example, in various embodiments, a read/latch stripe 424 can be formed for a particular subarray 425, with any number of sense amplifiers in the read/latch stripe formed above and below the columns of memory cells. Thus, in some embodiments (as illustrated in FIG. 1B), read/latch circuits and all sense amplifiers of a corresponding read/latch amplifier strip can be formed either over or under columns of memory cells.
As described in connection with FIGS. 4A and 4B, each sub-array may have column select circuitry (not shown) and/or multiplexers (e.g., 460-1, 460-2) configured to perform data move operations on a particular column 422 of a number of sub-arrays (e.g., sub-arrays 425-0 and 425-N-1) and its complementary digital lines, involving moving stored data values accessed from sense amplifiers 406 to coupled shared I/O lines 455-1. For example,
The controller may be further configured to direct movement of data values from a selected first row (e.g., row 419-1) and a selected sense line in a first subarray (e.g., subarray 425-0) and a selected second row (e.g., row 419-2) and a selected sense line in a second subarray (e.g., subarray 425-N-1) to a data I/O pin and/or processor via a shared I/O line (e.g., shared I/O line 455-1) to perform data processing. In various embodiments, processor 172 may be coupled to (e.g., be part of or physically associated with) host 110 as a destination location. In some embodiments, all data values from a respective row (e.g., rows 419-1 and 419-2) may be moved to a processor (e.g., via data I/O pins) using a plurality of shared I/O lines 455-1.
For example, multiplexers 460-1, 460-2 may direct (e.g., via column select circuitry) to move (e.g., sequentially move) each of eight columns (e.g., numbers/numerals) in a portion (e.g., 462-1) of a subarray (e.g., 425-0) for a particular row so that sense amplifiers of a read/latch stripe (e.g., 424-0) of the portion may store (cache) all data values in a particular order (e.g., in the order in which the columns are sensed) and move to a shared I/O line. Utilizing complementary digit lines (digits/x) and complementary shared I/O lines 455, 16 data values (e.g., bits) may be sequenced from one portion of the subarray to the shared I/O lines for each of the eight columns, such that one data value (e.g., bit) is input to each of the complementary shared I/O lines from each of the sense amplifiers at a time.
As such, with 2048 sub-array portions (e.g., sub-array portions 462-1,..., 462-M) each having eight columns and each configured to be coupled to a different shared I/O line (e.g., 455-1 to 455-M), 2048 data values (e.g., bits) may be moved to multiple shared I/O lines at substantially the same point in time (e.g., in parallel). Accordingly, the present disclosure describes configuring a plurality of shared I/O lines to be at least one thousand bits wide (e.g., 2048 bits wide) to increase the speed, rate, and/or efficiency of data movement in a DRAM implementation (e.g., relative to a 64-bit wide data path).
For example, a first read/latch circuit 450 (e.g., including sense amplifier 406 and associated circuitry) may be configured to enable movement of data values accessed from a first row (e.g., 419-0) of a first subarray (e.g., 425-0), and a second read/latch circuit 450 may be configured to enable movement of data values accessed from a second row (e.g., 419-2) of a second subarray (e.g., 425-N-1) to perform a read operation on the accessed data values. In some embodiments, the read operation and/or the data move operation may enable a computational operation (e.g., a mathematical and/or brining operation) to be performed on the first data value and the second data value at the destination location (e.g., processor 172). In some embodiments, a first read/latch circuit may be configured to effect movement of data values to a first subarray and a second read/latch circuit may be configured to effect movement of data values to a second subarray to perform a write operation on the moved data values.
As illustrated in FIGS. 4A and 4B, in each sub-array (e.g., sub-array 425-0), one or more multiplexers 460-1, 460-2 may be coupled to the sense amplifiers of each portion 462-1, 462-2, e.g., 462-M of the read/latch strip 424-0 of the sub-array. The multiplexers 460-1, 460-2 may be configured to access, select, receive, coordinate, combine, and transmit data values (e.g., bits) stored (cached) by the number of selected sense amplifiers in a portion (e.g., portion 462-1) of a subarray for input to a shared I/O line (e.g., shared I/O line 455-1). As such, the shared I/O lines may be configured to couple source locations in the banks to destination locations (e.g., data I/O pins) to enable improved data movement, as described herein.
As described herein, the controller can be configured to move data from a selected row in a source location and a selected sense line to a selected destination location (e.g., a data I/O pin) via a shared I/O line (e.g., in response to a signal from the
In a number of embodiments, different sub-arrays and different rows in each of the different sub-arrays can be activated, and data values from the activated rows can be sensed and stored (e.g., accessed) by respective read/latch circuits within a first time period, which can be simultaneous (e.g., particularly synchronous) or within a 5ns time window. After the row is activated and data values are sensed and stored, the data values may be accessed from the respective read/latch circuits and moved to a data I/O pin formed as part of I/O circuit 144 within a second time period (e.g., 10 ns). In a number of embodiments, data movement can be performed via coupled shared I/O lines described herein and/or via I/O lines coupling each of the sense amplifiers in the respective read/latch strips to data I/O pins. Accordingly, the controller described herein may be configured to direct the various embodiments that couple (e.g., via signals to multiplexers and/or sense amplifiers in the respective read/latch strips) to the I/O lines for the second time period to move the stored data values.
For example, in a number of embodiments, a first sense amplifier may be configured to couple to a shared I/O line within 10ns after a second sense amplifier is coupled to the same shared I/O line to enable movement of a stored first data value and a stored second data value to a destination location (e.g., to a data I/O pin and thus to processor 172 of host 110) via the same shared I/O line. A first set of sense amplifiers (e.g., a read/latch strip 424-0 including a first sense amplifier among a plurality of sense amplifiers) may be configured to send data sensed from a row at a particular ordinal position of a first subarray in parallel with a plurality of shared I/O lines (e.g., 455-1. A second set of sense amplifiers (e.g., a read/latch stripe 424-N-1 including a second sense amplifier among the plurality of sense amplifiers) may be configured to send data sensed from rows at different ordinal positions of the second subarray in parallel with the plurality of shared I/O lines.
The data (e.g., number of bits) sent may correspond to at least one kilobit width of the plurality of shared I/O lines and a subset of the plurality of sense amplifiers that are selectably and sequentially coupled to the plurality of shared I/O lines. For example, one eighth of 16,384 sense amplifiers (which are selectably and sequentially coupled to 2048 shared I/O lines) correspond to 2048 bits sent in parallel from the read/latch stripe 424-0 and the read/latch stripe 424-N-1 via a plurality of shared I/O lines. As described herein, the destination location may be or may include a processor 172 configured to perform data processing on the first data value and the second data value.
An address signal (e.g., from host 110) may be received by
A first signal (e.g., corresponding to a particular sub-array address determined by the sub-array decoder shown at 373 and described in connection with fig. 3) may be stored by a first sub-array latch (e.g., sub-array latch circuit 375-0) coupled to first sub-array 425-0. A second signal corresponding to a different sub-array address may be stored by a second sub-array latch (e.g., sub-array latch circuit 375-N-1) coupled to second sub-array 425-N-1. The row at the particular ordinal position and the row at a different ordinal position may be activated during a first time period in response to the storing of the first signal and the second signal.
As described herein, row address signals may be used to address rows in a first subarray and rows in a second subarray with row addresses corresponding to particular ordinal positions in the first subarray and different row addresses corresponding to different ordinal positions in the second subarray. Addressing rows in the first and second sub-arrays with row address signals corresponding to different ordinal positions of the first and second sub-arrays may be performed instead of addressing rows at a particular ordinal position in the first sub-array by using address signals that simultaneously address rows at the same ordinal position in the second sub-array, as is done in other implementations, in order to increase the speed, rate and/or efficiency of sub-array addressing. For example, the deactivation of a row at a particular ordinal position in the first and second subarrays followed by activation of a row at a different ordinal position in the first and second subarrays (achieved by the second address signal) may be extended by a time period ranging from 30ns to 60ns, rather than the simultaneous activation achieved by using different row addresses for the first and second subarrays described herein (e.g., up to 5ns time period).
Row activation during the first time period may enable a reduction in latency between sensing a first data value stored in a row at a particular ordinal position in the first subarray and sensing a second data value stored in a row at a different ordinal position in the second subarray. The reduction in latency may be relative to switching from activating a row at a particular ordinal position in the first and second subarrays to activating a row at a different ordinal position in the first and second subarrays, as is done in other implementations.
Coupling the shared I/O line to the read/latch circuits of the first subarray and to the read/latch circuits of the second subarray in a second time period (e.g., within 10ns relative to the previous activation of the row in the first time period of 0ns to 5 ns) may enable an increase in throughput capability (e.g., the number of bits actually moved per second) of the shared I/O line for data values stored in a row at a particular ordinal position in the first subarray and a row at a different ordinal position in the second subarray. The increased throughput capability of the shared I/O line of the present invention may be determined relative to other implementations, including: the row at a particular ordinal position in the first and second subarrays is activated and the read/latch circuits of the first and second subarrays are coupled to a shared I/O line, followed by the activation of the rows at different ordinal positions in the first and second subarrays and the re-coupling of the read/latch circuits of the first and second subarrays to the shared I/O line.
For example, multiple rows at different ordinal positions in different subarrays may be activated simultaneously (or within a 5ns time period) based on different row addresses, and data values from two different rows may be moved (e.g., coupled to and/or sent) over a particular shared I/O line within a 10ns time period (e.g., within 4ns of each other). This may increase the throughput capability of the coupled shared I/O lines relative to other implementations in which only performing a deactivation of a row at a particular ordinal position in the first and second subarrays followed by an activation of a row at a different ordinal position in the first and second subarrays may take a time period ranging from 30ns to 60 ns. Time periods in the range from 30ns to 60ns do not even include the time it takes to sense a data value, access a data value, and/or couple to an appropriate shared I/O line.
In physical bank 121 of memory device 120, a first data value may be stored in a row at a particular ordinal position in a first subarray and a second data value may be stored in a row at a different ordinal position in a second subarray. The address signals described herein may include addressing a first subarray with a particular subarray address and addressing a second subarray with a different subarray address so as to form a virtual bank relative to other implementations including activating rows at particular ordinal positions in the first and second subarrays followed by activating rows at different ordinal positions in the first and second subarrays. For example, a first read/latch circuit may be selectably coupled to a first row indicated by a particular row address in order to access data values of the first row, and a second read/latch circuit may be selectably coupled to a second row indicated by a different row address in order to access data values of the second row, forming a virtual bank and enabling read operations to be performed on the accessed data values of the first and second rows. In some embodiments, activating different rows in different subarrays of a bank, as described herein, may enable a write operation to be performed on the memory cells of the first and second rows.
In a number of embodiments, read/latch circuitry (e.g., 450-0, 450-1, 455-1, 450-X-1 in fig. 4A and 4B) is selectably and/or individually coupled to each of a plurality of sub-arrays (e.g., 425-0, 425-1, 425-N-1) and/or to a shared I/O line (e.g., at least one of 455-1, 455-2, 455-1, 455-M). For example, one of the eight sense amplifiers in read/latch stripe 424-0 of portion 462-1 in sub-array 425-0 (e.g., 406-0, 406-1,. logarithms, 406-7) and one of the eight sense amplifiers in read/latch stripe 424-N-1 of portion 462-1 in sub-array 425-N-1 may be selectively coupled to shared I/O line 455-1. In some embodiments, the shared I/O line is selectably coupled to at least three of the read/latch circuits individually coupled to at least three of the plurality of sub-arrays. For example, at least three of the read/latch circuits may be coupled to move data values over the shared I/O lines substantially simultaneously (e.g., within a 10ns time period after the previous read/latch circuit was coupled).
The read/latch strips (e.g., sense amplifiers 406 in all of the read/latch strips 424-0, 425-N-1) in each of a plurality of sub-arrays (e.g., sub-arrays 425-0, 425-N-1) may be configured to be coupled to a plurality of shared I/O lines (e.g., 455-1, 455-M). In some embodiments, only one column of the plurality (e.g., two, four, eight, sixteen, etc., including odd numbers) of columns 422 may be coupled to one of the plurality of shared I/O lines at a time in a first sub-array using a first read/latch stripe (e.g., read/latch stripe 424-0), and only one column of the plurality (e.g., two, four, eight, sixteen, etc., including odd numbers) of columns 422 may be coupled to one of the plurality of shared I/O lines at a time in a second sub-array using a second read/latch stripe (e.g., read/latch stripe 424-N-1).
In various embodiments, the
The shared I/O lines may be used (e.g., in a DRAM implementation) as data paths to move data from various locations (e.g., sub-arrays) in an array of memory cells. The shared I/O line may be shared between all read/latch stripes. In various embodiments, the sense amplifiers of one read/latch strip, two read/latch strips, or more than two read/latch strips may be coupled to a shared I/O line at any given time. A row coupled to a first read/latch stripe can be opened and the data values of the memory cells in the row can be sensed. After sensing, a first read/latch stripe (e.g., its sense amplifiers) may be opened to the shared I/O line along with a second read/latch stripe (e.g., its sense amplifiers) to the same shared I/O line.
For example, a first read/latch stripe 424-0 may include a number of sense amplifiers 406 configured to store a first data value sensed in a first row 419-1 of a first subarray 425-0 and to move the first data value via a coupled shared I/O line 455-1, and a second read/latch stripe 424-N-1 may include a number of sense amplifiers configured to store a second data value sensed in a second row 419-2 of a second subarray 425-N-1 and to move the second data value via a coupled shared I/O line 455-1. The number of sense amplifiers in a first read/latch stripe may be configured to be coupled to a shared I/O line within 10ns after the number of sense amplifiers in a second read/latch stripe are coupled to the shared I/O line to enable moving a first data value and a second data value to a destination location.
Alternatively or additionally, a first buffer (e.g., as shown at 461-1 and 461-2 in subarray portion 462-1 of subarray 425-0) may be coupled to a first sense amplifier (e.g., coupled to at least one of sense amplifiers 406-0,.., 406-7 in subarray portion 462-1 of subarray 425-0 via multiplexers 460-1, 460-2). The first buffers 461-1, 461-2 may further be coupled to a shared I/O line (e.g., shared I/O line 455-1). The first buffers 461-1, 461-2 may be configured to store first data values accessed from the first sense amplifiers for movement over the shared I/O line 455-1. A second buffer (e.g., as shown at 461-1 and 461-2 in subarray portion 462-1 of subarray 425-N-1) may be coupled to a second sense amplifier (e.g., coupled to at least one of sense amplifiers 406-0,.., 406-7 in subarray portion 462-1 of subarray 425-N-1 via multiplexers 460-1, 460-2) and may further be coupled to the same shared I/O line (e.g., shared I/O line 455-1). The second buffers 461-1, 461-2 may be configured to store second data values accessed from the second sense amplifiers for movement over the shared I/O line 455-1. The first data value stored by the first buffer may enable continuous coupling of the first buffer to the shared I/O line and the second data value stored by the second buffer may also enable continuous coupling of the second buffer to the shared I/O line.
For example, the first and second data values may be stored continuously (e.g., through multiple cycles of multiplexers 460-1, 460-2 coupled to respective sense amplifiers), and the first and second buffers may also be coupled to the shared I/O line to enable the data values to be selectably moved via the shared I/O line at appropriate times (e.g., as determined by the
Fig. 5 is a flow chart of an embodiment of a
At
At
As shown at
As used herein, ordinal positioning is used to distinguish between the relative positions of elements within a respective group of elements. For example, the plurality of subarrays may each include a series of 1024 rows (e.g., row 0 through row 1023). In this example, row 0 from a particular subarray (e.g., the first row of a particular subarray) has a different ordinal position than any of
In the above detailed description of the invention, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how one or more embodiments of the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and structural changes may be made without departing from the scope of the present disclosure.
As used herein, designators such as "X," "Y," "N," "M," etc. (particularly with respect to reference numbers in the figures) indicate a number of particular features that can include such indicia. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" include singular and plural referents unless the context clearly dictates otherwise, as well as the plural references, "a plurality", "at least one" and "one or more" (e.g., a plurality of memory arrays may refer to one or more memory arrays), and "plurality" is intended to refer to more than one of such things. Moreover, throughout this application, the words "can" and "may" are used in a permissive sense (i.e., having the potential to, being able to …) and not in a mandatory sense (i.e., must). The term "include" and its derivatives mean "including, but not limited to". The terms "coupled" and "coupling" mean physically connected, directly or indirectly, for accessing and/or moving (transmitting) instructions (e.g., control signals, address signals, etc.) and data, as the context dictates. The terms "data" and "data value" are used interchangeably herein and may have the same meaning depending on the context (e.g., one or more data units or "bits").
As described herein, an "I/O line" can be a line (e.g., a bus) that is selectably shared (e.g., coupled to) multiple sub-arrays, rows, and/or particular columns of memory cells, for example, via a set of sense amplifiers coupled to read/latch circuitry (e.g., in a read/latch stripe) of each of the sub-arrays. For example, the sense amplifiers of each of a selectable subset of the number of columns (e.g., eight column subsets of the total number of columns) may be selectably coupled to each of a plurality of I/O lines (e.g., shared I/O lines, as described herein) to move the data values stored (e.g., cached) in the sense amplifiers of the read/latch stripe to each of the plurality of I/O lines. Since the singular forms "a" and "an" and "the" may include both the singular and plural referents herein, the term "shared I/O line," for example, may be used to refer to "shared I/O lines. Further, "shared I/O line" is an abbreviation for "multiple shared I/O lines".
While example embodiments including various combinations and configurations of read/latch circuits, sense amplifiers, read/latch stripes, I/O lines, shared I/O lines, subarray decoders, row decoders and/or multiplexers, and other circuitry shown and described herein for subarray addressing have been illustrated and described herein, embodiments of the invention are not limited to those combinations explicitly stated herein. Other combinations and configurations of read/latch circuits, sense amplifiers, read/latch stripes, I/O lines, shared I/O lines, subarray decoders, row decoders and/or multiplexers, and other circuits disclosed herein for subarray addressing are expressly included within the scope of this disclosure.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that an arrangement calculated to achieve the same results may be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art upon reviewing the above description. The scope of one or more embodiments of the present disclosure includes other applications in which the above structures and processes are used. The scope of one or more embodiments of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
In the foregoing embodiments, some features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure have to use more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.
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