阅读说明：本技术 数字控制信号生成电路及电子设备 (Digital control signal generating circuit and electronic device ) 是由 赖哲人 戴兴科 于 2021-08-19 设计创作，主要内容包括：一种数字控制信号生成电路及电子设备,属于电子技术领域,通过通用输出电路将第一数字信号转换为第二数字信号以驱动上下拉电路；上下拉电路根据第二数字信号将上下拉电路的输出端进行上拉或者下拉以改变上下拉电路的输出端的电平状态,或者将上下拉电路的输出端既不上拉也不下拉,使上下拉输出处于高阻态；由于可以改变上下拉电路的输出端的电平状态,对有不同复位电平或上电启动逻辑电平需求的微处理器,仅需开发一个数字控制信号生成电路(一个芯片),即可以达到同时支持不同类型的上述微处理器芯片的目的,降低了开发成本,同时便于生产和和库存管理。(A digital control signal generating circuit and electronic equipment belong to the technical field of electronics, and a first digital signal is converted into a second digital signal through a universal output circuit to drive a pull-up and pull-down circuit; the pull-up and pull-down circuit pulls up or pulls down the output end of the pull-up and pull-down circuit according to the second digital signal to change the level state of the output end of the pull-up and pull-down circuit, or the output end of the pull-up and pull-down circuit is neither pulled up nor pulled down, so that the pull-up and pull-down output is in a high resistance state; the level state of the output end of the pull-up and pull-down circuit can be changed, and for microprocessors with different reset levels or power-on starting logic level requirements, only one digital control signal generating circuit (one chip) needs to be developed, so that the purpose of simultaneously supporting different types of microprocessor chips can be achieved, the development cost is reduced, and meanwhile, the production and inventory management are facilitated.)

1. A digital control signal generating circuit, comprising:

a general purpose output circuit configured to convert the first digital signal into a second digital signal to drive the pull-up and pull-down circuit;

the pull-up and pull-down circuit is connected with the general output circuit and configured to pull up or pull down the output end of the pull-up and pull-down circuit according to the second digital signal to change the level state of the output end of the pull-up and pull-down circuit, or pull up or pull down neither the output end of the pull-up and pull-down circuit according to the second digital signal to enable the output end of the pull-up and pull-down circuit to be in a high-resistance state.

2. The digital control signal generating circuit of claim 1, further comprising a resistive component;

the first end of the resistor assembly is connected with the output end of the pull-up and pull-down circuit, and the second end of the resistor assembly is pulled up to a first voltage or pulled down to a power ground;

when the output end of the pull-up and pull-down circuit is in a high-resistance state, the output level of the pull-up and pull-down circuit is determined by the voltage connected with the second end of the resistor component.

3. The digital control signal generating circuit of claim 2, wherein the digital control signal generating circuit further comprises:

a first communication circuit connected to the general output circuit and configured to receive a single-wire communication signal and decode the single-wire communication signal to output the first digital signal;

the general purpose output circuit is specifically configured to latch the first digital signal to output the second digital signal.

4. The digital control signal generating circuit according to claim 3, wherein the first communication circuit, the general purpose output circuit, and the pull-down circuit are integrated in one chip, and the resistive component is provided outside the chip.

5. The digital control signal generating circuit of claim 3, further comprising:

a control circuit configured to output a control signal;

and the second communication circuit is connected with the control circuit and the first communication circuit and is configured to transmit the single-wire communication signal from a line according to the control signal.

6. The digital control signal generating circuit according to any of claims 1 to 5, wherein the general purpose output circuit comprises a first D flip-flop and a second D flip-flop;

the data input end of the first D trigger and the data input end D of the second D trigger are connected to a first digital signal input end of the general output circuit, the clock end of the first D trigger and the clock end of the second D trigger are connected to the clock end of the general output circuit, and the inverted data latch output end of the first D trigger and the data latch output end of the second D trigger are connected to a second digital signal output end of the general output circuit.

7. The digital control signal generating circuit of claim 2, wherein the pull-up and pull-down circuit comprises a first field effect transistor and a second field effect transistor; the first field effect transistor is PMOS, and the second field effect transistor is NMOS; the source electrode of the first field effect tube is connected with a first power supply, the grid electrode of the first field effect tube and the grid electrode of the second field effect tube are connected to the second digital signal input end of the pull-up and pull-down circuit together, the drain electrode of the first field effect tube and the drain electrode of the second field effect tube are connected to the output end of the pull-up and pull-down circuit together, and the source electrode of the second field effect tube is connected with the power supply ground.

8. The digital control signal generating circuit according to claim 7, wherein when the first fet and the second fet are both in the off state, if the resistive component pulls up to the first voltage, the output terminal of the pull-up and pull-down circuit is pulled up to the first voltage by the resistive component, so that the pull-up and pull-down circuit outputs a high level digital control signal; if the resistance component is pulled down to the power ground, the output end of the pull-up and pull-down circuit is pulled down to the power ground by the resistance component, so that the pull-up and pull-down circuit outputs a low-level digital control signal.

9. The digital control signal generating circuit according to claim 8, wherein the first fet and the second fet are both in an off state when the second digital signal is in the first state or when the second digital signal input is stopped.

10. The digital control signal generating circuit as claimed in claim 7, wherein the second digital signal is in a second state, and when the resistor element is pulled up to the first voltage, the first fet is turned off according to the second digital signal in the second state, the second fet is turned on according to the second digital signal in the second state to a power ground, and the output terminal of the pull-up and pull-down circuit is pulled down to the power ground to enable the pull-up and pull-down circuit to output the low-level digital control signal.

11. The digital control signal generating circuit as claimed in claim 7, wherein when the second digital signal is in a third state and the resistor element is pulled down to ground, the second fet is turned off according to the second digital signal in the third state, the first fet is turned on according to the second digital signal in the third state to the first voltage, and the output terminal of the pull-up/down circuit is pulled up to the first voltage, so that the pull-up/down circuit outputs a high-level digital control signal.

12. An electronic device, characterized in that the electronic device comprises a digital control signal generating circuit according to any one of claims 1 to 11.

Technical Field

The application belongs to the technical field of electronics, and particularly relates to a digital control signal generation circuit and electronic equipment.

Background

Microprocessor chips from different companies will be reset or powered on with different digital control signals. Some chips require that the power-on starting signal and the reset signal are at low level at ordinary times, and are at high level when reset or power-on starting is needed; some chips are on the contrary and require that the power-on enable signal and the reset signal be high at ordinary times and low at times when a reset or power-on enable is desired. In order to match the two different chips, the power-on start signal generation circuit or the reset signal generation circuit in the existing scheme needs to be configured with two different chips, which has the disadvantages of increasing development cost and tape-out cost and bringing troubles to production and inventory management.

It is desirable to provide a digital control signal generating circuit to support the output of the two different digital signal levels.

Disclosure of Invention

The present application provides a digital control signal generating circuit and an electronic device, so as to output two different digital signal levels, i.e., a high level and a low level, in a compatible manner.

The embodiment of the application provides a digital control signal generating circuit, which comprises a slave machine, wherein the slave machine comprises:

a general purpose output circuit configured to convert the first digital signal into a second digital signal to drive the pull-up and pull-down circuit;

the pull-up and pull-down circuit is connected with the general output circuit and is configured to pull up or pull down the output end of the pull-up and pull-down circuit according to the second digital signal so as to change the level state of the output end of the pull-up and pull-down circuit.

In one embodiment, the digital control signal generating circuit further comprises a resistive component;

the first end of the resistor assembly is connected with the output end of the pull-up and pull-down circuit, and the second end of the resistor assembly is pulled up to a first voltage or pulled down to a power ground;

when the output end of the pull-up and pull-down circuit is in a high-resistance state, the output level of the pull-up and pull-down circuit is determined by the voltage connected with the second end of the resistor component.

In one embodiment, the digital control signal generating circuit further comprises:

a first communication circuit connected to the general output circuit and configured to receive a single-wire communication signal and decode the single-wire communication signal to output the first digital signal;

the general purpose output circuit is specifically configured to latch the first digital signal to output the second digital signal.

In one embodiment, the first communication circuit, the universal output circuit, and the pull-down circuit are integrated in a chip, and the resistive component is disposed off the chip.

In one embodiment, the digital control signal generating circuit further comprises:

a control circuit connected to the second communication circuit and configured to output a control signal;

and the second communication circuit is connected with the control circuit and the first communication circuit and is configured to transmit the single-wire communication signal from a line according to the control signal.

In one embodiment, the general purpose output circuit comprises a first D flip-flop and a second D flip-flop;

the data input end of the first D trigger and the data input end D of the second D trigger are connected to a first digital signal input end of the general output circuit, the clock end of the first D trigger and the clock end of the second D trigger are connected to the clock end of the general output circuit, and the inverted data latch output end of the first D trigger and the data latch output end of the second D trigger are connected to a second digital signal output end of the general output circuit.

In one embodiment, the pull-down and pull-up circuit comprises a first field effect transistor and a second field effect transistor; the first field effect transistor is PMOS, and the second field effect transistor is NMOS;

the source electrode of the first field effect tube is connected with a first power supply, the grid electrode of the first field effect tube and the grid electrode of the second field effect tube are connected to the second digital signal input end of the pull-up and pull-down circuit together, the drain electrode of the first field effect tube and the drain electrode of the second field effect tube are connected to the output end of the pull-up and pull-down circuit together, and the source electrode of the second field effect tube is connected with the power supply ground.

In one embodiment, when the first field effect transistor and the second field effect transistor are both in the off state, if the resistor component is pulled up to the first voltage, the output end of the pull-up and pull-down circuit is pulled up to the first voltage by the resistor component, so that the pull-up and pull-down circuit outputs a high-level digital control signal; if the resistance component is pulled down to the power ground, the output end of the pull-up and pull-down circuit is pulled down to the power ground by the resistance component, so that the pull-up and pull-down circuit outputs a low-level digital control signal.

In one embodiment, when the second digital signal is in the first state or the input of the second digital signal is stopped, the first field effect transistor and the second field effect transistor are both in the off state.

In one embodiment, when the second digital signal is in a second state and the resistance component is pulled up to the first voltage, the first fet is turned off according to the second digital signal in the second state, the second fet is turned on according to the second digital signal in the second state to a power ground, and the output terminal of the pull-up and pull-down circuit is pulled down to the power ground so that the pull-up and pull-down circuit outputs a low-level digital control signal.

In one embodiment, when the second digital signal is in a third state and the resistor element is pulled down to a power ground, the second fet is turned off according to the second digital signal in the third state, the first fet is turned on to the first voltage according to the second digital signal in the third state, and the output terminal of the pull-up and pull-down circuit is pulled up to the first voltage, so that the pull-up and pull-down circuit outputs the digital control signal at a high level.

The embodiment of the application also provides electronic equipment, and the electronic equipment comprises the digital control signal generating circuit.

Compared with the prior art, the embodiment of the invention has the following beneficial effects: the level state of the output end of the pull-up and pull-down circuit can be changed, and for microprocessors with different reset levels or power-on starting logic level requirements, only one digital control signal generating circuit (one chip) needs to be developed, so that the purpose of simultaneously supporting different types of microprocessor chips can be achieved, the development cost is reduced, and meanwhile, the production and inventory management are facilitated.

Drawings

In order to more clearly illustrate the technical invention in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts.

Fig. 1 is a schematic structural diagram of a digital control signal generating circuit according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a digital control signal generating circuit according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a digital control signal generating circuit according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a digital control signal generating circuit according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a digital control signal generating circuit according to an embodiment of the present disclosure;

FIG. 6 is an exemplary circuit schematic of a digital control signal generating circuit provided by an embodiment of the present application;

fig. 7 is a schematic diagram of another exemplary circuit of a digital control signal generating circuit according to an embodiment of the present application.

Detailed Description

In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.

It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, refer to an orientation or positional relationship illustrated in the drawings for convenience in describing the present application and to simplify description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

Related art TWS bluetooth headset systems typically include a charging bay and two bluetooth headsets.

The charging chamber contains a first battery, a discharge circuit, a microprocessor, and other circuitry (e.g., a first charging circuit). The Bluetooth headset comprises a second battery, a second charging circuit, a Bluetooth chip and other elements. When the earphone enters or leaves the charging chamber, the internal circuit of the Bluetooth earphone needs to generate a reset signal or a power-on starting signal. When the bluetooth headset enters the charging cabin, a reset signal with a preset level is often needed to reset the bluetooth chip, so that the program of the bluetooth chip is ensured to be in a normal working state. When the Bluetooth headset is in the charging cabin, the Bluetooth headset is in a power-off state to save power. When the bluetooth headset is taken out of the charging cabin, the bluetooth headset needs to be started up, so that the bluetooth headset can be automatically connected with the bluetooth of a mobile phone, the bluetooth headset usually comprises a circuit, and when the bluetooth headset goes out of the cabin, a power-on starting signal with a preset level is sent to achieve the purpose of starting a bluetooth chip.

However, this technique has the following disadvantages: bluetooth chips or microprocessor chips produced by different companies can be reset or started up by adopting different levels, so that the preset level can be a high level or a low level, two different chips are required to be configured, development cost and production cost are increased, and inconvenience is brought to production and inventory management.

Fig. 1 shows a schematic structural diagram of a digital control signal generating circuit according to a preferred embodiment of the present application, and for convenience of description, only the parts related to the present embodiment are shown, and detailed descriptions are as follows:

the above-described digital control signal generating circuit includes a general-purpose output circuit 12 and a pull-up and pull-down circuit 13.

A general purpose output circuit 12 configured to convert the first digital signal into a second digital signal to drive the pull-up and pull-down circuit 13.

And the pull-up and pull-down circuit 13 is connected with the general output circuit 12 and configured to pull up or pull down the output end of the pull-up and pull-down circuit 13 according to the second digital signal so as to change the level state of the output end of the pull-up and pull-down circuit 13, or pull up or pull down the output end of the pull-up and pull-down circuit according to the second digital signal so as to enable the output end of the pull-up and pull-down circuit to be in a high-resistance state.

As shown in fig. 2, the digital control signal generating circuit further includes a resistive component 14.

A first terminal of the resistor component 14 is connected to an output terminal of the pull-down and pull-up circuit 13, and a second terminal of the resistor component 14 is pulled up to a first voltage or pulled down to a power ground. When the output end of the pull-up and pull-down circuit is in a high resistance state, the output level of the pull-up and pull-down circuit is determined by the voltage connected with the second end of the resistor component.

In the related technical scheme, a control signal is sent to a logic chip through a control circuit so that the logic chip generates a digital control signal with a level matched with that of a Bluetooth chip or a microprocessor chip, however, in the initial stage after the logic chip is powered on, because the logic chip has no control signal input, the output end is in a high-impedance state, and a power-on starting signal port or a reset signal port of the Bluetooth chip or the microprocessor chip is in an unstable state, so that equipment configured with the digital control signal generating circuit is powered on or reset mistakenly, and the system stability is poor.

When no second digital signal is input, the output end of the pull-up and pull-down circuit 13 is at a steady level because the resistor component 14 is pulled down to the power ground or pulled up to the first voltage, and the stability of the system is improved. And the same chip internal circuit can simultaneously support the requirements of different microprocessors in the background technology on different reset or power-on starting digital signals by matching with a resistor component outside the chip, so that the purpose of simultaneously supporting different types of microprocessors can be achieved by only developing one digital control signal generating chip, the development cost is reduced, and meanwhile, the production and inventory management are facilitated.

As shown in fig. 3, the digital control signal generating circuit further includes a first communication circuit 11.

A first communication circuit 11 connected to the general-purpose output circuit 12, configured to receive the single-wire communication signal and decode the single-wire communication signal to output a first digital signal;

the general purpose output circuit 12 is specifically configured to latch the first digital signal to output a second digital signal.

It is noted that the first communication circuit 11, the general output circuit 12 and the pull-up and pull-down circuit 13 may be integrated in one chip, and the resistance component 14 is disposed outside the chip.

As shown in fig. 4, the digital control signal generating circuit further includes a second communication circuit 15 and a control circuit 16.

A control circuit 16 configured to output a control signal;

and a second communication circuit 15 connected to the control circuit 16 and the first communication circuit 11 and configured to transmit a single-wire communication signal from a line according to a control signal.

It is understood that when the digital control signal generating circuit is applied to an earphone system or an atomization device, the earphone system includes a host (charging box) and a slave (earphone), and the atomization device also includes the host (charging box) and the slave (e.g., a cigarette rod of an electronic cigarette). The second communication circuit 15 and the control circuit 16 may be provided in a master, and the resistance component 14, the first communication circuit 11, the general-purpose output circuit 12, and the pull-up and pull-down circuit 13 may be provided in a slave.

By providing the second communication circuit 15 and the first communication circuit 11, communication between the master and the slave is realized, and output of the digital control signal is controlled by the control circuit 16 on the master side.

The single-wire communication means that half-duplex communication is realized by one signal wire (single-wire bus) other than the ground wire. As shown in fig. 5, single-wire communication involves a master (e.g., a charging box) and a slave (e.g., an earphone or a cigarette rod). When information needs to be transmitted, whether the master or the slave, the field effect transistor connected to the single-wire bus, which is an open source, is driven by a digital transmission signal. Taking the host side transmission signal as an example, the single-wire communication signal (digital transmission signal) of the host side drives the third fet M3, and when the third fet M3 is turned on, the signal on the single-wire bus is low; when the third FET is turned off, the signal on the single wire bus is pulled to a high level VDD by a pull-up resistor Rx. The signal of the single-wire bus is received by a first NOT gate NOT1 connected to the bus from the slave, the output terminal of the first NOT gate NOT1 is connected to the first receiving circuit 151, and the first receiving circuit 151 decodes the received digital signal and outputs the first digital signal. When the slave needs to send a signal, the signal is also sent through the fourth fet M4 connected to the single-wire bus, and the signal is received by the second NOT gate NOT2 in the master and sent to the second receiving circuit 111 of the master.

Fig. 6 shows an exemplary circuit structure of a digital control signal generating circuit according to an embodiment of the present invention, fig. 7 shows another exemplary circuit structure of a digital control signal generating circuit according to an embodiment of the present invention, and for convenience of description, only the parts related to the embodiment of the present invention are shown, and the following details are described below:

the universal output circuit 12 includes a first D flip-flop U1 and a second D flip-flop U2.

The data input terminal D of the first D flip-flop U1 and the data input terminal D of the second D flip-flop U2 are commonly connected to a first digital signal input terminal of the general output circuit 12, the clock terminal of the first D flip-flop U1 and the clock terminal of the second D flip-flop U2 are commonly connected to a clock terminal of the general output circuit 12, and the inverted data latch output terminal/Q of the first D flip-flop U1 and the data latch output terminal Q of the second D flip-flop U2 are commonly connected to a second digital signal output terminal of the general output circuit 12.

Since the signal generated by decoding the single-wire communication signal needs to be stored before outputting a stable digital signal, the first D flip-flop U1 and the second D flip-flop U2 are provided to latch the first digital signal.

The pull-down circuit 13 includes a first fet M1 and a second fet M2. The first field effect transistor is a P-type Metal-Oxide Semiconductor field effect transistor (PMOS), and the second field effect transistor is an N-type Metal-Oxide Semiconductor field effect transistor (NMOS).

The source of the first fet M1 is connected to the first power source VBB, the gate of the first fet M1 and the gate of the second fet M2 are commonly connected to the second digital signal input terminal of the pull-down circuit 13, the drain of the first fet M1 and the drain of the second fet M2 are commonly connected to the output terminal of the pull-down circuit 13, and the source of the second fet M2 is connected to the power ground.

The resistor assembly 14 includes a first resistor R1.

It will be appreciated that the first fet and the second fet share three states.

The first state is described as follows: when the first field effect transistor and the second field effect transistor are both in a cut-off state, if the resistance component is pulled up to a first voltage, the output end of the pull-up and pull-down circuit is pulled up to the first voltage by the resistance component, so that the pull-up and pull-down circuit outputs a high-level digital control signal; if the resistance component is pulled down to the power ground, the output end of the pull-up and pull-down circuit is pulled down to the power ground by the resistance component, so that the pull-up and pull-down circuit outputs a low-level digital control signal.

In a specific implementation, when the second digital signal is in the first state or the input of the second digital signal is stopped, both the first field effect transistor and the second field effect transistor are in the cut-off state.

When no second digital signal is input at ordinary times, the first field effect transistor and the second field effect transistor are both in a cut-off state. If the reset port or the power-on starting port of the microprocessor chip connected with the digital control signal generating circuit is at a low level at ordinary times, the resistor assembly is pulled down to the power ground, and the output end of the pull-up and pull-down circuit is pulled down to the power ground by the resistor assembly, so that the pull-up and pull-down circuit outputs a low-level digital control signal. If the reset port or the power-on starting port of the microprocessor chip connected with the digital control signal generating circuit is at a high level at ordinary times, the resistor assembly is pulled up to a first voltage, and the output end of the pull-up and pull-down circuit is pulled up to the first voltage by the resistor assembly, so that the pull-up and pull-down circuit outputs a high-level digital control signal.

The second state is described as follows: when the second digital signal is in the second state and the resistor element is pulled up to the first voltage, as shown in fig. 6, the first fet is turned off according to the second digital signal in the second state, the second fet is turned on to the power ground according to the second digital signal in the second state, and the output terminal of the pull-up/down circuit is pulled down to the power ground so that the pull-up/down circuit outputs the low-level digital control signal.

When a reset port or a power-on starting port of a microprocessor chip connected with the digital control signal generating circuit is at a high level at ordinary times, and when the reset port or the power-on starting port needs to be reset or is input at a low level at power-on starting, the control circuit sends a single-wire communication signal to the first communication circuit through the second communication circuit so that the first communication circuit outputs a first digital signal, the general output circuit converts the first digital signal into a second digital signal at a third state, at the moment, when the resistance component is pulled up to a first voltage, the first field effect transistor is cut off according to the second digital signal at the second state, the second field effect transistor is conducted to a power ground according to the second digital signal at the second state, and the output end of the pull-up and pull-down circuit is pulled down to the power ground so that the pull-up and pull-down circuit outputs the digital control signal at the low level. After the microprocessor chip is reset or powered on and started, the control circuit sends a single-wire communication signal to the first communication circuit through the second communication circuit so that the first communication circuit outputs a first digital signal, the general output circuit converts the first digital signal into a second digital signal in a first state, the first field effect transistor and the second field effect transistor are both in a cut-off state, and the ordinary state is recovered.

The third state is described as follows: when the second digital signal is in the third state and the resistor element is pulled down to the power ground, as shown in fig. 7, the second fet is turned off according to the second digital signal in the third state, the first fet is turned on to the first voltage according to the second digital signal in the third state, and the output terminal of the pull-up/down circuit is pulled up to the first voltage so that the pull-up/down circuit outputs the high-level digital control signal.

When a reset port or a power-on starting port of a microprocessor chip connected with the digital control signal generating circuit is in a low level at ordinary times, when the reset port or the power-on starting port needs to be input in a high level at the time of resetting or power-on starting, the control circuit sends a single-wire communication signal to the first communication circuit through the second communication circuit so that the first communication circuit outputs a first digital signal, the general output circuit converts the first digital signal into a second digital signal in a third state, at the moment, when the resistance component is pulled down to a power ground, the second field effect tube is cut off according to the second digital signal in the third state, the first field effect tube is conducted to a first voltage according to the second digital signal in the third state, and the output end of the pull-up and pull-down circuit is pulled up to the first voltage so that the pull-up and pull-down circuit outputs the digital control signal in the high level. After the microprocessor chip is reset or powered on and started, the control circuit sends a single-wire communication signal to the first communication circuit through the second communication circuit so that the first communication circuit outputs a first digital signal, the general output circuit converts the first digital signal into a second digital signal in a first state, the first field effect transistor and the second field effect transistor are both in a cut-off state, and the ordinary state is recovered.

The following further description of fig. 6 and 7 is made in conjunction with the working principle:

in fig. 6, when no second digital signal is input at ordinary times, the first fet M1 and the second fet M2 are both in the off state, and since the first resistor R1 is pulled down to the power ground, the output terminal of the pull-up and pull-down circuit is pulled up to the first voltage by the first resistor R1, so that the pull-up and pull-down circuit outputs a high-level digital control signal. The reset port or the power-on start port of the microprocessor chip connected to the digital control signal generation circuit is at a high level at ordinary times, and when a low level needs to be input when the reset or power-on start is needed, the first communication circuit 11 receives the single-wire communication signal and decodes the single-wire communication signal to output a first digital signal in a second state (the first digital signal in the second state includes a third sub-digital signal at the low level and a fourth sub-digital signal at the high level); the data input terminal D of the first D flip-flop U1 receives the third sub-digital signal of low level, and the first D flip-flop U1 outputs the first sub-digital signal of high level from the inverted data latch output terminal/Q of the first D flip-flop U1 according to the third sub-digital signal of low level; the data input terminal D of the second D flip-flop U2 receives the fourth sub-digital signal of high level, and the second D flip-flop U2 outputs the second sub-digital signal of high level from the data latch output terminal Q of the second D flip-flop U2 according to the fourth sub-digital signal of high level; wherein the first sub-digital signal and the second sub-digital signal together constitute a second digital signal. The second fet M2 is turned on according to the second sub-digital signal with high level to the power ground, the first fet M1 is turned off according to the first sub-digital signal with high level, so that the output terminal of the pull-up and pull-down circuit 13 is pulled down to the power ground, and the output terminal of the pull-up and pull-down circuit 13 outputs a digital control signal with low level. It can be understood that after the reset or power-on start of the microprocessor chip is completed, the control circuit sends a single-wire communication signal to the first communication circuit through the second communication circuit, so that the first communication circuit outputs a first digital signal, the general-purpose output circuit converts the first digital signal into a second digital signal in a first state (the first digital signal in the first state includes a third sub-digital signal at a low level and a fourth sub-digital signal at a low level), and the first D flip-flop U1 outputs the first sub-digital signal at a high level from the inverted data latch output/Q of the first D flip-flop U1 according to the third sub-digital signal at the low level; the second D flip-flop U2 outputs a low-level second sub-digital signal from the data latch output terminal Q of the second D flip-flop U2 according to the low-level fourth sub-digital signal; the second fet M2 is turned off according to the low-level second sub-digital signal, and the first fet M1 is turned off according to the high-level first sub-digital signal, so that both the first fet and the second fet are turned off and return to the normal state. Therefore, when the single-bus communication signal is input, the output of the digital control signal of the low-level pulse is realized.

In fig. 7, when no second digital signal is input at ordinary times, the first fet M1 and the second fet M2 are both in an off state, and since the first resistor R1 is pulled down to the power ground, the output terminal of the pull-up and pull-down circuit is pulled down to the power ground by the first resistor R1, so that the pull-up and pull-down circuit outputs a low-level digital control signal. The microprocessor chip connected to the digital control signal generation circuit is normally at a low level, and when a high level needs to be input when reset or power-on start is required, the first communication circuit 11 receives the single-wire communication signal and decodes the single-wire communication signal to output a first digital signal in a third state (the first digital signal in the third state includes a third sub-digital signal at a high level and a fourth sub-digital signal at a low level); the data input terminal D of the first D flip-flop U1 receives the third sub-digital signal of high level, and the first D flip-flop U1 outputs the first sub-digital signal of low level from the inverted data latch output terminal/Q of the first D flip-flop U1 according to the third sub-digital signal of high level; the data input terminal D of the second D flip-flop U2 receives the fourth sub-digital signal of low level, and the second D flip-flop U2 outputs the second sub-digital signal of low level from the data latch output terminal Q of the second D flip-flop U2 according to the fourth sub-digital signal of low level; wherein the first sub-digital signal and the second sub-digital signal together constitute a second digital signal. The second fet M2 is turned off according to the low-level second sub-digital signal, and the first fet M1 is turned on to the first voltage according to the low-level first sub-digital signal, so that the output terminal of the pull-up/down circuit 13 is pulled up to the first voltage, and the output terminal of the pull-up/down circuit 13 outputs the high-level digital control signal. It can be understood that after the reset or power-on start of the microprocessor chip is completed, the control circuit sends a single-wire communication signal to the first communication circuit through the second communication circuit, so that the first communication circuit outputs a first digital signal, the general-purpose output circuit converts the first digital signal into a second digital signal in a first state (the first digital signal in the first state includes a third sub-digital signal at a low level and a fourth sub-digital signal at a low level), and the first D flip-flop U1 outputs the first sub-digital signal at a high level from the inverted data latch output/Q of the first D flip-flop U1 according to the third sub-digital signal at the low level; the second D flip-flop U2 outputs a low-level second sub-digital signal from the data latch output terminal Q of the second D flip-flop U2 according to the low-level fourth sub-digital signal; the second fet M2 is turned off according to the low-level second sub-digital signal, and the first fet M1 is turned off according to the high-level first sub-digital signal, so that both the first fet and the second fet are turned off and return to the normal state. Therefore, when the single-bus communication signal is input, the output of the digital control signal of the high-level pulse is realized.

The embodiment of the application also provides an electronic device, which comprises the digital control signal generating circuit. The electronic device may be an earphone system or a nebulizer or other electronic devices equipped with a digital control signal generating circuit, and is not limited herein. The atomization device comprises an electronic cigarette.

According to the embodiment of the invention, the first digital signal is converted into the second digital signal through the universal output circuit so as to drive the pull-up and pull-down circuit; the pull-up and pull-down circuit pulls up or pulls down the output end of the pull-up and pull-down circuit according to the second digital signal to change the level state of the output end of the pull-up and pull-down circuit, or neither pulls up nor pulls down the output end of the pull-up and pull-down circuit according to the second digital signal to enable the output end of the pull-up and pull-down circuit to be in a high-resistance state; the level state of the output end of the pull-up and pull-down circuit can be changed, and for microprocessors with different reset levels or power-on starting logic level requirements, only one digital control signal generating circuit (one chip) needs to be developed, so that the purpose of simultaneously supporting different types of microprocessor chips can be achieved, the development cost is reduced, and meanwhile, the production and inventory management are facilitated.

It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.