阅读说明：本技术 一种功率器件的过温检测电路 (Over-temperature detection circuit of power device ) 是由 王飞 王云 郑鲲鲲 郝炳贤 任广辉 薛静 王桂磊 亨利·阿达姆松 于 2020-05-21 设计创作，主要内容包括：本发明公开了一种功率器件的过温检测电路,属于过温检测电路技术领域,三极管的PN结发射极与场效应管共享一个PGND,相对应的比较电平也对应到同一个电位,场效应管的热能可以通过PGND的金属连线绕过DTI传到三极管的发射极,其次PGND与三极管的B,C端节点在NPN的版图上形成类似于插指电容结构,用于加热NPN的B,C端金属连线,从而加热NPN管,所有以上金属层的面积需要完全覆盖NPN管以实现最佳的热传导。(The invention discloses an over-temperature detection circuit of a power device, which belongs to the technical field of over-temperature detection circuits, wherein a PN junction emitter of a triode and a field effect transistor share one PGND, corresponding comparison levels also correspond to the same electric potential, the heat energy of the field effect transistor can be transmitted to the emitter of the triode by bypassing a DTI through a metal connecting wire of the PGND, then the PGND and a B end and a C end node of the triode form a finger-inserting capacitor structure on an NPN layout, the finger-inserting capacitor structure is used for heating the metal connecting wires at the B end and the C end of the NPN, so that the NPN is heated, and the area of all the metal layers needs to completely cover the NPN to realize the optimal heat conduction.)

1. An over-temperature detection circuit of a power device, characterized in that: including field effect transistor, triode, resistance R0 and signal amplifier, the external load of drain electrode of field effect transistor, field effect transistor's source ground, field effect transistor's grid connects drive circuit, field effect transistor's source electric connection the projecting pole of triode, the external bias current of collecting electrode of triode, the positive pole of projecting pole and comparator is connected to the base of triode, the one end of resistance R0 is connected to the negative pole of comparator, and the projecting pole of triode is connected to resistance R0's the other end, bias current is connected to resistance R0's one end, just comparator output end alarm signal OT (Over Temperature).

2. The over-temperature detection circuit of a power device according to claim 1, wherein: the outside production of the field effect transistor is introduced by a Deep Trench Isolation (DTI) process into a BCD (bipolar, CMOS and DMOS) process.

3. The over-temperature detection circuit of a power device according to claim 2, wherein: when the DTI process is introduced into the BCD process, the thermal isolation effect of the DTI is avoided, so that the heat energy can be conducted to the PN junction to be detected.

4. The over-temperature detection circuit of a power device according to claim 1, wherein: the emitter of the PN junction in the triode and the field effect transistor share one PGND (Power GND), and the corresponding comparison level corresponds to the same potential.

5. The over-temperature detection circuit of a power device according to claim 1, wherein: the heat energy of the field effect transistor bypasses the DTI through the metal connecting wire of the PGND and is transmitted to the emitting electrode of the triode.

6. The over-temperature detection circuit of a power device according to claim 1, wherein: and the PGND and the B and C end nodes of the triode form a similar finger-inserting capacitance structure on the NPN layout.

7. The over-temperature detection circuit of a power device according to claim 1, wherein: the area of the metal layer completely covers the NPN tube.

8. The over-temperature detection circuit of a power device according to claim 1, wherein: and the PGND and the B and C end nodes of the triode form a similar finger-inserting capacitance structure on the NPN layout.

9. The over-temperature detection circuit of a power device according to claim 1, wherein: all the areas of the above metal layers completely cover the NPN transistor.

10. The over-temperature detection circuit of a power device according to claim 1, wherein: and the PGND and the B and C end nodes of the triode form a similar finger-inserting capacitance structure on the NPN layout.

Technical Field

The invention relates to an over-temperature detection circuit, in particular to an over-temperature detection circuit of a power device, and belongs to the technical field of over-temperature detection circuits.

Background

In power integrated circuits, excessive current flow in the power devices can cause the power modules to heat up dramatically resulting in device damage. For safety reasons, over-temperature detection circuits are introduced to prevent such failures.

Taking a low-side DMOS as an example (figure 1) and used for detecting the temperature of the DMOS, wherein Vref is a band gap reference to generate a temperature insensitive level, an alarm mechanism under a specific temperature is realized by utilizing the negative temperature characteristic of a PN junction point voltage, when the temperature rises, the voltage of VBE is reduced to Vref and is an over-temperature detection point (figure 2), a PN junction of an over-temperature detection circuit is placed on the edge of the DMOS of a power device, and when the DMOS is heated and heated, the temperature of the PN junction is raised by heat conduction on the surface of a wafer. A DTI process is introduced into a DMOS process, an isolation layer of the existing DTI process is realized by air isolation and direct deep-digging groove physical isolation, an oxidation layer is firstly formed in a groove and then is filled with a conducting layer, and in any structure, the DTI is thermal isolation, the heat of a power device is limited in the DTI of the DMOS, so that the heat can not be conducted to a detection PN junction outside the DTI, and further the temperature rise of the DMOS can not be detected.

Disclosure of Invention

The main object of the present invention is to provide an over-temperature detection circuit of a power device (fig. 3), wherein a PN junction emitter of a triode and a field effect transistor share one PGND, a corresponding comparison level also corresponds to the same potential, heat energy of the field effect transistor can bypass a DTI through a metal connection line of the PGND and be transmitted to the emitter of the triode, then the PGND and a B and C end node of the triode form a finger-inserted capacitor structure on an NPN layout, which is used for heating the metal connection lines of the B and C ends of the NPN, thereby heating the NPN transistor, and the areas of all the metal layers need to completely cover the NPN transistor to realize optimal heat conduction (fig. 4, the left side is a DMOS, and the right side is an NPN).

The purpose of the invention can be achieved by adopting the following technical scheme:

the utility model provides a power device's excess Temperature detection circuitry, includes field effect transistor, triode, resistance R0 and signal amplifier, the external load of drain electrode of field effect transistor, field effect transistor's source ground, field effect transistor's grid connects drive circuit, field effect transistor's source electric connection the projecting pole of triode, the external bias current of collecting electrode of triode, the positive pole of projecting pole and comparator is connected to the base of triode, the one end of the negative pole connecting resistance R0 of comparator, the projecting pole of triode is connected to resistance R0's the other end, bias current is connected to resistance R0's one end, just comparator output alarm signal OT (Over Temperature, excess Temperature).

Preferably, the outside production of the field effect transistor is introduced into a BCD (bipolar, CMOS and DMOS) process by a Deep Trench Isolation (DTI) process.

Preferably, when the DTI process is incorporated into the BCD process, thermal isolation of the DTI is avoided so that thermal energy can be conducted to the externally detected PN junction.

Preferably, the emitter of the PN junction in the triode and the field effect transistor share one PGND, and the corresponding comparison level also corresponds to the same potential.

Preferably, the heat energy of the field effect transistor is transmitted to the emitter of the triode by bypassing the DTI through the metal wire of the PGND.

Preferably, the PGND and the B and C end nodes of the triode form a finger-like capacitor structure on the NPN layout.

Preferably, the area of the metal layer completely covers the NPN tube.

Preferably, the PGND and the B and C end nodes of the triode form a finger-like capacitor structure on the NPN layout.

The invention has the beneficial technical effects that:

according to the over-temperature detection circuit of the power device, a PN junction emitter of a triode and a field effect transistor share one PGND, corresponding comparison levels correspond to the same potential, heat energy of the field effect transistor can bypass a DTI through a metal connecting wire of the PGND and is transmitted to the emitter of the triode, then the PGND and a B end node and a C end node of the triode form a finger-inserting capacitor structure on an NPN layout, the finger-inserting capacitor structure is used for heating the metal connecting wires of the B end and the C end of the NPN, the NPN is heated, and the area of all metal layers needs to completely cover the NPN to achieve optimal heat conduction (fig. 4, the left side is a DMOS, and the right side is an NPN).

Drawings

FIG. 1 is a circuit diagram of an over-temperature detection circuit in the prior art;

FIG. 2 is a prior art over-temperature detection circuit layout;

FIG. 3 is an over-temperature detection circuit diagram of a preferred embodiment of an over-temperature detection circuit of a power device according to the present invention;

fig. 4 is a thermal conductive layout of a preferred embodiment of an over-temperature detection circuit of a power device according to the present invention.

Detailed Description

In order to make the technical solutions of the present invention more clear and definite for those skilled in the art, the present invention is further described in detail below with reference to the examples and the accompanying drawings, but the embodiments of the present invention are not limited thereto.

As shown in fig. 3-4, in this embodiment, an Over-Temperature detection circuit of a power device includes a field-effect transistor, a resistor R0 and a signal amplifier, where a drain of the field-effect transistor is externally connected to a load, a source of the field-effect transistor is grounded, a gate of the field-effect transistor is connected to a driving circuit, a source of the field-effect transistor is electrically connected to an emitter of the transistor, a collector of the transistor is externally connected to a bias current, a base of the transistor is connected to the emitter and an anode of a comparator, a cathode of the comparator is connected to one end of a resistor R0, the other end of the resistor R0 is connected to the emitter of the transistor, one end of the resistor R0 is connected to the bias current, and an output end of the comparator is used for providing an alarm signal OT (.

The emitter of the PN junction of the triode and the field effect transistor share one PGND, the corresponding comparison level corresponds to the same potential, the heat energy of the field effect transistor can bypass the DTI through the metal connecting wire of the PGND and is transmitted to the emitter of the triode, and then the PGND and the B and C end nodes of the triode form a finger-inserting capacitor structure on the NPN layout for heating the metal connecting wires at the B and C ends of the NPN so as to heat the NPN, and the area of all the metal layers needs to completely cover the NPN to realize the optimal heat conduction.

In this embodiment, the outside production of the field effect transistor is by introducing a DTI process into the BCD process.

In this embodiment, when the DTI process is introduced into the BCD process, the thermal isolation of the DTI is avoided so that thermal energy can be conducted to the externally detected PN junction.

In this embodiment, the emitter of the PN junction in the transistor shares a PGND with the fet, and the corresponding comparison level corresponds to the same potential.

In this embodiment, the thermal energy of the fet is transferred to the emitter of the transistor through the PGND metal wire, bypassing the DTI.

In the embodiment, the PGND and the B and C end nodes of the triode form a finger-like capacitor structure on the NPN layout.

In this embodiment, the area of the metal layer completely covers the NPN transistor.

In the embodiment, the PGND and the B and C end nodes of the triode form a finger-like capacitor structure on the NPN layout.

The above description is only for the purpose of illustrating the present invention and is not intended to limit the scope of the present invention, and any person skilled in the art can substitute or change the technical solution of the present invention and its conception within the scope of the present invention.