Decision feedback equalizer
阅读说明:本技术 决策反馈均衡器 (Decision feedback equalizer ) 是由 刘熙恩 闵绍恩 谢依峻 于 2019-03-22 设计创作,主要内容包括:本发明公开了一种决策反馈均衡器,其具有第一路径以及第二路径。该第一路径包含了第一取样电路以及第一闩锁电路,其中该第一取样电路用以根据输入信号、第二设定信号以及第二重设信号以产生第一设定信号以及第一重设信号,且该第一闩锁电路用以根据该第一取样电路的输出以产生第一数字信号。该第二路径包含了第二取样电路以及第二闩锁电路,其中该第二取样电路用以根据该输入信号、该第一设定信号以及该第一重设信号以产生该第二设定信号以及该第二重设信号,且该第二闩锁电路用以根据该第二取样电路的输出以产生第二数字信号。(The invention discloses a decision feedback equalizer, which is provided with a first path and a second path. The first path includes a first sampling circuit for generating a first set signal and a first reset signal according to an input signal, a second set signal and a second reset signal, and a first latch circuit for generating a first digital signal according to an output of the first sampling circuit. The second path includes a second sampling circuit and a second latch circuit, wherein the second sampling circuit is used for generating the second setting signal and the second reset signal according to the input signal, the first setting signal and the first reset signal, and the second latch circuit is used for generating a second digital signal according to the output of the second sampling circuit.)
1. A decision feedback equalizer comprising:
a first path comprising:
a first sampling circuit for generating a first setting signal and a first reset signal according to an input signal, a second setting signal and a second reset signal; and
a first latch circuit, coupled to the sampling circuit, for generating a first digital signal according to the first set signal and the first reset signal; and
a second path comprising:
a second sampling circuit for generating the second setting signal and the second reset signal according to the input signal, the first setting signal and the first reset signal; and
a second latch circuit, coupled to the second sampling circuit, for generating a second digital signal according to the second setting signal and the second reset signal;
wherein the first sampling circuit comprises:
a sense amplifier for receiving the input signal and generating an amplified input signal at an end; and
an adjusting circuit, coupled to the terminal of the sense amplifier, for generating an adjusting signal to the terminal according to the second setting signal and the second resetting signal to adjust the voltage level of the amplified input signal;
wherein the first setting signal and the first reset signal are generated according to the amplified input signal.
2. The dfe of claim 1, wherein the first digital signal is used as odd bits of an output digital signal of the dfe, and the second digital signal is used as even bits of the output digital signal of the dfe.
3. The dfe of claim 1, wherein the adjusting circuit comprises:
a first differential amplifier selectively enabled according to the second setting signal to generate a first adjusting signal to the terminal according to a first differential voltage signal to adjust the voltage level of the amplified input signal; and
a second differential amplifier selectively enabled according to the second reset signal to generate a second adjustment signal to the terminal according to a second differential voltage signal to adjust the voltage level of the amplified input signal.
4. The dfe of claim 3, wherein the input signal is a differential input signal, and the differential input signal, the first differential voltage signal and the second differential voltage signal have the same common mode voltage.
5. The dfe of claim 3, wherein the sense amplifier comprises a sense amplifier switch controlled by a clock signal to determine whether the sense amplifier switch is enabled or not, the source of the transistor of the first differential amplifier is connected to the sense amplifier switch through a first switch, and the source of the transistor of the second differential amplifier is connected to the sense amplifier switch through a second switch, wherein the first switch and the second switch are controlled by the second setting signal and the second resetting signal, respectively.
6. The dfe of claim 5, wherein the drain of the transistor of the first differential amplifier is directly connected to the terminal of the sense amplifier, and the drain of the transistor of the second differential amplifier is directly connected to the terminal of the sense amplifier.
7. The dfe of claim 1, wherein the adjusting circuit comprises:
a first differential amplifier selectively enabled according to the second setting signal and a clock signal to generate a first adjusting signal to the terminal according to a first differential voltage signal to adjust a voltage level of the amplified input signal; and
a second differential amplifier selectively enabled according to the second reset signal and the clock signal to generate a second adjustment signal to the terminal according to a second differential voltage signal to adjust the voltage level of the amplified input signal.
8. The dfe of claim 7, wherein the input signal is a differential input signal, and the differential input signal, the first differential voltage signal, and the second differential voltage signal have the same common mode voltage.
9. The dfe of claim 7, wherein the sense amplifier comprises a sense amplifier switch controlled by a clock signal to determine whether to enable or disable, the source of the transistor of the first differential amplifier is connected to a reference voltage through a first switch, and the source of the transistor of the second differential amplifier is connected to the reference voltage through a second switch, wherein the first switch is controlled by the second setting signal and the clock signal at the same time, and the second switch is controlled by the second resetting signal and the clock signal at the same time.
10. The dfe of claim 9, wherein the drain of the transistor of the first differential amplifier is directly connected to the terminal of the sense amplifier, and the drain of the transistor of the second differential amplifier is directly connected to the terminal of the sense amplifier.
Technical Field
The invention relates to a decision feedback equalizer.
Background
A Decision Feedback Equalizer (DFE) is a technique often used at a receiving end of a high-speed cable transmission system to compensate channel loss or channel reflection (channel reflection) of a transmission signal due to various transmission processes, and its main operation principle is to eliminate Inter-symbol interference (ISI) that is known to affect a following signal through a set of tap parameters (tap coefficients) obtained by an adaptive algorithm (adaptation) and a currently received digital signal. In analog circuits of high speed decision feedback equalizers, the most difficult part to implement is the feedback of the first tap (first tap), since in principle the delay of the feedback signal through the sampler (sampler), the propagation delay of the feedback path and the summer delay have to be prepared before the next data, especially at higher speeds the timing constraints are tighter.
To solve this problem, some patent technologies (for example, US7869498 and US8477833) and papers propose related decision feedback equalization circuit architectures, however, these technologies have temperature drift problems in the design of the junction parameters, and therefore, the junction parameters must be adjusted depending on background correction (background calibration), thereby increasing the instability and complexity of the circuit.
Disclosure of Invention
Therefore, one of the objectives of the present invention is to provide a decision feedback equalizer having the advantages of high speed, low temperature effect, low power consumption, no need of background correction to adjust the tap parameter …, etc., so as to solve the problems in the prior art.
In one embodiment of the present invention, a decision feedback equalizer is disclosed having a first path and a second path. The first path includes a first sampling circuit and a first latch circuit, wherein the first sampling circuit is used for generating a first setting signal and a first reset signal according to an input signal, a second setting signal and a second reset signal, and the first latch circuit is used for generating a first digital signal according to the first setting signal and the first reset signal. The second path includes a second sampling circuit and a second latch circuit, wherein the second sampling circuit is used for generating the second setting signal and the second resetting signal according to the input signal, the first setting signal and the first resetting signal, and the second latch circuit is used for generating a second digital signal according to the second setting signal and the second resetting signal.
Drawings
Fig. 1 is a schematic diagram of a decision feedback equalizer according to an embodiment of the invention.
Fig. 2 is a timing diagram of a plurality of signals within a decision feedback equalizer.
Fig. 3 is a circuit architecture diagram of a first path and a second path according to an embodiment of the invention.
FIG. 4 is a diagram of a sampling circuit according to a first embodiment of the present invention.
FIG. 5 is a timing diagram of a plurality of signals of the sampling circuit of FIG. 4.
FIG. 6 is a diagram of a sampling circuit according to a second embodiment of the present invention.
FIG. 7 is a timing diagram of a plurality of signals of the sampling circuit of FIG. 6.
Description of the symbols
100 decision feedback equalizer
102. 112, 122 summing circuit
108 multiplexer
110 first path
114. 124, 314, 324 sampling circuit
120 second path
316. 326 latch circuit
410. 610 sense amplifier
412. 414, 612, 614 inverters
420. 620 regulating circuit
CK. CKB clock signal
D _ odd first digital signal
D _ even second digital signal
Dout output digital signal
M1-M13 transistor
S _ odd first setting signal
S _ even second setting signal
R _ odd first reset signal
R _ even second reset signal
Vin input signal
Vin ', Vin ' +, Vin ' -adjusted input signal
Feedback signals of VFB1_ even, VFB1_ odd and VFB2
Voltage of Vh1
VCM common mode Voltage
Detailed Description
Fig. 1 is a diagram of a decision feedback equalizer 100 according to an embodiment of the invention. As shown in fig. 1, the dfe 100 includes a summing circuit 102, a first path 110, a second path 120, and a multiplexer 108, wherein the first path 110 includes a summing circuit 112 and a sampling circuit 114, and the second path 120 includes a summing circuit 122 and a sampling circuit 124.
The dfe 100 shown in fig. 1 employs two paths and half-rate (half-rate) multiplexing to achieve the purpose of reducing the operation delay. Specifically, referring to the timing diagram of fig. 2, in the operation of the dfe 100, the summing circuit 102 subtracts a feedback signal VFB2 from the input signal Vin to generate an adjusted input signal Vin ', and then the summing circuit 112 in the first path 110 subtracts a feedback signal VFB1_ even from the adjusted input signal Vin' and samples the signal with a clock signal CK through the sampling circuit 114 to generate a first digital signal D _ odd; and the summing circuit 122 in the second path 120 subtracts a feedback signal VFB1_ odd from the adjusted input signal Vin' and samples the subtracted signal with a clock signal CKB by the sampling circuit 124 to generate a second digital signal D _ even. Then, the multiplexer 108 outputs the first digital signal D _ odd and the second digital signal D _ even alternately as the output digital signal Dout of the decision feedback equalizer 100 through the control of the clock signal CKB. For example, assuming that the input signal Vin sequentially includes the bit A, B, C, D, E, the clock signals CK and CKB have a frequency half of the frequency of the input signal Vin, the first digital signal D _ odd generated by the sampling circuit 114 includes A, C, E, and the second digital signal D _ even generated by the sampling circuit 124 includes B, D, i.e., the first digital signal D _ odd is used as the odd bits of the output digital signal Dout, and the second digital signal D _ even is used as the even bits of the output digital signal Dout.
In fig. 1, the feedback signal VFB2 is generated by adjusting the output digital signal Dout according to the tap parameter h2, the feedback signal VFB1_ even is generated by adjusting the second digital signal D _ even according to the tap parameter h1, and the feedback signal VFB1_ odd is generated by adjusting the first digital signal D _ odd according to the tap parameter h 1. As described in the prior art, in the high-speed decision feedback equalizer, the most difficult part to implement is the feedback of the first tap (i.e., the related operations of the feedback signal VFB1_ even and the feedback signal VFB1_ odd), so in order to reduce the feedback delay, the present invention embeds the feedback function in the sampling circuit, and the specific implementation manner thereof is as follows.
Fig. 3 is a circuit architecture diagram of the first path 110 and the second path 120 according to an embodiment of the invention. In fig. 3, the first path 110 includes a
Fig. 4 is a schematic diagram of a
The architecture of the sampling circuit 324 is similar to that of the
As shown in the circuit architectures of fig. 3 and 4, since the first setting signal S _ odd and the first resetting signal R _ odd generated by the
In this example, the common-mode voltage VCM of the differential signal received by the first differential amplifier (i.e., the transistors M10, M11) and the second differential amplifier (i.e., the transistors M12, M13) in the adjusting circuit 420 is the same as the common-mode voltage of the adjusted input signal Vin ' (including the differential signals Vin ' +, Vin ' -), so that the sense amplifier 410 and the adjusting circuit 420 have the same/similar variation under the different process, temperature, and voltage (voltage), i.e., the adjusting signal generated by the adjusting circuit 420 can actually have the voltage Vh1 without being varied with the temperature. On the other hand, since the voltage Vh1 does not vary with temperature, the adaptive algorithm of the connector parameter h1 can be executed without background when the electronic device is powered on, thereby indirectly reducing the system complexity.
FIG. 6 is a diagram of a
The architecture of the sampling circuit 324 is similar to that of the
As shown in the circuit architectures of fig. 3 and fig. 6, since the first setting signal S _ odd and the first resetting signal R _ odd generated by the
In this example, the common-mode voltage VCM of the differential signal received by the first differential amplifier (i.e., the transistors M10, M11) and the second differential amplifier (i.e., the transistors M12, M13) in the adjusting
The above-mentioned embodiments are only preferred embodiments of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the scope of the present invention.
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