阅读说明：本技术 用于ePWM模块的移相控制方法、装置和存储介质 (Phase shift control method and device for ePWM module and storage medium ) 是由 刘昌赫 于 2020-07-13 设计创作，主要内容包括：提出用于ePWM模块的移相控制方法、装置和存储介质。ePWM模块生成第一和第二PWM信号,当定时器的定时器值与第一比较值匹配时执行高、低电平信号的第一切换操作,当定时器值与定时器周期值匹配时执行高、低电平信号的第二切换操作。在目标相位设定值使得相位差发生在滞后和超前相位之间的转变,以及定时器的先前相位设定值位于被限定为初始值与第一比较值之间的第一区间并且目标相位设定值位于被限定为第一比较值和定时器周期值之间的第二区间时,设置位于定时器的初始值与先前相位设定值之间的第二比较值以使得ePWM模块在定时器值与第二比较值匹配时执行高、低电平信号的与第一切换操作相同的第三切换操作。(A phase shift control method, apparatus and storage medium for an ePWM module are presented. The ePWM module generates first and second PWM signals, performs a first switching operation of high and low level signals when a timer value of a timer matches a first comparison value, and performs a second switching operation of high and low level signals when the timer value matches a timer period value. When the target phase setting value causes a transition of the phase difference between the lag and lead phases, and the previous phase setting value of the timer is in a first interval defined between the initial value and the first comparison value and the target phase setting value is in a second interval defined between the first comparison value and the timer period value, setting a second comparison value located between the initial value of the timer and the previous phase setting value to cause the ePWM module to perform a third switching operation of the high and low level signals identical to the first switching operation when the timer value matches the second comparison value.)

1. A phase shift control method for an enhanced pulse width modulation (ePWM) module configured to: generating a first PWM signal and a second PWM signal, a timer value of a timer for the second PWM signal being counted from an initial value to a timer period value in each PWM signal period, a first switching operation of a high level signal and a low level signal of the second PWM signal being performed when the timer value matches a first comparison value between the initial value and the timer period value, a second switching operation of a high level signal and a low level signal of the second PWM signal being performed when the timer value matches the timer period value, and a phase difference between the second PWM signal and the first PWM signal being controlled based on a phase setting value of the timer, wherein the first switching operation is opposite to the second switching operation, the phase shift control method comprising:

setting a second comparison value of the timer to cause the ePWM module to perform a third switching operation of a high level signal and a low level signal of the second PWM signal when the timer value matches the second comparison value when the target phase setting value causes the phase difference to transition between a lag phase and a lead phase and a previous phase setting value of the timer is located in a first interval defined between the initial value and the first comparison value and the target phase setting value is located in a second interval defined between the first comparison value and the timer period value,

wherein the third switching operation is the same as the first switching operation, and the second comparison value is between the initial value of the timer and the previous phase setting value.

2. The phase shifting control method according to claim 1, wherein setting the second comparison value of the timer so that the ePWM module performs a third switching operation of a high level signal and a low level signal of the second PWM signal when the timer value matches the second comparison value comprises:

setting a phase setting value of the timer to a phase setting value of the first PWM signal in a current period of the second PWM signal;

setting a phase setting value of the timer to the target phase setting value and setting the second comparison value in a next period of the second PWM signal; and

setting the second comparison value to 1/2 of the timer period value of the timer for a further next period of the second PWM signal.

3. The phase shift control method according to claim 2, wherein the PWM interruption of the second PWM signal is turned on before the phase setting value of the timer is set to the phase setting value of the first PWM signal, and the PWM interruption of the second PWM signal is turned off after the second comparison value is set to 1/2 of the timer period value of the timer.

4. The phase shifting control method according to any one of claims 1 to 3, wherein the second comparison value is determined by:

wherein CMPB is the second comparison value, PRD is the timer period value, PHS1 is the previous phase setting value of the second PWM signal, and PHS2 is the target phase setting value of the second PWM signal.

5. The dephasing control method according to any one of claims 1 to 3, characterized in that the target phase setting is set when receiving the synchronization signal of the ePWM module.

6. The phase shift control method according to any one of claims 1 to 3, characterized in that counting is continued from the target phase setting value when the timer value is set to the target phase setting value.

7. The phase shift control method according to any one of claims 1 to 3, wherein the phase setting value of the timer is set to the target phase setting value and counting is continued from the target phase setting value when the previous phase setting value of the timer is in the second interval and the target phase setting value is in the first interval.

8. The phase shifting control method according to any one of claims 1 to 3, wherein the ePWM module is a DSP, a CPU or a microcontroller.

9. The phase shifting control method according to any one of claims 1 to 3, wherein the ePWM module has a plurality of PWM channels, each channel generating the first and second PWM signals.

10. An apparatus for phase shift control, the apparatus comprising a processor and a memory, the processor being configured to perform the steps of the method of any one of claims 1 to 9.

11. A computer-readable storage medium having stored thereon a computer program comprising instructions which, when executed by a processor, cause the processor to carry out the method of any one of claims 1 to 9.

Technical Field

The present disclosure relates to signal driving, and more particularly, to a phase shift control method, apparatus, and storage medium for Enhanced Pulse width modulation (ePWM) module.

Background

The ePWM module for generating the PWM signal to drive the electric device can simply realize a phase shift control mode such as the PWM driving between bridges, wherein the phase shift comprises a lag phase shift and a lead phase shift. each complete PWM channel in the ePWM module consists of two PWM signal outputs, referred to as PWMxA and PWMxB. The PWM signals of the respective channels establish a synchronization mechanism by the synchronization signal. One advantage of the ePWM module over the conventional PWM module is that the phase difference between PWM signals in each channel can be controlled by directly configuring the phase register, so as to simply implement phase shifting.

However, the ePWM module is restricted by a phase shift mechanism when performing phase shift control, and when the phase of the PWM signal crosses from a lagging phase to a leading phase or from a leading phase to a lagging phase, there is a problem that the waveform is lost in a specific case. Part of the waveform loss during phase shifting may cause a change in the duty cycle of the PWM signal output, resulting in a dc offset of the periodically varying operating current, thereby adversely affecting circuit elements, particularly power devices.

There is therefore a need for an improvement in the phase shifting mechanism of the ePWM module to avoid waveform loss in the above-described situation.

Disclosure of Invention

In order to solve the above problem, the present disclosure provides a phase shift control method and apparatus for an ePWM module, and a storage medium.

According to an aspect of the present disclosure, a phase shift control method for an enhanced pulse width modulation (ePWM) module is presented, the ePWM module being configured to: generating a first PWM signal and a second PWM signal, a timer value of a timer for the second PWM signal being counted from an initial value to a timer period value in each PWM signal period, a first switching operation of a high level signal and a low level signal of the second PWM signal being performed when the timer value matches a first comparison value between the initial value and the timer period value, a second switching operation of a high level signal and a low level signal of the second PWM signal being performed when the timer value matches a timer period value, and a phase difference between the second PWM signal and the first PWM signal being controlled based on a phase setting value of the timer, wherein the first switching operation is opposite to the second switching operation, the phase shift control method comprising:

setting a second comparison value of the timer to cause the ePWM module to perform a third switching operation of a high level signal and a low level signal of the second PWM signal when the timer value matches the second comparison value when the target phase setting value causes a transition of the phase difference between a lag phase and a lead phase and a previous phase setting value of the timer is located in a first interval defined between the initial value and the first comparison value and the target phase setting value is located in a second interval defined between the first comparison value and the timer period value,

wherein the third switching operation is the same as the first switching operation, and the second comparison value is between the initial value of the timer and the previous phase setting value.

According to one embodiment, setting the second comparison value of the timer such that the ePWM module performs the third switching operation of the high level signal and the low level signal of the second PWM signal when the timer value matches the second comparison value comprises: setting a phase setting value of the timer to a phase setting value of the first PWM signal in a current period of the second PWM signal; setting a phase setting value of the timer to the target phase setting value and setting the second comparison value in a next period of the second PWM signal; and 1/2 setting the second comparison value to the timer period value of the timer in a further next period of the second PWM signal.

According to one embodiment, the PWM interrupt of the second PWM signal is turned on before the phase setting of the timer is set to the phase setting of the first PWM signal, and the PWM interrupt of the second PWM signal is turned off after the second comparison value is set to 1/2 of the timer period value of the timer.

According to one embodiment, the second comparison value is determined by:

wherein CMPB is the second comparison value, PRD is the timer period value, PHS1 is the previous phase setting value of the second PWM signal, and PHS2 is the target phase setting value of the second PWM signal.

According to one embodiment, the target phase setting value is set upon receiving a synchronization signal of the ePWM module.

According to one embodiment, counting from the target phase setting value is continued when the timer value is set to the target phase setting value.

According to one embodiment, the phase setting value of the timer is set to the target phase setting value and counting is continued from the target phase setting value when the previous phase setting value of the timer is located in the second interval and the target phase setting value is located in the first interval.

According to one embodiment, the ePWM module is a DSP, a CPU, or a microcontroller.

According to one embodiment, the ePWM module has a plurality of PWM channels, each channel generating the first and second PWM signals.

According to another aspect of the present disclosure, an apparatus for phase shift control is presented, the apparatus comprising a processor and a memory, the processor being configured to perform the steps of the method as described above.

According to yet another aspect of the present disclosure, a computer-readable storage medium is proposed, on which a computer program comprising instructions is stored, which instructions, when executed by a processor, cause the processor to carry out the method as described above.

By adopting the improved phase shift control method disclosed by the disclosure, when a transition from a phase lead to a phase lag exists between a target phase setting value and a previous phase setting value input aiming at a PWM signal, the ePWM module does not lack a small part of waveform in the waveform of the output PWM signal, so that the phase of the PWM signal is ensured to be set and changed in a desired manner, and stable and safe circuit element driving is realized.

Drawings

The above and other features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

Fig. 1 is a timing diagram illustrating two PWM signal waveforms and timer value changes in one PWM channel of an ePWM module based on a conventional phase shift control method;

fig. 2 is a timing diagram of two PWM signal waveforms and timer value changes in one PWM channel of an ePWM module based on a phase shift control method according to an embodiment of the present disclosure;

FIG. 3 is a schematic flow diagram of controlling phase shifting operation of an ePWM module based on a phase shifting control method according to an embodiment of the present disclosure;

FIG. 4 is a schematic block diagram of a phase shift control device according to an embodiment of the present disclosure; and

fig. 5 is a schematic structural view of a phase shift control device according to another embodiment of the present disclosure.

Detailed Description

Exemplary embodiments will now be described more fully with reference to the accompanying drawings. The exemplary embodiments, however, may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. In the drawings, the size of some of the elements may be exaggerated or distorted for clarity. The same reference numerals denote the same or similar structures in the drawings, and thus detailed descriptions thereof will be omitted.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, etc. In other instances, well-known structures, methods, or operations are not shown or described in detail to avoid obscuring aspects of the disclosure.

Implementation of the dephasing control method, apparatus and storage medium thereof according to the present disclosure is described herein with an ePWM module in the TI corporation c2000 series DSP as an example ePWM module. Those skilled in the art will appreciate that the methods of the present disclosure may be applied to any PWM module other than a c2000 series DSP capable of providing ePWM control and drive functions using a phase shifting mechanism. These modules may be implemented in various forms such as a DSP, a CPU, a single chip, a controller, a microcontroller, an integrated circuit, a circuit module, a combination of hardware and/or software, and the like.

The problem of PWM waveform loss in some cases for the phase shifting mechanism of the ePWM module is described below in conjunction with fig. 1.

Fig. 1 shows a timing diagram of two PWM signal waveforms and timer value changes in one PWM channel of an ePWM module based on a conventional phase shift control method, where the upper half is the timing of the signal waveform 120 of the first PWM signal PWM1 of one complete PWM channel in c2000 and the timer value change 110 of the timer 1 corresponding thereto, and the lower half is the timing of the signal waveform 220 of the second PWM signal PWM2 in the PWM channel and the timer value change 210 of the timer 2 corresponding thereto.

First, the operating principles and characteristics of the PWM signals generated by the two PWM channels in the ePWM module are described.

For PWM signals, the timer value of the timer may be incremented or decremented from an initial value to the timer period value PRD in each period, and the process repeated in the next period. According to the embodiment of the present disclosure, the timer may also be an up-down counting mode that counts up/down from the initial value to the timer period value PRD and then counts down/increments in reverse from the timer period value PRD to the initial value in each period. The parameter to increment the countdown may be manually configured by the corresponding register. For example, if the counting step is a positive integer, in the up-counting mode, the initial value of the timer may be set to be smaller than the timer period value PRD; in the down-counting mode, the initial value of the timer may be set to be greater than the timer period value PRD. The timer count-down may also be viewed as the timer "incrementing" the count in count units of negative values. For example, the initial value of the timer may be selected to be 0, the timer period value PRD may be a positive integer greater than 0, and the timer value may be incremented by 1 each time. The periodic variation of the timer value may be indicative of a phase change of the PWM signal, each time the timer value is increased or decreased, corresponding to a respective phase increase. For example, if the initial value of the timer is 0 and the timer period value is 100, then in the process of counting up by 0 to 100, regardless of the initial phase value of the PWM signal at the beginning of the period, the phase of the PWM signal changes by 360 degrees within one period, and each time the value of the timer is incremented by 1, the phase value that changes with it is 360/(timer period value-timer initial value) ═ 360/(100-0) ═ 3.6 degrees.

When the timer value is updated with the target phase setting value in the phase register, the timer value update becomes effective at the next time of receiving the synchronization signal in the present period. Here, the phase register is also a timer value register of the timer. By setting and/or updating a timer value corresponding to a PWM desired phase, which is hereinafter referred to as a target phase setting value PHS, switching operation of a PWM signal between a high level signal and a low level signal at the PWM desired phase can be controlled by a timer. After the timer value is updated to the target phase setting value PHS, the timer continues to count up until the timer period value PRD completes the period timing of the current period, so that the PWM period for updating the target phase setting value PHS may have a condition of ending the PWM period in advance.

According to an embodiment of the present disclosure, the phase difference between the second PWM signal PWM2 and the first PWM signal PWM1 as a reference signal may be defined from where the corresponding waveform of the second PWM signal PWM2 is located at the beginning of each cycle of the first PWM signal PWM 1. For example, when the first PWM signal PWM1 occurs a voltage rising edge (falling edge) at the beginning of a cycle, and the corresponding voltage rising edge (falling edge) of the second PWM signal PWM2 occurs later, then the second PWM signal PWM2 lags the phase of the first PWM signal PWM 1; the phase of the second PWM signal PWM2 leads the phase of the first PWM signal PWM1 if the corresponding voltage rising edge (falling edge) of the second PWM signal PWM2 occurs earlier than the PWM 1.

Assuming that the timer value of the timer is 0 to PRD (for up-counting) or PRD to 0 (for down-counting) for the case where the initial phase setting value PHS of the timer is set with the timer, for example, the initial phase setting value PHS of the timer as the first PWM signal PWM1 of the reference PWM signal may be set to PRD/2, representing that the timer value as the timer of the first PWM signal PWM1 is PRD/2 at the synchronization timing of each cycle. At this time, the initial phase setting PHS of the timer of the second PWM signal PWM2 may be PRD/2, which is 0 degree relative to the phase shift of the first PWM signal PWM 1.

The timing diagram of the waveform and timer value variation of the two PWM signals PWM1 and PWM2 of the ePWM module as described in fig. 1 shows a more general case. Here, the initial phase setting value of the timer of the first PWM signal PWM1 as the reference signal is set to 0, and the initial phase setting value PHS1 of the timer of the second PWM signal PWM2 is set to a value greater than 0 (which is also smaller than the comparison value CMPA2 of the PWM2, which will be described in detail later). Although the initial phase settings of the two PWM signals in fig. 1 are not the same (e.g., neither is equal to half the respective timer period value), the decision principles regarding the phase lag and lead between the second PWM signal PWM2 and the first PWM signal PWM1 are similar to those described above. The target phase setting PHS1 of the second PWM signal PWM2 is in the interval (0, PHD/2) representing that the second PWM signal PWM2 is phase-retarded with respect to the PWM1, and then the target phase setting PHS2 of the second PWM signal PWM2 is set to be in the interval (PRD/2, PRD) representing that the second PWM signal PWM2 is phase-advanced with respect to the PWM1, i.e., the phase difference is shifted between phase-retarded and phase-advanced.

In the ePWM module, updating the timer value is done by signal synchronization. In the phase shift and multi-way PWM signal synchronization process, the desired target phase setting value PHS (i.e., the updated timer value) may be calculated at any time within the cycle, but the target phase setting value PHS needs to be written or loaded into the phase register at the instant of receiving the synchronization signal. Therefore, upon receipt of the synchronization signal by the ePWM module, a new target phase setting value PHS is written in the phase register of the timer, and the timer continues to count back with the updated or loaded timer value (i.e., the target phase setting value PHS). The ePWM module realizes the time synchronization of each path of PWM signals by loading the updated value of the phase register at the moment of receiving the synchronous signals. For example, in the case of count-up, if the initial phase setting values PHS of the phase registers of the first and second PWM signals PWM1 and PWM2 are both 50(PRD is 100, PRD/2 is 50), 50 is written into the counter of the respective timers at the same time at the instant when the first synchronization signal is received, the two PWM signals are counted from the timer value 50 at the same time, and the phase difference between the two PWM signals is 0. If the target phase setting value PHS of the phase register of the second PWM signal is set to 30, at the instant of receiving the synchronization signal, the counter of the timer of the second PWM signal PWM2 starts counting at 30, which is loaded, while the counter of the timer of the first PWM signal PWM1 still starts counting at 50, resulting in that the time at which the timer value counted by the counter of the timer of the PWM2 signal reaches its comparison value CMPA2 is counted 20(50-30) times later than the time at which the timer value counted by the counter of the timer of the PWM1 signal reaches its comparison value CMPA1, i.e., the phase of the PWM2 signal lags behind the phase of the PWM1 signal by 20 count steps. From the above correspondence of step size to phase, the phase lag value can be easily calculated. According to embodiments of the present disclosure, the synchronization signal may be generally transmitted at the beginning of each PWM period of the reference PWM signal.

The ePWM module controls the duty cycle of the PWM signal using the comparison value CMP. The comparison value CMP may be divided into a first comparison value CMPA and a second comparison value CMPB. The comparison value CMP is a value between the initial value of the timer and the timer period value as a condition for triggering switching between the high level signal and the low level signal of the PWM signal. When the timer value of the timer and the comparison value CMP match (e.g., are equal to each other), the trigger condition is satisfied, and a switching operation (i.e., a change from a high level to a low level, or a change from a low level to a high level) occurs between the high level signal and the low level signal of the PWM signal. When the timer value counts to the timer period value PRD, the switching operation occurs again between the high level signal and the low level signal of the PWM signal, and the period ends. The switching operation at the end of the period is opposite to the switching operation triggered when the comparison value CMP is matched, and if the switching operation when the comparison value CMP is matched is changed from the high level to the low level, the switching operation at the end of the period is changed from the low level to the high level, and vice versa. By setting the position of the comparison value in the value range of the timer, the proportion of the high-level signal part and the low-level signal part of the PWM signal in one period, namely the duty ratio, can be adjusted.

The comparison value CMP is updated by a comparison value register written into a timer. Unlike the target phase setting PHS, the updated comparison value CMP may take effect in the current cycle if it is located between the current timer value of the timer and the timer cycle value. If the updated comparison value CMP is between the initial value of the timer and the current timer value, and the matching triggering time of the comparison value CMP is already missed, it needs to take effect in the next PWM period and trigger the matching operation when the timer counts the updated comparison value CMP.

It follows that the switching of the high and low level signals of the PWM signal only occurs at two instants when the matching condition of the comparison value CMP is satisfied and when the timer count reaches the timer period value PRD.

Turning now to the general case shown in FIG. 1, a continuation of the phase shift control method according to embodiments of the present disclosure is described. The first PWM signal PWM1 generally serves as a reference signal to set the initial value 101 of the timer 1, the timer period value PRD 1102 of the timer 1, and the first comparison value CMPA1 of the timer 1 when initializing the ePWM module. The PWM1 signal switches from a high level signal to a low level signal when the trigger condition of CMPA1 is satisfied, and switches back from a low level signal to a high level signal when timer 1 counts to timer period value PRD 1. The initial phase setting of the timer of the first PWM signal PWM1 may be set and maintained at 0. In fig. 1, the operation principle of the method according to the embodiment of the present disclosure is illustrated in an up-counting manner, and a phase shift control method may also be implemented in a down-counting manner by those skilled in the art based on the present disclosure.

The second PWM signal PWM2 sets the initial value 201 of the timer 2, the timer period value PRD 2202 of the timer 2, and the first comparison value CMPA2 of the timer 2 when initializing the ePWM module. The PWM2 signal switches from a low level signal to a high level signal when the trigger condition of CMPA2 is met, and switches back from a high level signal to a low level signal when timer 2 counts to the timer period value PRD 2. In order to realize the phase shift control in a continuous interval, the signal waveform of the second PWM signal PWM2 of the ePWM module is set to be opposite in polarity to the signal waveform of the first PWM signal PWM1, that is, the switching operations of the two PWM signals at the high and low levels at the two moments when the comparison value is satisfied and the timer period value is counted are respectively opposite.

The second PWM signal PWM2 updates the current timer value of the timer 2 at the first synchronization timing Sync1 according to the target phase setting value PHS1 set in the phase register in the first PWM period. The initial phase setting PHS1 (or may be referred to as a previous phase setting) of the second PWM signal PWM2 is set to a value that is less than the first comparison value CMPA2 and greater than the initial value 201 (e.g., 0) of the timer 2, i.e., PHS1 is located between the initial value 201 and the first comparison value CMPA2, when the second PWM signal PWM2 is phase-lagging with respect to PWM1, for example. While the first PWM signal PWM1 is used as a reference signal, and the timer value of the timer 1 at the time of generation of the synchronization signal Sync1 is always at its initial phase setting value (e.g., 0), the lagging phase of the PWM2 to the PWM1 signal can be calculated to be 360 x (PHS1 — initial value of timer 2)/PRD 2 degrees based on the updated timer value of the PWM2 signal (i.e., PHS 1). The PWM2 signal continues to count by timer 2 for the remainder of the PWM cycle, and when the match condition is met when CMPA2 is counted, the PWM2 signal switches from low to high and back to low at the end of the cycle, enabling normal phase-lagging PWM operation.

The phase register value of the timer 2 of the PWM2 signal is unchanged when the second synchronization signal Sync2 is received in the second PWM period, the lagging phase of the previous PWM period is maintained, and the process of switching the PWM2 signal from the low level to the high level and back to the low level signal is repeated.

Upon receiving the third synchronization signal Sync3 in the third PWM period, the PWM2 signal receives the new target phase setting PHS2 written in the phase register of the timer 2, updates the current timer value 204 of the timer 2 to the target phase setting PHS2, see the jump of the timer value variation curve from 204 to PHS2 in fig. 1. When the target phase setting PHS2 is greater than the first comparison value CMPA2, the PWM2 signal waveform is shifted from the low-level phase section corresponding to the previous phase setting PHS1 to the phase section corresponding to the target phase setting PHS2, which is supposed to be high, i.e., shifted from the phase-lag section to the phase-lead section, so that a phase shift transition occurs in which the second PWM signal PWM2 lags the phase of the previous cycle to the phase of the present cycle in comparison with the reference PWM signal PWM 1.

Timer 2 continues to count up from the updated timer value (i.e., target phase setting PHS2) until the timer period value PRD2 is reached. Since the phase of the PWM2 signal lags behind the PWM1 signal during the previous PWM cycle, the PWM2 signal is still in a low state at the third synchronization time Sync 3. During the period from the third synchronization time Sync3 to the end of the period, the timer 2 cannot count up to the first comparison value CMPA2 again due to updating, and the switching time point of the high-level and low-level switching of the timer value matched with the first comparison value CMPA2 is missed, so that the PWM2 signal no longer generates the low-level to high-level switching operation triggering the PWM2 signal. At the end of the present PWM cycle, the PWM2 signal needs to go low again so that the PWM2 signal continues to remain low, as configured in advance. The low signal state of the PWM2 signal remains until the timer value of timer 2 for the next PWM cycle counts to CMPA2 before the PWM2 signal switches high again.

As shown in block 230 of fig. 1, the high-level PWM waveform signal portion is lost during the time period starting when the PWM2 signal switches from high to low before being received from the third synchronization signal Sync3 until the end of the time when the CMPA2 condition match triggers a low-level switch to high in the next cycle. This partial waveform loss not only results in an undesirable change in the duty cycle of the PWM2 signal output, but also causes a current bias to occur in the periodically varying operating current. For example, in the application scenario of phase shift control between two active bridge bidirectional DC-DC converters, loss of part of the waveform during phase shift causes change of the output duty ratio of the H-bridge, and the DC offset on the periodically changing working current is superimposed on the working current with a large peak value in a high-power situation, which easily causes saturation of the inductor or the transformer, and finally burns out the power device. This waveform loss condition has a greater negative impact on the consecutive late phase to early phase transitions.

The above problem of waveform loss is explained based on the phase shift operation in which the phase setting value of the PWM2 signal is changed from a value PHS1 smaller than the first comparison value CMPA2 to a value PHS2 larger than CMPA2, i.e., the transition from the previous lag phase to the next lead phase, in the case where the counter of the timer is counted up from the initial value (e.g., 0) to the timer period value PRD2, wherein the new target phase setting value PHS2 is located between the CMPA2 and the timer period value PRD, and the previous phase setting value PHS1 of the timer is located between the initial value and the CMPA 2. It should be noted, however, that in the case where the counter for the timer counts down from the initial value to the timer period value PRD2 (i.e., the initial value is greater than PRD2), or the counter counts down from the timer period value PRD2 in reverse to the initial value (e.g., 0), there is also a problem of waveform loss when the new target phase setting PHS2 causes the PWM2 signal to undergo a phase shift operation in which the leading phase transitions to the lagging phase relative to the previous phase setting PHS1, at which time the new target phase setting PHS2 is less than CMPA2, while the previous phase setting PHS1 is greater than CMPA2, or PHS2 is between the initial value of the counter and CMPA2, while the previous phase setting PHS1 is between CMPA2 and the timer period value PRD 2. It can be seen that the counter of the timer, whether counting up from a smaller initial value to a larger timer period value PRD2 or counting down from a larger initial value to a smaller timer period value PRD2, has the problem of a lost waveform as long as the previous phase setting PHS1 is in the first interval defined between the initial value and CMPA2 and the updated target phase setting PHS2 is in the second interval defined between CMPA2 and the timer period value PRD, except that the transition direction of the phase difference is reversed, with the transition from the lagging phase to the leading phase in the count up and the leading phase in the count down. Therefore, when the new target phase setting value of the timer is set so that any one of the two-way transitions between the leading phase and the lagging phase occurs in the phase of the PWM2 signal, and the previous phase setting value PHS1 falls within the above-described first section, and the updated target phase setting value PHS2 falls within the above-described second section, it is necessary to consider the problem of the PWM signal waveform loss.

Fig. 2 shows a timing diagram of two PWM signal waveforms and timer value changes in one PWM channel of an ePWM module according to an improved phase shift control method of an embodiment of the present disclosure. The arrangement of the two PWM signals PWM1 and PWM2 is similar to that in fig. 1, and the following mainly describes the technical details of the improvement with respect to fig. 1.

The phase shift control method shown in fig. 2 has the same timing of the PWM2 signal when the Sync signal Sync1 is received as in fig. 1. In order to avoid missing the opportunity to compare the timer value of the timer 2 with the first comparison value CMPA2 when the synchronization signal Sync3 is received to trigger a low-to-high switching operation when a condition is matched, a transition waveform may be generated in the PWM2 signal waveform, ensuring that the PWM2 signal is switched from low to high before the timer value is updated based on the target phase setting value PHS2 written in the phase register of the timer 2, shortening the time to continue with the low signal.

Upon receiving the second synchronization signal Sync2, the target phase setting PHS of the phase register value written to the timer 2 may be the same as PHS1 upon receiving the first synchronization signal Sync1, the period PWM2 signal remaining identical to the PWM2 signal within the PWM period in which the first synchronization signal Sync1 is located. While receiving this second synchronization signal Sync2, the second comparison value CMPB2 may be set by writing a second comparator register value, and a switching operation between high and low levels of the PWM2 signal is performed when the timer value set at the timer 2 counts to match the second comparison value CMPB2, which is the same as the switching operation when the first comparison value CMPA2 matches. The second comparison value CMPB2 may be between the initial value 201 of the timer 2 and the previous phase setting value PHS1 of the timer, and in the PWM period in which the second synchronization signal Sync2 is located, since the timer value of the timer 2 has crossed the second comparison value CMPB2, the switching operation of the high and low levels of the PWM2 signal triggered by the comparison of the timer value with the second comparison value CMPB2 does not occur.

Upon receiving the third synchronization signal Sync3, the phase register of the timer 2 is written with a new target phase setting PHS 2. After the switching operation that triggers the high level to the low level when the PWM2 signal is counted by the timer 2 to the PRD2 at the end of the last PWM cycle, the timer 2 starts counting up from the initial value in a period until the third synchronization signal Sync3 is received, and triggers the same switching operation as the level switching operation triggered when the timer value matches the first comparison value CMPA2 when matching the second comparison value CMPB2, pulling the PWM2 signal back to the high level, as shown by the dotted line 205 of fig. 2. In this way, when the timer value of the timer 2 at the reception timing of the later third synchronization signal Sync3 is updated to the new target phase setting value PHS2 (see the timer value change curve portion jumping from the timer value 206 equal to PHS1 to PHS2 in fig. 2), the PWM2 signal is already in the high state even if the matching-triggered switching operation timing of the first comparison value CMPA2 is missed. Then at the end of the period, the timer value of timer 2 counts to the timer period value PRD2, and the PWM2 signal is switched from high to low, thus generating a complete phase-shifted waveform including the transition waveform. The adjusted phase-shifting waveform has normal duty ratio and quick response time, and the problem of waveform loss is effectively avoided.

Fig. 3 then shows a schematic flow diagram for controlling the phase shifting operation of an ePWM module based on an improved phase shifting control method according to an embodiment of the present disclosure.

At step S310, the phase shift control method of the ePWM module is started.

First, in step S320, the module is initialized with PWM and control parameters, for example, the first comparison value CMPA1 of the first PWM signal PWM1, the initial value of the timer 1 and the timer period value PRD1, the first comparison value CMPA2 of the second PWM signal PWM2, the initial value of the timer 2 and the timer period value PRD2 are set.

In step S330, a target phase setting PHS2 corresponding to a desired phase of the second PWM signal PWM2 with respect to the reference PWM signal PWM1 may be calculated by the phase input controller.

In step S340, it is determined whether the target phase setting PHS2 causes a transition between a leading phase and a lagging phase of the PWM2 signal compared to the phase difference of the PWM1 signal, and whether the previous phase setting value of the timer is in a first interval between the initial value and the CMPA and the target phase setting value is in a second interval between the CMPA and the timer period value.

If the determination result in step S340 is that there is no transition (no in branch of fig. 3), i.e., the target setting PHS2 of the timer does not cause the phase difference of the second PWM signal PWM2 to transition between the leading and lagging phases, and the setting of the timer does not cross CMPA2 from the first section and enter the second section, so that there is no loss of the PWM drive waveform, the method proceeds to step S380, writes the target phase setting PHS2 into the timer register directly at the time of the synchronization signal reception, updates the timer value to the target phase setting PHS2, and returns to step S330 to wait for the next calculation of the target phase setting of the PWM2 signal corresponding to the desired phase.

If the determination at step S340 is that there is a transition (as in branch yes of fig. 3), the method proceeds to step S350. The ePWM module first turns on the PWM interrupt of the second PWM signal PWM2 to perform the modified phase shift control operation step S360.

Step S360 may include the following substeps, respectively:

s361: in the next first PWM cycle, a 0 is written to the phase register of timer 2 upon receipt of the synchronization signal, with the purpose of setting the phase setting value to 0 so that there is no phase shift in the next cycle, in preparation for the transition waveform. The 0 value setting of the above-described phase register is used to set the phase of the second PWM signal PWM2 to be the same as the phase of the reference signal PWM 1. According to the embodiments of the present disclosure, phase synchronization (i.e., no phase shift) between the two PWM signals can be satisfied as long as the phase setting of the PWM2 signal is set to be the same as the initial phase setting of the reference signal PWM 1.

S362: the target phase setting PHS2 calculated in step S330 is written in the phase register in the second PWM cycle, so that the next cycle outputs the PWM2 signal with the desired leading phase. While a second comparison value CMPB2 for generating a transition waveform within the present PWM period is calculated. According to embodiments of the present disclosure, CMPB2 may be calculated using the following formula:

the PHS1 is the previous phase setting value of the PWM2 signal, and the PHS2 is the target phase setting value of the PWM2 signal. This ensures that there is a complete high or low waveform of the PWM2 signal before the end of the second PWM period without causing fluctuations in duty cycle, e.g., as shown in fig. 2, the high waveform after the dashed line 205 has the same duration as the subsequent level waveform, thus ensuring that the PWM2 signal has the same duty cycle at the beginning of the dashed line 205. The above formula can minimize the loss of duty cycle. Other ways of calculating CMPB2 may also exist, depending on the embodiment.

S363: in the third PWM cycle, the second comparison value CMPB2 is restored to half of the PRD2, avoiding its effect on the normal PWM waveform output.

After step S360 is completed, the method turns off the PWM interrupt in step S370, so that the ePWM module performs automatic operation to smoothly complete the transition process between the lag phase and the lead phase.

Through the improved phase shift control operation, when a transition from a lagging phase to a leading phase exists between a target phase setting value and a previous phase setting value input aiming at a PWM signal, the ePWM module outputs a PWM signal waveform without a part of waveform, the duty ratio of the PWM signal is ensured to be set and changed in a desired mode, and stable and safe circuit element driving is realized.

According to an embodiment of the present disclosure, an apparatus 400 for phase shift control of an ePWM module is also presented, as shown in fig. 4. The apparatus 400 may have a processor 401 and a memory 402. The processor 401 may be configured to perform the steps of the dephasing control method for the ePWM module as described above. The memory 402 may be configured to store data and commands necessary to perform the above-described steps.

In accordance with embodiments of the present disclosure, the apparatus for dephasing control of an ePWM module may also take the form of a more complete apparatus 500 as shown in FIG. 5. The apparatus 500 shown in fig. 5 is only an example and should not bring any limitations to the function and scope of use of the disclosed embodiments. The apparatus 500 is embodied in a general purpose computing device. The components of apparatus 500 may include, but are not limited to: at least one processing unit 510, at least one memory unit 520, a bus 530 that couples various system components including the memory unit 520 and the processing unit 510, a display unit 540, and the like.

Wherein the memory unit stores program code executable by the processing unit 510 to cause the processing unit 510 to perform steps according to various exemplary embodiments of the present disclosure as described in the methods of the present specification for phase shift control of ePWM modules. For example, the processing unit 510 may perform the steps as shown in fig. 3.

The memory unit 520 may include a readable medium in the form of a volatile memory unit, such as a random access memory unit (RAM)5201 and/or a cache memory unit 5202, and may further include a read only memory unit (ROM) 5203.

The memory unit 520 may also include a program/utility 5204 having a set (at least one) of program modules 5205, such program modules 5205 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which, or some combination thereof, may comprise an implementation of a network environment.

Bus 530 may be one or more of any of several types of bus structures including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

The apparatus 500 may also communicate with one or more external devices 600 (e.g., keyboard, pointing device, bluetooth device, etc.), with one or more devices that enable a user to interact with the apparatus 500, and/or with any devices (e.g., router, modem, etc.) that enable the apparatus 500 to communicate with one or more other computing devices. Such communication may occur via input/output (I/O) interfaces 550. Also, the apparatus 500 may communicate with one or more networks (e.g., a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network, such as the internet) via the network adapter 560. The network adapter 560 may communicate with other modules of the device 500 via the bus 530. It should be appreciated that although not shown in the figures, other hardware and/or software modules may be used in conjunction with the apparatus 500, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, among others.

Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein may be implemented by software, or by software in combination with necessary hardware. Therefore, the technical solution according to the embodiments of the present disclosure may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (which may be a CD-ROM, a usb disk, a removable hard disk, etc.) or on a network, and includes several instructions to cause a processor or a computing device (which may be a personal computer, a server, or a network device, etc.) to execute the steps of the method for phase shift control of an ePWM module according to the embodiments of the present disclosure.

In an exemplary embodiment of the disclosure, a computer-readable storage medium is also provided, on which a computer program is stored, the program comprising executable instructions that, when executed by, for example, a processor, may implement the steps of the method for dephasing control of an ePWM module described in any of the above embodiments. In some possible implementations, various aspects of the disclosure may also be implemented in the form of a program product comprising program code for causing a terminal device to perform the steps according to various exemplary embodiments of the disclosure described in this specification for a method of dephasing control of an ePWM module, when the program product is run on the terminal device.

The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

The computer readable storage medium may include a propagated data signal with readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A readable storage medium may also be any readable medium that is not a readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a readable storage medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Program code for carrying out operations for the present disclosure may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., through the internet using an internet service provider).

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.